CPU Architectures Research Articles

Faster Montgomery multiplication and Multi-Scalar-Multiplication for SNARKs

The bottleneck in the proving algorithm of most of elliptic-curve-based SNARK proof systems is the Multi-Scalar-Multiplication (MSM) algorithm. In this paper we give an overview of a variant of the Pippenger MSM algorithm together with a set of optimizations tailored for curves that admit a twisted Edwards form. We prove that this is the case for SNARK-friendly chains and cycles of elliptic curves, which are useful for recursive constructions. Our contribution is twofold: first, we optimize the arithmetic of finite fields by improving on the well-known Coarsely Integrated Operand Scanning (CIOS) modular multiplication. This is a contribution of independent interest that applies to many different contexts. Second, we propose a new coordinate system for twisted Edwards curves tailored for the Pippenger MSM algorithm.Accelerating the MSM over these curves is critical for deployment of recursive proof< systems applications such as proof-carrying-data, blockchain rollups and blockchain light clients. We implement our work in Go and benchmark it on two different CPU architectures (x86 and arm64). We show that our implementation achieves a 40-47% speedup over the state-of-the-art implementation (which was implemented in Rust). This MSM implementation won the first place in the ZPrize competition in the open division “Accelerating MSM on Mobile” and will be deployed in two real-world applications: Linea zkEVM by ConsenSys and probably Celo network.

Enimanal: Augmented cross-architecture IoT malware analysis using graph neural networks

IoT malware analysis is crucial for understanding the behavior and purpose of malware samples. While deep learning methods have been applied to IoT malware analysis using sequences or graphs to represent system calls, these approaches have limitations in their semantic representation of system call names. This paper presents Enimanal, a novel cross-architecture IoT malware analysis method based on graph neural networks. Enimanal leverages information from the Linux Programmer Manual to improve the semantic representation of dynamic system call information. By fusing semantic and structural information, Enimanal constructs a unique feature representation called an attributed system call graph (ASCG). We evaluated Enimanal on a dataset of 63k IoT malware samples with 9 CPU architectures and find that it outperforms comparison methods by up to 46% in macro precision and 38% in macro recall, achieving macro precision, macro recall and macro f1-score of over 98%. Furthermore, we verify the robustness of Enimanal against “zero-day” IoT malware.

Improving performance of SYCL applications on CPU architectures using LLVM‐directed compilation flow

SummaryThe wide adoption of SYCL as an open‐standard API for accelerating C++ software in domains such as HPC, automotive, artificial intelligence, machine learning, and other areas necessitates efficient compiler and runtime support for a growing number of different platforms. Existing SYCL implementations provide support for various devices like CPUs, GPUs, DSPs, FPGAs and so forth, typically via OpenCL or CUDA backends. While accelerators have increased the performance of user applications significantly, employing CPU devices for further performance improvement is beneficial due to the significant presence of CPUs in existing data‐centers. SYCL applications on CPUs, currently go through an OpenCL backend. Though an OpenCL backend is valuable in supporting accelerators, it may introduce additional overhead for CPUs since the host and device are the same. Overheads like a run‐time compilation of the kernel, transferring of input/output memory to/from the OpenCL device, invoking the OpenCL kernel and so forth, may not be necessary when running on the CPU. While some of these overheads (such as data transfer) can be avoided by modifying the application, it can introduce disparity in the SYCL application's ability to achieve performance portability on other devices. In this article, we propose an alternate approach to running SYCL applications on CPUs. We bypass OpenCL and use a CPU‐directed compilation flow, along with the integration of whole function vectorization to generate optimized host and device code together in the same translation unit. We compare the performance of our approach—the CPU‐directed compilation flow, with an OpenCL backend for existing SYCL‐based applications, with no code modification for BabelStream benchmark, Matmul from the ComputeCpp SDK, N‐body simulation benchmarks and SYCL‐BLAS (Aliaga et al. Proceedings of the 5th International Workshop on OpenCL; 2017.), on CPUs from different vendors and architectures. We report a performance improvement of up to on BabelStream benchmarks, up to on Matmul, up to on the N‐body simulation benchmark and up to 16% on SYCL‐BLAS.

Mdapy: A flexible and efficient analysis software for molecular dynamics simulations

The mdapy is a library for pre- and postprocessing molecular dynamics simulation data. Benefitting from the just-in-time compile technology of TaiChi mdapy can be written in pure Python while possessing similar speed to those written in C++. mdapy is designed with highly paralleled and makes full advantages of modern computer resources on both multicore CPU and GPU architecture. The package implements a fast module to find the neighbors of particles in both free and periodic boundaries, based on which it offers a wide variety of methods to analyze atomic environments, such as standard centrosymmetry parameters, radial distribution function and newer methods, such as atomic entropy fingerprint. In addition, mdapy can be used to create the geometric structure of polycrystals with metallic or graphene grain boundaries by Voronoi diagram. mdapy can directly read the DUMP and DATA format defined in LAMMPS code, and, in practice, it accepts any other format by converting it into NumPy ndarray format. This design philosophy enables seamless integration with abundant scientific ecosystems in the Python community and easy cooperation with other analysis codes like OVITO or freud. Program summaryProgram Title: mdapyCPC Library link to program files:https://doi.org/10.17632/dtdkxvcsc9.1Developer's repository link:https://github.com/mushroomfire/mdapyCode Ocean capsule:https://codeocean.com/capsule/5271472Licensing provisions: BSD 3-clauseProgramming language: Python, C++Nature of problem: Atomic environment analysis and generation of the initial structure are important in molecular dynamics simulations. Many analysis methods relying on particle neighbors, such as radial distribution functions and atomic entropy, are computationally intensive and need to be carefully implemented to scale to large systems. Traditional code is often written in C++ or Fortran to guarantee performance while causing difficulty in installation and secondary development due to the complexity of the programming language.Solution method: mdapy is written in parallel to quickly perform neighbor finding, provides a set of analysis methods and creates an atomic geometry structure on multicore CPU and GPU. Over 95 percent of mdapy is written in Python with a uniform API to call. All data are stored in NumPy ndarray, making users easy to install, use and secondary develop.Additional comments including restrictions and unusual features:1. mdapy provides fast parallel implementations of neighbor finding in periodic and free boundary system.2. mdapy can generate a polycrystalline model with graphene grain boundaries.3. mdapy is helpful for analyzing the melting process by the mean squared displacement and Lindemann index at the atomic level.4. mdapy is very easy to install via pip install mdapy without any compile steps and can be run on Windows, Linux and Mac OS with Python 3.7-3.10.5. mdapy has detailed documentation to make it easier to use.

Exploring the performance and portability of the k-means algorithm on SYCL across CPU and GPU architectures

The aim of SYCL is to reduce the gap between the performance and code portability of the main accelerators used in HPC, such as multi-vendor CPUs, GPUs, and FPGAs. To evaluate SYCL’s performance portability, this paper uses the k-means algorithm as a case study. The k-means algorithm is simple to code but can be complex to optimize. In this research, we compare our developed SYCL version with the most efficient implementations of CUDA and OpenMP. Our resulting SYCL code can potentially run on multi-vendor CPUs and GPUs. Additionally, we have created a hand-tuned SYCL variation that is optimized for specific device architectures (CPU, NVIDIA GPU, and Intel GPU) to evaluate the performance difference between a standard version and an optimized one. The results show that SYCL outperforms Intel GPUs and CPUs compared to the state-of-the-art He-Vialle version, while on NVIDIA GPUs SYCL offers equivalent performance compared to its native CUDA implementation.

A Comprehensive Memory Management Framework for CPU-FPGA Heterogenous SoCs

Efficient utilization of restrained memory resources is of paramount importance in CPU-FPGA heterogeneous multiprocessor system-on-chip (HMPSoC)-based system design for memory-intensive applications. State-of-the-art high level synthesis (HLS) tools rely on the system programmers to manually determine the data placement within the complex memory hierarchy. Different data placement policies may lead to different system performance, and finding an optimal data placement policy is a nontrivial problem. For instance, we show counter-intuitive results that traditional frequency and locality-based data placement strategy designed for CPU architecture leads to nonoptimal system performance in CPU-FPGA HMPSoCs. In this work, we first propose an automatic data placement framework for field programmable gate array (FPGA) kernels to determine whether each array object should be accessed via the on-chip BRAM, shared CPU L2-cache, or DDR memory to achieve the optimal performance. Moreover, we find that when the CPU kernel and the FPGA kernel are executed in parallel, memory contentions may degrade the performance and the optimal data placement policy designed for the FPGA kernel alone will not achieve the optimal overall system performance. In this article, we proposed to use cache partitioning to alleviate the impact brought by memory contentions. We extend the framework designed for FPGA by adding the cross-layer memory contentions analysis to automatically generate an optimal data placement policy and cache partitioning mechanism for the parallel executing kernels. The proposed data placement framework can be seamlessly integrated with the commercial Vivado HLS. The experimental results on the Zedboard platform show an average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times $ </tex-math></inline-formula> performance speedup for FPGA kernels compared with a greedy-based allocation strategy. When FPGA kernels and CPU kernels are executed in parallel, the FPGA kernel and the CPU kernel have a performance speedup of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.62\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.10\times $ </tex-math></inline-formula> on average, respectively.

RegGuard: Leveraging CPU registers for mitigation of control- and data-oriented attacks

CPU registers are small discrete storage units that are used to store temporary data and instructions within the CPU. Registers are not addressable in the same way memory is, which makes them immune to memory attacks and manipulation by other means. In this paper, we take advantage of this to protect critical program data with integrity guarantees that cover register spills. This protection effectively addresses control- and data-oriented attacks targeting the stack, even by adversaries with the full knowledge of program memory. Our solution RegGuard is a software-based mitigation technique that uses existing CPU registers and cryptographic primitives to protect critical variables with hardware-level assurance. Unlike conventional register allocation methods, RegGuard prioritises the security significance of a register candidate over its expected performance gain. Our scheme also deals effectively with saved registers to the stack, i.e., when the compiler frees registers to make room for the variables of a new call. With RegGuard, register values saved to the stack are protected, including strong adversaries with arbitrary read and write access capabilities. While our primary design focus is on security, performance is important for a scheme to be adopted in practice. RegGuard is still benefiting from the performance gain normally associated with register allocations and provides practical protection. Despite being adaptable to different CPU architectures, we showcase the performance of RegGuard using different benchmark programs and the C library on the ARM64 architecture as a proof-of-concept.

BitBrain and Sparse Binary Coincidence (SBC) memories: Fast, robust learning and inference for neuromorphic architectures.

We present an innovative working mechanism (the SBC memory) and surrounding infrastructure (BitBrain) based upon a novel synthesis of ideas from sparse coding, computational neuroscience and information theory that enables fast and adaptive learning and accurate, robust inference. The mechanism is designed to be implemented efficiently on current and future neuromorphic devices as well as on more conventional CPU and memory architectures. An example implementation on the SpiNNaker neuromorphic platform has been developed and initial results are presented. The SBC memory stores coincidences between features detected in class examples in a training set, and infers the class of a previously unseen test example by identifying the class with which it shares the highest number of feature coincidences. A number of SBC memories may be combined in a BitBrain to increase the diversity of the contributing feature coincidences. The resulting inference mechanism is shown to have excellent classification performance on benchmarks such as MNIST and EMNIST, achieving classification accuracy with single-pass learning approaching that of state-of-the-art deep networks with much larger tuneable parameter spaces and much higher training costs. It can also be made very robust to noise. BitBrain is designed to be very efficient in training and inference on both conventional and neuromorphic architectures. It provides a unique combination of single-pass, single-shot and continuous supervised learning; following a very simple unsupervised phase. Accurate classification inference that is very robust against imperfect inputs has been demonstrated. These contributions make it uniquely well-suited for edge and IoT applications.

Design of a nonvolatile-register-embedded RISC-V CPU with software-controlled data-retention and hardware-acceleration functions

This paper describes the design of a nonvolatile CPU based on RISC-V that is an open-source and highly flexible instruction set architecture. This CPU incorporates nonvolatile registers utilizing magnetic tunnel junction (MTJ) device, as well as custom instructions specific to the control of these nonvolatile registers and an accelerator module embedded into the CPU architecture. These techniques enable efficient execution of intermittent operations suitable for energy-limited internet-of-things (IoT) applications. Through performance evaluation of the CPU designed in a 55-nm CMOS/MTJ-hybrid process technology, we show that our CPU can save up to 56.9% of power consumption compared to conventional ones, with an average power consumption of 3.91 μW/MHz.

An evaluation of Kd-Trees vs Bounding Volume Hierarchy (BVH) acceleration structures in modern CPU architectures

Ray tracing is a rendering technique that is highly praised for its realism and image quality. Nonetheless, this is a computationally intensive task that is slow compared to other rendering techniques like rasterization. Bounding Volume Hierarchy (BVH) is a primitive subdivision acceleration mechanism that is the mainly used method for accelerating ray tracing in modern solutions. It is regarded as having better performance against other acceleration methods. Another well-known technique is Kd-Trees that uses binary space partitioning to adaptively subdivide space with planes. In this research, we made an up-to-date evaluation of both acceleration structures, using state-of-the-art BVH and Kd-Trees algorithms implemented in C, and found out that the Kd-Trees acceleration structure provided better performance in all defined scenarios on a modern x86 CPU architecture.

Areion: Highly-Efficient Permutations and Its Applications to Hash Functions for Short Input

In the real-world applications, the overwhelming majority of cases require hashing with relatively short input, say up to 2K bytes. The length of almost all TCP/IP packets is between 40 to 1.5K bytes, and the maximum packet lengths of major protocols, e.g., Zigbee, Bluetooth low energy, and Controller Area Network (CAN) are less than 128 bytes. However, existing schemes are not well optimized for short input. To bridge the gap between real-world needs (in future) and limited performances of state-of-the-art hash functions for short input, we design a family of wide-block permutations Areion that fully leverages the power of AES instructions, which are widely deployed in many devices. As its applications, we propose several hash functions. Areion significantly outperforms existing schemes for short input and even competitive to relatively long message. Indeed, our hash function is surprisingly fast, and its performance is less than 3 cycles/byte in the latest Intel architecture for any message size. Especially, it is about 10 times faster than existing state-of-the-art schemes for short message up to around 100 bytes, which are most widely-used input size in real-world applications, on both the latest CPU architectures (IceLake, Tiger Lake, and Alder Lake) and mobile platforms (Pixel 6 and iPhone 13).

Automatic segmentation and parallel phased least squares for highly efficient geodetic network parameter estimation

This paper describes a novel automatic segmentation algorithm and parallel phased least squares strategy. These developments have been motivated by a requirement to repeatedly estimate extremely large parameter sets from massive and constantly changing geodetic networks in a highly efficient manner. The challenge of solving parameter sets efficiently, together with the inverse of the normal equations to obtain the full matrix of parameter estimate precisions, may be addressed by using highly optimised parallel matrix factorisation libraries. While offering notable reductions in time on multi-core CPU architectures, the simultaneous solution of extremely large measurement sets still requires excessive amounts of time and computational resources (if attainable). Historically, the challenge has been addressed by geodesists through a range of Helmert blocking or matrix partitioning techniques and sequential least squares models. While capable of producing rigorous parameter estimates, certain methods suffer from computational inefficiency; implementation complexity; inflexibility in re-forming the parameterised expressions upon the introduction of new measurements or non-rigorous variance matrices. Tienstra's phased least squares method is able to overcome all of the aforementioned problems, provided an efficient and flexible process is available for rigorously subdividing the parameters and measurements. In this contribution, we present an automatic segmentation algorithm and a strategy for parallelising Tienstra's phased least squares method using a dynamic scheduling queue. These developments offer a breakthrough in geodetic methodology, in that for the first time they allow for the rigorous solution of both parameters and variances from massive systems of observation equations subject to continual change in an adaptive and highly efficient manner.

YaConv: Convolution with Low Cache Footprint

This article introduces YaConv , a new algorithm to compute convolution using GEMM microkernels from a Basic Linear Algebra Subprograms library that is efficient for multiple CPU architectures. Previous approaches either create a copy of each image element for each filter element or reload these elements into cache for each GEMM call, leading to redundant instances of the image elements in cache. Instead, YaConv loads each image element once into the cache and maximizes the reuse of these elements. The output image is computed by scattering results of the GEMM microkernel calls to the correct locations in the output image. The main advantage of this new algorithm—which leads to better performance in comparison to the existing im2col approach on several architectures—is a more efficient use of the memory hierarchy. The experimental evaluation on convolutional layers from PyTorch, along with a parameterized study, indicates an average 24% speedup over im2col convolution. Increased performance comes as a result of 3× reduction in L3 cache accesses and 2× fewer branch instructions.

Time series analysis acceleration with advanced vectorization extensions

Time series analysis is an important research topic and a key step in monitoring and predicting events in many fields. Recently, the Matrix Profile method, and particularly two of its Euclidean-distance-based implementations—SCRIMP and SCAMP—have become the state-of-the-art approaches in this field. Those algorithms bring the possibility of obtaining exact motifs and discords from a time series, which can be used to infer events, predict outcomes, detect anomalies and more. While matrix profile is embarrassingly parallelizable, we find that auto-vectorization techniques fail to fully exploit the SIMD capabilities of modern CPU architectures. In this paper, we develop custom-vectorized SCRIMP and SCAMP implementations based on AVX2 and AVX-512 extensions, which we combine with multithreading techniques aimed at exploiting the potential of the underneath architectures. Our experimental evaluation, conducted using real data, shows a performance improvement of more than 4times with respect to the auto-vectorization.

Bringing Compiling Databases to RISC Architectures

Current hardware development greatly influences the design decisions of modern database systems. For many modern performance-focused database systems, query compilation emerged as an integral part and different approaches for code generation evolved, making use of standard compilers, general-purpose compiler libraries, or domain-specific code generators. However, development primarily focused on the dominating x86-64 server architecture; but neglected current hardware developments towards other CPU architectures like ARM and other RISC architectures. Therefore, we explore the design space of code generation in database systems considering a variety of state-of-the-art compilation approaches with a set of qualitative and quantitative metrics. Based on our findings, we have developed a new code generator called FireARM for AArch64-based systems in our database system, Umbra. We identify general as well as architecture-specific challenges for custom code generation in databases and provide potential solutions to abstract or handle them. Furthermore, we present an extensive evaluation of different compilation approaches in Umbra on a wide variety of x86-64 and ARM machines. In particular, we compare quantitative performance characteristics such as compilation latency and query throughput. Our results show that using standard languages and compiler infrastructures reduces the barrier to employing query compilation and allows for high performance on big data sets, while domain-specific code generators can achieve a significantly lower compilation overhead and allow for better targeting of new architectures.

Hierarchical cache configuration based on hybrid SOT- and STT-MRAM

With the rapid growth of big data information and the continuous iteration progress of CPU architecture, the implementation of a new memory-based cache architecture is urgent and challenging. In the paper, a CPU cache architecture system based on MRAM is built. Firstly, the performance of SRAM, STT-MRAM and SOT-MRAM as caches from 8 kb to 32 Mb is evaluated. Secondly, by summarizing the performance of SRAM and MRAM in different cache levels, a new quad-core CPU cache architecture design scheme with SOT-MRAM as the first level of cache and STT-MRAM as the second level of cache is determined. Thirdly, the built cache system is simulated. A non-inclusive strategy is proposed to replace the inclusive strategy in order to solve the problem of high dynamic energy of STT-MRAM at the second level. The idea of having a quad-core CPU dynamically share the second-level cache is proposed in the paper. Finally, the caching system in the paper is compared with the other previous works, showing up to 60.78% energy consumption advantage and 33.22% leakage power advantage. The proposed MRAM-based CPU cache system and the corresponding cache strategy have potential application with the benefits of low power and less area.

Evolving CPU Architectures for AI

Evolving CPU Architectures for AI

A Review of Vedic Mathematics for the Design of High-Speed Arithmetic RISC Processors

Vedic Mathematics is a collection of techniques and concepts developed from ancient Indian mathematical books known as the Vedas. These strategies are designed to make different mathematical computations easier and faster. High-throughput RISC Processor Design, on the other hand, includes the creation of processors that prioritize the execution of a high number of instructions per unit of time. If there have been breakthroughs relating to Vedic Mathematics and High-Throughput RISC Processor Design, it would be intriguing to investigate how these old mathematical ideas may be utilized to improve the efficiency of current processor designs. Give a summary of the work, stressing the potential benefits and drawbacks of incorporating Vedic Mathematics concepts into the design of High-Throughput RISC computers. Introduce Vedic Mathematics and High-Throughput RISC Processor Design separately. Explain briefly why you're looking at incorporating Vedic Mathematics into CPU architecture. Outline key Vedic Mathematics concepts that may be applied to processor design. What distinguishes these ideas from typical mathematical approaches Provide an overview of the fundamental ideas and issues involved in the design of high-throughput RISC processors. Emphasize the critical areas for improvement and integrating principles from Vedic Mathematics into Processor Architecture: Investigate the use of Vedic Mathematics principles in processor architecture to discuss how these concepts may be utilized to solve specific problems or improve aspects of high-throughput RISC architectures. The importance of multipliers in Arithmetic Unit performance is underlined. The incorporation of Vedic Science, an ancient mathematical system comprised of 16 Sutras, implies a fresh method for arithmetic computations. The suggestion comprises optimizing the Vedic multiplier type Urdhva Triyakbhyam by substituting Convey Save Viper for the usual carry. This is done to reduce delays caused by standard adders and incomplete products aspire to outperform traditional designs in terms of speed. The explicit data on the speed gains is obtained and how they were assessed will bolster the claims and utilization of the proposed proficient Vedic multiplier in the number juggling module of the RISC processor. In addition, stating its application in the field of digital signal processing (DSP) broadens the scope of work. Validation of RTLs and FPGAs for the Register-Transfer Level (RTL) implementation of the proposed Math Unit in VHDL, paired with simulation using Xilinx ISE EDA tools, is a useful step in verifying the design. Validation on an FPGA device, especially a Vertex-IV, provides credibility to the suggested solution.

Exploring Fine-Grained In-Memory Database Performance for Modern CPUs

Modern CPUs keep integrating more cores and large size cache, which is beneficial for in-memory databases to improve parallel processing power and cache locality. While state-of-the-art CPUs have diverse architectures and roadmaps such as large core count and large cache size (AMD x86), moderate core count and cache size (intel x86), large core count and moderate cache size (ARM), exploring in-memory databases performance characteristics for different CPU architectures is important for in-memory database designs and optimizations. In this paper, we develop a fine-grained in-memory database benchmark to evaluate the performance of each operator on different CPUs to explore how CPU hardware architectures influence performance. Different from well known conclusions that more cores and larger cache size can achieve higher performance, we find out that the micro cache architectures play an important role opposite to core count and cache size, the shared monolithic L3 cache with moderate size beats large disaggregated L3 cache. The experiments also show that predicting operator performance on different CPUs is difficult according to diverse CPU architectures and micro cache architectures, and different implementations of each operator are not always high or low with interleaved strong and weak performance regions influenced by CPU hardware architectures. Intel x86 CPUs represent cache-centric processor design, while AMD x86 and ARM CPUs represent computing-centric processor design, the OLAP benchmark experiments of SSB discover that OmniSciDB and OLAP Accelerator with vector-wise processing model performs well on intel x86 CPUs compared to AMD x86 CPUs and the JIT compliant based Hyper prefers to AMD x86 CPUs rather than intel x86 CPUs. The CPU roadmaps of increasing cores or improving cache locality should be considered for in-memory database algorithm design and platform selection.

An Investigation of Heterogeneous Embedded CPU and GPU Architectures

Edge detection using the Canny method is popular. The Canny method’s calculation is too complex for traditional embedded systems, preventing real-time edge recognition. High-end embedded CPUs with GPGPUs can process more data (General Purpose Graphics Processing Units). This research proposes a distributed computing-friendly parallel canny technique.