Single Stuck-at Fault Coverage Research Articles

Test Response Compaction via Output Bit Selection

The conventional output compaction methods based on XOR-networks and/or linear feedback shift registers may suffer from the problems of aliasing, unknown-values, and/or poor diagnosability. In this paper, we present an alternative method called the output-bit-selection method to address the test compaction problem. By observing only a subset of output responses, this method can effectively deal with all the above-mentioned problems. Efficient algorithms that can identify near optimum subsets of output bits to cover all detectable faults in very large circuits are developed. Experimental results show that less than 10% of the output response bits of an already very compact test set are enough to achieve 100% single stuck-at fault coverage for most ISCAS benchmark circuits. Even better results are obtained for ITC 99 benchmark circuits as less than 3% of output bits are enough to cover all stuck-at faults in these circuits. The increase ratio of selected bits to cover other types of faults is shown to be quite small if these faults are taken into account during automatic test pattern generation. Furthermore, the diagnosis resolution of this method is almost the same as that achieved by observing all output response bits.

A test set embedding approach based on twisted-ring counter with few seeds

Test data storage, test application time and test power dissipation increase dramatically for single stuck-at faults while tens of million gates are integrated in a System-on-a-Chip (SoC), which makes implementing fault testing for embedded cores based SoC become a challenging task. To further reduce test data storage, test application time and test power dissipation, this paper presents a new test set embedding approach based on twisted-ring counter (TRC) with few seeds. This approach includes two improvements. The first is that an efficient seed-selection algorithm is employed to exploit the high-density unspecified bits in the deterministic test set and so the test data storage for complete coverage of single stuck-at faults is minimized. The second is that a novel test-sequence-reduction scheme based on shifting seeds is proposed to reduce test application time that in turn reduces test power dissipation. Compared with the conventional approach, experiments on ISCAS’89 benchmark circuits show that the proposed approach requires 65% less test data storage, 68% shorter test application time and 67% less test power dissipation. Moreover, its hardware overhead is very small.

Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m)

This paper presents an algebraic testing method for detecting stuck-at faults in the polynomial-basis (PB) bit-parallel (BP) multiplier circuits over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ). The proposed technique derives the test vectors from the expressions of the inner product (IP) variables without any requirement of the ATPG tool. This low- complexity testing method requires (2m + 1) test vectors for detecting single stuck-at faults in the AND part and multiple stuck-at faults in the EXOR part of the multiplier circuits. The test vectors are independent of the multiplier's structure, as proposed in (T. A. Gulliver et al., 1991), but are dependent on m. For the multiplier circuits, the test set is found to be smaller in size than the ATPG-generated test set. The test set provides 100 percent single stuck-at fault coverage.

A BIST pattern generator design for near-perfect fault coverage

A new design methodology for a pattern generator is proposed, formulated in the context of on-chip BIST. The design methodology is circuit-specific and uses synthesis techniques to design BIST generators. The pattern generator consists of two components: a pseudorandom pattern generator (like an LFSR or, preferably, a GLFSR) and a combinational logic to map the outputs of the pseudorandom pattern generator. This combinational logic is synthesized to produce a given set of target patterns by mapping the outputs of the pseudorandom pattern generator. It is shown that, for a particular CUT, an area-efficient combinational logic block can be designed/synthesized to achieve 100 (or almost 100) percent single stuck-at fault coverage using a small number of test the This method is significantly different from weighted pattern generation and can guarantee testing of all hard-to-detect faults without expensive test point insertion. Experimental results on common benchmark netlists demonstrate that the fault coverage of the proposed pattern generator is significantly higher compared to conventional pattern generation techniques. The design technique for the logic mapper is unique and can be used effectively to improve existing pattern generators for combinational logic and scan-based BIST structures.

A minimal universal test set for self-test of EXOR-Sum-of-Products circuits

A testable EXOR-Sum-of-Products (ESOP) circuit realization and a simple, universal test set which detects all single stuck-at faults in the internal lines and the primary inputs/outputs of the realization are given. Since ESOP is the most general form of AND-EXOR representations, our realization and test set are more versatile than those described by other researchers for the restricted GRM, FPRM, and PPRM forms of AND-EXOR circuits. Our circuit realization requires only two extra inputs for controllability and one extra output for observability. The cardinality of our test set for an n input circuit is (n+6). For Built-in Self-Test (BIST) applications, we show that our test set can be generated internally as easily as a pseudorandom pattern and that it provides 100 percent single stuck-at fault coverage. In addition, our test set requires a much shorter test cycle than a comparable pseudoexhaustive or pseudorandom test set.

FsmTest: Functional test generation for sequential circuits

This paper presents a new approach to test pattern generation for sequential circuits modeled as finite state machines. This approach is well suited for controller synthesis, because such devices are usually represented as explicit finite state machines. Based on a functional fault model, only a restricted set of transitions of the finite state machine (FSM) is considered for the purpose of testing. A new state discriminating sequence, referred to as EUIO is proposed. Overlapping is accomplished to reduce the test length. In most cases, test length and CPU time requirements are substantially lower compared with gate-level ATPGs. Techniques are also introduced to preserve a high fault coverage. Evaluation on MCNC benchmarks has shown the effectiveness of the test algorithm both at functional and gate levels, while achieving in most cases 100% coverage of single stuck-at faults.

Defect level evaluation in an IC design environment

The purpose of this paper is to present a methodology for the evaluation of the Defect Level in an IC design environment. The methodology is based on the extension of Williams-Brown formula to nonequiprobable faults, which are collected from the IC layout, using the information on a typical IC process line defect statistics. The concept of weighted fault coverage is introduced, and the Defect Level (DL) evaluated for the Poisson and the negative binomial yield models. It is shown that DL depends on the critical areas associated with undetected faults, and their correspondent defect densities. Simulation results are presented, which highlight that the classic single Line Stuck-At (LSA) fault coverage is a unreliable metric of test quality. Moreover, results show that the efficiency of a given set of test patterns strongly depends on the physical design and defect statistics.

Microprocessor testability

As the level of microprocessor complexity increases to several hundred thousand transistors for a single-chip machine, it is becoming very difficult to test commercially available designs to the level of fault coverage desired by some customers. In order to achieve near 100-percent coverage of single stuck-at faults, future microprocessors must be designed with special testing features (designed for testability). The authors describe the testing problem for microprocessors, including the various methods of generating test sets and their application by the user. A survey of the testability features of some of today's commercially available microprocessors is presented. Suggestions for testability features for future-generation microprocessors are also discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>