Counter Research Articles

Bit-Sliced Implementation of SM4 and New Performance Records

SM4 is a popular block cipher issued by the Office of State Commercial Cryptography Administration (OSCCA) of China. In this paper, we use the bit-slicing technique that has been shown as a powerful strategy to achieve very fast software implementations of SM4. We investigate optimizations on two frontiers. First, we present a more efficient bit-sliced representation for SM4, which enables running 64 blocks in parallel with 256-bit registers. Second, we describe an optimized algorithm for data form transformations, also allowing efficient implementations of SM4 under Counter (CTR) mode and Galois/Counter mode. The above optimizations contribute to a significant performance gain on one core compared with the state-of-the-art results. This work is an extension of the conference paper at Inscrypt 2022, awarded the best paper award.

Assessment of Radiation-Induced Soft Errors on Lightweight Cryptography Algorithms Running on a Resource-Constrained Device

Most safety-critical edge-computing devices rely on lightweight cryptography (LWC) algorithms to provide security at minimum power and performance overhead. LWC algorithms are traditionally embedded as a hardware component, but with the advance of the Internet of Things (IoT), emerging firmware is more likely to support cryptography algorithms to comply with different security levels and industry-standards. This is the first work to present the soft error assessment of five cryptography algorithms executing in a low-power microprocessor running under neutron radiation, considering electronic code book (ECB) and counter (CTR) mode of operation implementations. Results obtained from two neutron radiation tests suggest that: ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</i> ) the NOEKEON algorithm gives the best relative soft error reliability, performance, power efficiency and memory footprint utilisation trade-offs between the five algorithms considering both ECB and CTR implementations, and ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ii</i> ) cryptography solutions based on the counter mode of operation present better FIT rate for silent data corruption (SDC) and crash w.r.t. ECB implementations.

Cloud-Assisted Image Double Protection System With Encryption and Data Hiding Based on Compressive Sensing

In this paper, we propose a compressive sensing(CS)-based scheme that combines encryption and data hiding to provide double protection to the image data in the cloud outsourcing. Different domain techniques are integrated for efficiency and security. After the data holder gets the sample of the raw data, he embeds watermark into sample and encrypts it, and then sends the protected sample to cloud for storage and recovery. Cloud cannot get any information about either the original data or watermark in the CS recovery process. Finally, users can extract the watermark and decrypt the data recovered by cloud directly in sparse domain. At the same time, after extracting the watermark, the image data of user will be closer to the original data compared with the data without extraction. Besides, the counter (CTR) mode is introduced to generate the measurement matrix of CS, which can improve security while avoiding the storage of measurement matrixes. The experimental results demonstrate that the scheme can provide both privacy protection and copyright protection with high efficiency.

Efficient Implementation of AES-CTR and AES-ECB on GPUs With Applications for High-Speed FrodoKEM and Exhaustive Key Search

The Advanced Encryption Standard (AES) is a standardized block cipher widely used to protect data confidentiality. Besides that, it can be used to generate pseudo-random numbers, which has many important applications. Recently, several works demonstrated the efficient implementations of AES electronics code book (ECB) and counter (CTR) mode on GPU platforms, achieving high throughput. In this brief, we set a speed record of AES implementation, which outperformed previous implementations. In particular, the proposed AES implementation achieved throughput 9&#x0025; (CTR) and 7&#x0025; (ECB) higher than the state-of-the-art, bit-sliced implementation. Moreover, the proposed technique does not require round keys to be embedded into the code during compilation, which is a serious limitation found in earlier work. The proposed technique also achieved up to 63&#x0025; higher throughput compared to another technique presented recently. Two use cases are presented here to verify the efficiency of the proposed AES implementation. Firstly, AES is used to generate random samples in a NIST post-quantum key encapsulation mechanism (KEM), achieving 3,350, 1,503 and 7,716 key exchanges per second on V100, T4, and RTX3080 GPUs respectively. This allows the proposed FrodoKEM implementation to be <inline-formula> <tex-math notation="LaTeX">$2.99\times $ </tex-math></inline-formula> faster than the state-of-the-art performance. The proposed AES implementation was also used in an exhaustive key search application, achieving 11,428, 3,969, and 9,998 <inline-formula> <tex-math notation="LaTeX">$\times 10^{6}$ </tex-math></inline-formula> encryptions per second on V100, T4, and RTX3080 GPUs, respectively.

A Flexible Electrochemical Biosensor Based on Modified Laser-Induced Graphene for Selective Detection of Phenazines

The opportunistic pathogen Pseudomonas aeruginosa (P. aeruginosa) is the main cause of various acute infections, especially in patients with severely burned and chronic infections. Moreover, P. aeruginosa can be found in lungs of patients with cystic fibrosis and in implanted devices.1 Biofilm of P. aeruginosa usually shows increased tolerance to antimicrobial agents.2,3 Among main virulence factors secreted by P. aeruginosa are pyocyanin (PYO) and phenazine-1-carboxylic acid (PCA) which belong to a group of quorum sensing molecules called phenazines. These phenazines also play an important role in the formation and growth of P. aeruginosa biofilms. As specific biomarkers of P. aeruginosa, detection of PYO and PCA can enable diagnosis of P. aeruginosa infection. Existing methods for detection of phenazines include high performance liquid chromatography-mass spectrometry (HPLC-MS),4 fluorescence measurements5, and electrochemical methods.6–8 But bulky and expensive instruments and the complex sample preparation process limit the broad application of the MS method. In addition, neither MS and fluorescence detection method can achieve in-situ monitoring of biofilm formation and growth. Compared to these methods, electrochemical sensors are low-cost, user-friendly, and compact. They also show the potential for in vivo monitoring.9 In this work, we have developed an all-in-one electrochemical sensor for selective identification of PYO and PCA down to 1 µM and 10 µM respectively in bacterial culture medium (brain heart infusion, BHI) using square wave voltammetry (SWV). The sensor working electrode (WE) is comprised of platinum (Pt) nanocrystals electrodeposited on laser-induced graphene (LIG). The counter (CE) and pseudo-reference electrode (RE) are based on LIG and electrodeposited silver (Ag) on LIG, respectively. We studied the effect of various electrodeposition conditions to optimize the material stability and sensor response. The fabrication process is facile, scalable, and user-friendly. The schematic of the fabrication process is shown in Figure 1a. The inset shows a picture of a fabricated sensor on polyimide. Figure 1b and Figure 1c show the SWV results for different concentrations of PYO and PCA in BHI. The oxidation peak for PYO and PCA are located at -0.15 V and -0.25 V, respectively, which enable selective identification of these phenazines. We studied the effect of SWV frequency on the sensor signal and found that 15 Hz and 10 Hz are the optimum frequency with the highest ratio of peak current to the baseline current for PYO and PCA, respectively. Compared to other electrochemical sensors based on gold7,10 or carbon,11 our sensor is flexible and integrates all three electrodes in a compact and scalable design.In conclusion, we successfully developed a printable flexible sensor based on LIG, modified using electrodeposition of platinum and silver to create a portable and compact three-electrode electrochemical device for selective detection of two phenazines (PYO and PCA) directly in bacterial culture broth. A limit of detection of 1 µM was achieved for PYO and 10 µM for PCA. To achieve a high sensitivity, the SWV frequency was optimized. The ability to identify both phenazines can advance our knowledge on how the interplay between these molecules affect biofilm phenotypes. Future works include improving the sensitivity through electrode engineering, growing P. aeruginosa biofilms on the sensors, and in situ monitoring of the pyocyanin level during biofilm growth. The flexibility of this sensor also promises its application in wearable technology or medical devices (e.g. for smart catheters, smart wound dressings, etc.). REFERENCES S. L. Percival et al., Wound Repair Regen., 20, 647–657 (2012) http://doi.wiley.com/10.1111/j.1524-475X.2012.00836.x.S. Subramanian, R. C. Huiszoon, S. Chu, W. E. Bentley, and R. Ghodssi, Biofilm, 2, 100015 (2020) https://www.sciencedirect.com/science/article/pii/S2590207519300152.S. E. Darch and D. Koley, Proc. R. Soc. A Math. Phys. Eng. Sci., 474, 20180405 (2018) https://royalsocietypublishing.org/doi/10.1098/rspa.2018.0405.M. Kushwaha et al., ACS Chem. Biol., 13, 657–665 (2018) https://pubs.acs.org/sharingguidelines.S. Fulaz et al., ACS Appl. Mater. Interfaces, 11, 32679–32688 (2019) https://pubs.acs.org/doi/abs/10.1021/acsami.9b09978.F. A. Alatraktchi et al., Y. K. Mishra, Editor. PLoS One, 13, e0194157 (2018) https://dx.plos.org/10.1371/journal.pone.0194157.L. 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Compact Implementation of ARIA on 16-Bit MSP430 and 32-Bit ARM Cortex-M3 Microcontrollers

In this paper, we propose the first ARIA block cipher on both MSP430 and Advanced RISC Machines (ARM) microcontrollers. To achieve the optimized ARIA implementation on target embedded processors, core operations of ARIA, such as substitute and diffusion layers, are carefully re-designed for both MSP430 (Texas Instruments, Dallas, TX, USA) and ARM Cortex-M3 microcontrollers (STMicroelectronics, Geneva, Switzerland). In particular, two bytes of input data in ARIA block cipher are concatenated to re-construct the 16-bit wise word. The 16-bit word-wise operation is executed at once with the 16-bit instruction to improve the performance for the 16-bit MSP430 microcontroller. This approach also optimizes the number of required registers, memory accesses, and operations to half numbers rather than 8-bit word wise implementations. For the ARM Cortex-M3 microcontroller, the 8×32 look-up table based ARIA block cipher implementation is further optimized with the novel memory access. The memory access is finely scheduled to fully utilize the 3-stage pipeline architecture of ARM Cortex-M3 microcontrollers. Furthermore, the counter (CTR) mode of operation is more optimized through pre-computation techniques than the electronic code book (ECB) mode of operation. Finally, proposed ARIA implementations on both low-end target microcontrollers (MSP430 and ARM Cortex-M3) achieved (209 and 96 for 128-bit security level, respectively), (241 and 111 for 192-bit security level, respectively), and (274 and 126 for 256-bit security level, respectively). Compared with previous works, the running timing on low-end target microcontrollers (MSP430 and ARM Cortex-M3) is improved by (92.20% and 10.09% for 128-bit security level, respectively), (92.26% and 10.87% for 192-bit security level, respectively), and (92.28% and 10.62% for 256-bit security level, respectively). The proposed ARIA–CTR implementation improved the performance by 6.6% and 4.0% compared to the proposed ARIA–ECB implementations for MSP430 and ARM Cortex-M3 microcontrollers, respectively.

Efficient Parallel Implementation of CTR Mode of ARX-Based Block Ciphers on ARMv8 Microcontrollers

With the advancement of 5G mobile telecommunication, various IoT (Internet of Things) devices communicate massive amounts of data by being connected to wireless networks. Since this wireless communication is vulnerable to hackers via data leakage during communication, the transmitted data should be encrypted through block ciphers to protect the data during communication. In addition, in order to encrypt the massive amounts of data securely, it is essential to apply one of secure mode of operation. Among them, CTR (CounTeR) mode is the most widely used in industrial applications. However, these IoT devices have limited resources of computing and memory compared to typical computers, so that it is challenging to process cryptographic algorithms that have computation-intensive tasks in IoT devices at high speed. Thus, it is required that cryptographic algorithms are optimized in IoT devices. In other words, optimizing cryptographic operations on these IoT devices is not only basic but also an essential effort in order to build secure IoT-based service systems. For efficient encryption on IoT devices, even though several ARX (Add-Rotate-XOR)-based ciphers have been proposed, it still necessary to improve the performance of encryption for smooth and secure IoT services. In this article, we propose the first parallel implementations of CTR mode of ARX-based ciphers: LEA (Lightweight Encryption Algorithm), HIGHT (high security and light weight), and revised CHAM on the ARMv8 platform, a popular microcontroller in various IoT applications. For the parallel implementation, we propose an efficient data parallelism technique and register scheduling, which maximizes the usage of vector registers. Through proposed techniques, we process the maximum amount of encryption simultaneously by utilizing all vector registers. Namely, in the case of HIGHT and revised CHAM-64/128 (resp. LEA, revised CHAM-128/128, and CHAM-128/256), we can execute 48 (resp. 24) encryptions simultaneously. In addition, we optimize the process of CTR mode by pre-computing and using the intermediate value of some initial rounds by utilizing the property that the nonce part of CTR mode input is fixed during encryptions. Through the pre-computation table, CTR mode is optimized up until round 4 in LEA, round 5 in HIGHT, and round 7 in revised CHAM. With the proposed parallel processing technique, our software provides 3.09%, 5.26%, and 9.52% of improved performance in LEA, HIGHT, and revised CHAM-64/128, respectively, compared to the existing parallel works in ARM-based MCU. Furthermore, with the proposed CTR mode optimization technique, our software provides the most improved performance with 8.76%, 8.62%, and 15.87% in LEA-CTR, HIGHT-CTR, and revised CHAM-CTR, respectively. This work is the fastest implementation of CTR mode on ARMv8 architecture to the best of our knowledge.

High-Speed Implementation of PRESENT on AVR Microcontroller

We propose the compact PRESENT on embedded processors. To obtain high-performance, PRESENT operations, including an add-round-key, a substitute layer and permutation layer operations are efficiently implemented on target embedded processors. Novel PRESENT implementations support the Electronic Code Book (ECB) and Counter (CTR). The implementation of CTR is improved by using the pre-computation for one substitute layer, two diffusion layer, and two add-round-key operations. Finally, compact PRESENT on target microcontrollers achieved 504.2, 488.2, 488.7, and 491.6 clock cycles per byte for PRESENT-ECB, 16-bit PRESENT-CTR (RAM-based implementation), 16-bit PRESENT-CTR (ROM-based implementation), and 32-bit PRESENT-CTR (ROM-based implementation) modes of operation, respectively. Compared with former implementation, the execution timing is improved by 62.6%, 63.8%, 63.7%, and 63.5% for PRESENT-ECB, 16-bit PRESENT-CTR (RAM based implementation), 16-bit PRESENT-CTR (ROM-based implementation), and 32-bit PRESENT-CTR (ROM-based implementation) modes of operation, respectively.

Parallel Implementations of ARX-Based Block Ciphers on Graphic Processing Units

With the development of information and communication technology, various types of Internet of Things (IoT) devices have widely been used for convenient services. Many users with their IoT devices request various services to servers. Thus, the amount of users’ personal information that servers need to protect has dramatically increased. To quickly and safely protect users’ personal information, it is necessary to optimize the speed of the encryption process. Since it is difficult to provide the basic services of the server while encrypting a large amount of data in the existing CPU, several parallel optimization methods using Graphics Processing Units (GPUs) have been considered. In this paper, we propose several optimization techniques using GPU for efficient implementation of lightweight block cipher algorithms on the server-side. As the target algorithm, we select high security and light weight (HIGHT), Lightweight Encryption Algorithm (LEA), and revised CHAM, which are Add-Rotate-Xor (ARX)-based block ciphers, because they are used widely on IoT devices. We utilize the features of the counter (CTR) operation mode to reduce unnecessary memory copying and operations in the GPU environment. Besides, we optimize the memory usage by making full use of GPU’s on-chip memory such as registers and shared memory and implement the core function of each target algorithm with inline PTX assembly codes for maximizing the performance. With the application of our optimization methods and handcrafted PTX codes, we achieve excellent encryption throughput of 468, 2593, and 3063 Gbps for HIGHT, LEA, and revised CHAM on RTX 2070 NVIDIA GPU, respectively. In addition, we present optimized implementations of Counter Mode Based Deterministic Random Bit Generator (CTR_DRBG), which is one of the widely used deterministic random bit generators to provide a large amount of random data to the connected IoT devices. We apply several optimization techniques for maximizing the performance of CTR_DRBG, and we achieve 52.2, 24.8, and 34.2 times of performance improvement compared with CTR_DRBG implementation on CPU-side when HIGHT-64/128, LEA-128/128, and CHAM-128/128 are used as underlying block cipher algorithm of CTR_DRBG, respectively.

Efficient Implementation of ARX-Based Block Ciphers on 8-Bit AVR Microcontrollers

As the development of Internet of Things (IoT), the data exchanged through the network has significantly increased. To secure the sensitive data with user’s personal information, it is necessary to encrypt the transmitted data. Since resource-constrained wireless devices are typically used for IoT services, it is required to optimize the performance of cryptographic algorithms which are computation-intensive tasks. In this paper, we present efficient implementations of ARX-based Korean Block Ciphers (HIGHT and LEA) with CounTeR (CTR) mode of operation, and CTR_DRBG, one of the most widely used DRBGs (Deterministic Random Bit Generators), on 8-bit AVR Microcontrollers (MCUs). Since 8-bit AVR MCUs are widely used for various types of IoT devices, we select it as the target platform in this paper. We present an efficient implementation of HIGHT and LEA by making full use of the property of CTR mode, where the nonce value is fixed, and only the counter value changes during the encryption. On our implementation, the cost of additional function calls occurred by the generation of look-up table can be reduced. With respect to CTR_DRBG, we identified several parts that do not need to be computed. Thus, precomputing those parts in offline and using them online can result in performance improvements for CTR_DRBG. Furthermore, we applied several optimization techniques by making full use of target devices’ characteristics with AVR assembly codes on 8-bit AVR MCUs. Our proposed table generation way can reduce the cost for building a precomputation table by around 6.7% and 9.1% in the case of LEA and HIGHT, respectively. Proposed implementations of LEA and HIGHT with CTR mode on 8-bit AVR MCUs provide 6.3% and 3.8% of improved performance, compared with the previous best results, respectively. Our implementations are the fastest compared to previous LEA and HIGHT implementations on 8-bit AVR MCUs. In addition, the proposed CTR_DRBG implementations on AVR provide better performance by 37.2% and 8.7% when the underlying block cipher is LEA and HIGHT, respectively.

ACE: ARIA-CTR Encryption for Low-End Embedded Processors.

In this paper, we present the first optimized implementation of ARIA block cipher on low-end 8-bit Alf and Vegard’s RISC processor (AVR) microcontrollers. To achieve high-speed implementation, primitive operations, including rotation operation, a substitute layer, and a diffusion layer, are carefully optimized for the target low-end embedded processor. The proposed ARIA implementation supports the electronic codebook (ECB) and the counter (CTR) modes of operation. In particular, the CTR mode of operation is further optimized with the pre-computed table of two add-round-key, one substitute layer, and one diffusion layer operations. Finally, the proposed ARIA-CTR implementations on 8-bit AVR microcontrollers achieved 187.1, 216.8, and 246.6 clock cycles per byte for 128-bit, 192-bit, and 256-bit security levels, respectively. Compared with previous reference implementations, the execution timing is improved by 69.8%, 69.6%, and 69.5% for 128-bit, 192-bit, and 256-bit security levels, respectively.

Highly Efficient Implementation of Block Ciphers on Graphic Processing Units for Massively Large Data

With the advent of IoT and Cloud computing service technology, the size of user data to be managed and file data to be transmitted has been significantly increased. To protect users’ personal information, it is necessary to encrypt it in secure and efficient way. Since servers handling a number of clients or IoT devices have to encrypt a large amount of data without compromising service capabilities in real-time, Graphic Processing Units (GPUs) have been considered as a proper candidate for a crypto accelerator for processing a huge amount of data in this situation. In this paper, we present highly efficient implementations of block ciphers on NVIDIA GPUs (especially, Maxwell, Pascal, and Turing architectures) for environments using massively large data in IoT and Cloud computing applications. As block cipher algorithms, we choose AES, a representative standard block cipher algorithm; LEA, which was recently added in ISO/IEC 29192-2:2019 standard; and CHAM, a recently developed lightweight block cipher algorithm. To maximize the parallelism in the encryption process, we utilize Counter (CTR) mode of operation and customize it by using GPU’s characteristics. We applied several optimization techniques with respect to the characteristics of GPU architecture such as kernel parallelism, memory optimization, and CUDA stream. Furthermore, we optimized each target cipher by considering the algorithmic characteristics of each cipher by implementing the core part of each cipher with handcrafted inline PTX (Parallel Thread eXecution) codes, which are virtual assembly codes in CUDA platforms. With the application of our optimization techniques, in our implementation on RTX 2070 GPU, AES and LEA show up to 310 Gbps and 2.47 Tbps of throughput, respectively, which are 10.7% and 67% improved compared with the 279.86 Gbps and 1.47 Tbps of the previous best result. In the case of CHAM, this is the first optimized implementation on GPUs and it achieves 3.03 Tbps of throughput on RTX 2070 GPU.

PAGE—Practical AES-GCM Encryption for Low-End Microcontrollers

An optimized AES (Advanced Encryption Standard) implementation of Galois Counter Mode of operation (GCM) on low-end microcontrollers is presented in this paper. Two optimization methods are applied to proposed implementations. First, the AES counter (CTR) mode of operation is speed-optimized and ensures constant timing. The main idea is replacing expensive AES operations, including AddRound Key, SubBytes, ShiftRows, and MixColumns, into simple look-up table access. Unlike previous works, the look-up table does not require look-up table updates during the entire encryption life-cycle. Second, the core operation of Galois Counter Mode (GCM) is optimized further by using Karatsuba algorithm, compact register utilization, and pre-computed operands. With above optimization techniques, proposed AES-GCM on 8-bit AVR (Alf and Vegard’s RISC processor) architecture from short-term, middle-term to long-term security levels achieved 415, 466, and 477 clock cycles per byte, respectively.

Fast Number Theoretic Transform for Ring-LWE on 8-bit AVR Embedded Processor.

In this paper, we optimized Number Theoretic Transform (NTT) and random sampling operations on low-end 8-bit AVR microcontrollers. We focused on the optimized modular multiplication with secure countermeasure (i.e., constant timing), which ensures high performance and prevents timing attack and simple power analysis. In particular, we presented combined Look-Up Table (LUT)-based fast reduction techniques in a regular fashion. This novel approach only requires two times of LUT access to perform the whole modular reduction routine. The implementation is carefully written in assembly language, which reduces the number of memory access and function call routines. With LUT-based optimization techniques, proposed NTT implementations outperform the previous best results by 9.0% and 14.6% for 128-bit security level and 256-bit security level, respectively. Furthermore, we adopted the most optimized AES software implementation to improve the performance of pseudo random number generation for random sampling operation. The encryption of AES-256 counter (CTR) mode used for random number generator requires only 3184 clock cycles for 128-bit data input, which is 9.5% faster than previous state-of-art results. Finally, proposed methods are applied to the whole process of Ring-LWE key scheduling and encryption operations, which require only 524,211 and 659,603 clock cycles for 128-bit security level, respectively. For the key generation of 256-bit security level, 1,325,171 and 1,775,475 clock cycles are required for H/W and S/W AES-based implementations, respectively. For the encryption of 256-bit security level, 1,430,601 and 2,042,474 clock cycles are required for H/W and S/W AES-based implementations, respectively.

A New Method for Format Preserving Encryption in High-Data Rate Communications

In some encryption systems it is necessary to preserve the format and length of the encrypted data. This kind of encryption is called FPE (Format Preserving Encryption). Currently, only two AES (Advanced Encryption Standard) modes of operation recommended by the NIST (National Institute of Standards and Technology) are able to implement FPE algorithms, FF1 and FF3. These modes work in an electronic codebook fashion and can be configured to encrypt databases with an arbitrary format and length. However, there are no stream cipher proposals able to implement FPE encryption for high data rate information flows. The main novelty of this work is a new block cipher operation mode proposal to implement an FPE algorithm in a stream cipher fashion. It has been called CTR-MOD and it is based on a standard block cipher working in CTR (Counter) mode and a modulo operation. The confidentiality of this mode is analyzed in terms of its IND- CPA (Indistinguishability under Chosen Plaintext Attack) advantage of any adversary attacking it. Moreover, the encryption scheme has been implemented on an FPGA (Field Programmable Gate Array) and has been integrated in a Gigabit Ethernet interface to test an encrypted optical link with a real high data rate traffic flow.

Cryptographic system for data applications, in the context of internet of things

With each passing day, Internet of Things (IoT), has the potential to transform our society to a more digital way. In this paper, a cryptographic system is proposed, which has been designed and implemented, following the IoT optimized technologies. As the benefits of IoT are numerous, the need for a privacy platform is more than necessary to be developed. This work aims to demonstrate this by, firstly, implementing efficient and flexible, the fundamentals primitives of cryptography and privacy. Secondly, this is achieved, by introducing applied cryptography, in a more interactive and flexible approach. The proposed system and the incorporation of this platform is scrutinized. In the context of this work, an application of symmetric cryptography is introduced, based on the Advanced Encryption Standard (AES) in Electronic Code Book (ECB), Cipher Block Chaining (CBC) and Counter (CTR) modes of operation, for both encryption and decryption of texts, images and electronic data applications. In addition two other security schemes are supported by the proposed system: AES Galois/Counter Mode (GCM) and AES Galois Message Authentication Code (GMAC). The GCM proposed integration, in an authentication scheme, designed to provide authenticity and confidentiality, at the same time. On the other hand, GMAC, can be applied as message authentication code. Both operations, are optimized in sense of implementation resources, since the major cost is targeted to AES core. In addition, based on the integrated hardware modules, user registration and validation is proposed and implemented, with no additional cost, and with no performance penalty. Furthermore, two factor authentication has been designed and proposed, based on One Time Passwords (OTP), which can been produced with a random procedure. After these, a reference to the security levels, as regards to the communication between the IoT layers of the architecture, is presented. IoT hardware platforms are facing lack of security level and this brings the opportunity to use advanced security mechanisms. Implementation comparison results emphasize the importance of testing and measuring the performance of the alternative encryption algorithms, supported by hardware platforms.

(Invited) New Flexible Electrodes for Electrochemical Analysis: A Step Forward Towards Wearable Sensors

Electrochemical sensors present many advantages to develop wearable sensors and to be applied for real samples as at the point-of-care using. They are easy to use, low cost and above all, they allow easy integration with the electronics and different parts of the system. However, there are several problems still to be solved in order to carry out the complete integration of these systems. Currently flexible electronics is already a reality, so, the manufacture of the sensor itself on a flexible substrate without losing any of its relevant functionalities takes on paramount importance. In this sense, printing technologies offer a suitable solution for the development of flexible electrodes as well as electronics to use them. Therefore, these technologies open the door to the development of a whole new range of flexible devices for many applications in biosensing, Point-of-Care (PoC) analysis and wearable systems. In this work, the fabrication process of carbon-based electrochemical sensors on flexible plastic substrates has been optimized. Thus, different flexible substrates; including several materials, thickness and color; have been evaluated for printing the new sensors. These sensors have been printed using different carbon and silver ink formulations with several mesh screens (stainless steel, polyester…). The selection of the ink formulations and mesh affects to the final surface morphology as well as the shelf-life and performance of electrodes. In the same way, a critical step in the fabrication of flexible sensors has been the selection of the drying conditions. This step enables the curing of the inks by removing the organic solvents, but without affecting to the flexible substrates. In most of the cases, the plastic substrates show a low glass transition temperature. Therefore, the drying time and temperature as well as the methodologies (box oven, conveyor dryer…) have been essential for avoiding some physical change in the substrate and electrode surface. As a flexible substrate is used, the final electrode structures should also show stretchable features. A microscopy and electrochemical characterization has been carried out with the new flexible carbon-based electrodes. The final sensor consists of a multilayer structure integrating the working (WE), reference (RE) and counter (CE) electrode as well as a dielectric layer on the same bendable substrate ( Figure 1A ). Thus, the surface morphology of the electrodes was observed by using scanning (SEM) and transmission (TEM) electron microscopy in order to check the effect of the substrate, printing conditions and ink compositions. The performance of new electrodes has been also evaluated by using different electrochemical techniques such cyclic voltammetry (CV), amperometry and electrochemical impedance spectroscopy (EIS), in static, and specially, dynamic conditions. The new flexible sensors were integrated into a basic flow analysis system by using a modular platform ( Figure 1D ). This platform enables the interfacing between the sensor and the other components of the FIA system; peristaltic pump, injection valve and electrochemical station ( Figure 1 B and C ). A portable All-in-One electrochemical station with built-in EIS analyzer ( Figure 1 E ) was used for performing the electrochemical measurements. The performance of the new flexible electrochemical sensors has been evaluated with different benchmark redox compounds in the FIA system. This work has been supported by EU (MANUNET) and IDEPA (IDE/2017/000124) Figure 1

Physical Layer Encryption for Industrial Ethernet in Gigabit Optical Links

Industrial Ethernet is a technology widely spread in factory floors and critical infrastructures where a high amount of data need to be collected and transported. Fiber optic networks at gigabit rates fit well with that type of environment, where speed, system performance, and reliability are critical. In this paper, a new encryption method for high-speed optical communications suitable for such kinds of networks is proposed. This new encryption method consists of a symmetric streaming encryption of the 8b/10b data flow at physical coding sublayer level. It is carried out thanks to a format preserving encryption block cipher working in CTR (counter) mode. The overall system has been simulated and implemented in a field programmable gate array. Thanks to experimental results, it can be concluded that it is possible to cipher traffic at this physical level in a secure way. In addition, no overhead is introduced during encryption, getting minimum latency and maximum throughput.

FACE: Fast AES CTR mode Encryption Techniques based on the Reuse of Repetitive Data

The Advanced Encryption Standard (AES) algorithm and Counter (CTR) mode are used for numerous services as an encryption technique that provides confidentiality. Even though the AES with counter (AES CTR) mode has an advantage in that it can process multiple data blocks in parallel, its implementation should also be observed to reduce the computational burden of current services.In this paper, we propose an implementation method called FACE that can improve the performance of the AES CTR mode. The proposed method is based on five caches of frequently occurring intermediate values, so that it reduces the number of unnecessary computations. Our method can be employed in any AES CTR implementation, regardless of the platform, environment, or implementation method. There are two known AES implementation techniques, namely, counter-mode caching and bitslicing. FACE extends counter-mode caching in order to optimize the previous result and to maximize the scope of caching. We show that FACE can be applied efficiently to various implementations (table-based, bitsliced, and AES-NI-based). In particular, this is the first attempt to combine our extended counter-mode caching with bitsliced implementations of AES, and is also the first to apply counter-mode caching up to the round transformations of AES-NI implementation. To prove the efficiency of our proposed method, we conduct a performance evaluation in various environments, which we then compare with the previous fastest results. Our bitsliced FACE needs 6.41 cycles/byte on an Intel Core 2, and AES-NI-based FACE records 0.44 cycles/byte on an Intel Core i7.

Hydrogen Permeation in Nuclear Components at High Temperatures: Preliminary Electrochemistry Study

Adventitious hydrogen uptake into engineering materials frequently occurs as a consequence of the corrosion process at cathodic sites and tends to compromise, often severely, the mechanical properties of the alloy leading particularly to reduced fracture toughness and ductility and increased brittleness. In light water reactors (LWR) oxidation of the zirconium fuel cladding, and also other reactor internal components, results in pickup of hydrogen into the metal and limits how long the cladding can remain in the reactor environment, hence limiting the efficient consumption (“burn-up”) of the nuclear fuel. The fraction of hydrogen that is picked up by the metal in service, and the rate of the hydrogen diffusion, are key factors in understanding this phenomenon. It is thus of considerable interest to have a better understanding of the kinetics of hydrogen entry and diffusion/permeation in reactor pressure vessel materials (i.e. austenitic stainless steels and nickel based alloys) and particularly fuel cladding (zirconium alloys) under realistic operating conditions. The main purpose of this research is to adapt the well-known Devanathan-Stachurski permeation cell, to measure hydrogen diffusion at temperatures in the range 100-300°C, Figure 1. The work is divided in two stages. Firstly, an electrochemical study and selection of the candidate electrolytes, reference (RE) and counter (CE) electrodes for the oxidation and reduction compartments of the cell, within the temperature range specified above has been carried out. Secondly, hydrogen permeation measurements will be carried out in order to measure the entry kinetics and diffusion coefficient of hydrogen in reactor materials. This current report is focused on the first phase of the work. To realise the Devanathan-Stachurski concept at higher temperatures requires the use of concentrated salt solutions, molten salts or ionic liquids. For this work two molten salt eutectic mixtures were selected: NaOH + KOH (49:51 by mass; alkaline system) and NaHSO4 + KHSO4 (47:53 by mass; acidic system). Both electrolytes rely on residual dissolved water to supply protons and, hence, a humidified argon gas flow was provided with which the electrolyte was equilibrated. Platinum was used as the counter electrode while silver was found to behave as a sufficiently stable pseudo-reference electrode under the experimental conditions. Preliminary polarization curves (Figures 2 and 3) using both molten salts are shown within the working temperature range for Zr (99.2% – i.e. commercial purity zirconium), Zr4 (Zr + 1.5% Sn, 0.3% Fe+Cr and 0.2% Fe – i.e. zircalloy 4) and 316SS (16-18%Cr, 10-14% Ni, 2-2.5% Ni – i.e. AISI 316 austenitic stainless steel). The results demonstrate cathodic kinetics consistent with hydrogen evolution and anodic kinetics consistent with passivation in both electrolytes. Although 316SS is consistently less stable (i.e. corrodes more) under anodic polarisation. The bisulphate eutectic provides better hydrogen evolution kinetics but was found to be unstable above about 250°C and so the sodium/potassium hydroxide was selected as the electrolyte of choice. Conventionally, Devanathan-Stachurski cells operate under steady state (Fick’s 1stLaw) where the hydrogen activity is fixed on opposite sides of the permeation membrane. However in order to maximise the opportunity for detection of hydrogen given the extremely low diffusivity in zirconium, a protocol was adopted whereby the working electrode surface was first polarised into the cathodic region to evolve hydrogen then the potential was stepped into the anodic region to oxidise hydrogen. This concept is shown in figure 4. Figure 5 shows the results of two anodic polarisation in NaOH-KOH at 250°C from which it is clear that pre-polarisation into the cathodic region to evolve hydrogen results in a higher current that can be ascribed to the presence of hydrogen in the metal. Figure 1