Package Cost Reduction Research Articles

Managing Mismatches in Voltage Stacking with CoreUnfolding

Five percent to 25% of power could be wasted before it is delivered to the computational resources on a die, due to inefficiencies of voltage regulators and resistive loss. The power delivery could benefit if, at the same power, the delivered voltage increases and the current decreases. This article presents CoreUnfolding , a technique that leverages voltage Stacking to improve power delivery efficiency. Our experiments show that about 10% system-wide power can be saved, the voltage regulator area can be reduced by 30%, di / dt improves 49%, and the power pin count is reduced by 40% (≈ 20% reduction in packaging costs), with negligible performance degradation.

A Review of Failure Analysis Methods for Advanced 3D Microelectronic Packages

Advanced three dimensional (3D) packaging is a key enabler in driving form factor reduction, performance benefits, and package cost reduction, especially in the fast paced mobility and ultraportable consumer electronics segments. The high level of functional integration and the complex package architecture pose a significant challenge for conventional fault isolation (FI) and failure analysis (FA) methods. Innovative FI/FA tools and techniques are required to tackle the technical and throughput challenges. In this paper, the applications of FI and FA techniques such as Electro Optic Terahertz Pulse Reflectometry, 3D x-ray computed tomography, lock-in thermography, and novel physical sample preparation methods to 3D packages with package on package and stacked die with through silicon via configurations are reviewed, along with the key FI and FA challenges.

Stitch Bond Process of Pd-Coated Cu Wire: Experimental and Numerical Studies of Process Parameters and Materials

Cost reduction is the main driver in the recent transition to Cu wire bonding from predominate Au wire bonding. Other cost reduction in packaging comes from new developments in substrates and lead frames, for example, Pre-Plated Frames (PPF) and uPPF for QFP and QFN reduce the plating and material cost. However, 2nd bonds (stitch bonds) can be more challenging on some of the new leadframe types due to the rough surface finish and thin plating thickness. Pd-coated Cu (PCC) wire has been recently introduced to improve the wire bonding process with bare Cu wire, mainly to improve reliability and enhance the stitch bond process. More fundamental studies are required to understand the influences of bonding parameters and bonding tools to improve stitch bondability. The stitch bond process of 0.7 mil diameter PCC wire on Au/Ni/Pd-plated quad flat-no lead (QFN) PPF substrate is investigated in this study. Two capillaries with the same geometry but different surface finishes are used to investigate the effect of capillary surface finish on the stitch bond process. The two capillary types are a polished finish type which is commonly used for Au wire bonding, and a granular finish capillary that has a much rougher surface finish. Process window between no stick on lead (NSOL) and short tail is compared. The effect of process parameters including bond force and table scrub amplitude is studied. The process window test results revealed that the granular capillary has larger process window and a lower chance of short tail occurrence. It has been shown that a higher scrub amplitude increases the chance of successful stitch bond formation. To further compare the capillary surface finishes, 3 sets of parameter settings with different bond force and scrub amplitude are tested. For all three parameter sets tested, the granular capillary showed better quality in bond strength. The granular capillary resulted in higher stitch pull strength compared to the polished type. A finite element model (FEM) of the process was developed to better understand the experimental observations. The amount of surface expansion (plastic deformation) of the wire at the wire and substrate interface was extracted from the model and attributed to the degree of adhesion (bonding). The model was used to confirm the experimental observation of adhesion (bonding) with different surface finish.

Thick Copper and Aluminum Wire Bonding Technology for High Power Laser Devices

The trends of increasing demand of higher power laser devices with increased current capacity and total package cost reduction to improve dollars per watt of laser output power have resulted in the need for alternatives to traditional gold wirebonds on gold-plated substrates. Copper and aluminum wires are considered to be the leading candidates due to their vast reliability database in the semiconductor industry and cost advantages. Room temperature (25°C) wirebonding with a robust process window and high yield is required for high-volume, low-cost applications. The wirebonds must also meet or exceed the stringent reliability requirements of 1000 hours at 85°C/85%RH damp heat (DH) and 1000 hrs at 175°C high temperature storage (HTS) testing. In this study, 10 mils round thick copper and aluminum wire bonding has been successfully developed at room temperature with no intermetallic failure or void formation at the Al/Au and Cu/Au interfaces after 1000 hours of DH and HTS testing. Further investigation with corrosion-resistant Al wire shows excellent pull strength and wire shear per Mil-Std 883 after 2000 hours of DH and HTS testing with no evidence of void formation at the Al/Au interface. The thickness of the Au-Al intermetallic is found to be minimal at ∼4um after 1000 hours of HTS testing. This study has demonstrated that both thick copper and aluminum wire are capable of wire bonding at room temperature to function as a reliable interconnect with improved product performance and low cost.

Facet reflectivity of a spot-size-converter integrated semiconductor optical amplifier

Traveling-wave type semiconductor optical amplifiers (SOAs) integrated with a spot-size-converter (SSC) are extensively studied for improvement of coupling efficiency with single-mode fibers and for cost reduction in packaging. In this paper, the structural dependence of the SSC on effective facet reflectivity R/sub eff/ is investigated theoretically and experimentally. It is shown that, not only sufficient mode-conversion in the SSC region, but also the introduction of angled facets, are essential for reducing R/sub eff/. A small gain ripple (less than 0.1 dB) in an amplified spontaneous emission (ASE) spectrum, fiber-to-fiber gain of 26 dB, and saturation output power of 7 dBm are observed for the fabricated SOA, which consists of a window length of 20 /spl mu/m, facet angle of 7/spl deg/, and anti-reflection coated facet of less than 1% reflectivity.