Hardware Implementation Cost Research Articles

Combined word-length optimization and high-level synthesis of digital signal processing systems

Conventional approaches for fixed-point implementation of digital signal processing algorithms require the scaling and word-length (WL) optimization at the algorithm level and the high-level synthesis for functional unit sharing at the architecture level. However, the algorithm-level WL optimization has a few limitations because it can neither utilize the functional unit sharing information for signal grouping nor estimate the hardware cost for each operation accurately. In this study, we develop a combined WL optimization and high-level synthesis algorithm not only to minimize the hardware implementation cost, but also to reduce the optimization time significantly. This software initially finds the WL sensitivity or minimum WL of each signal throughout fixed-point simulations of a signal flow graph, performs the WL conscious high-level synthesis where signals having the similar WL sensitivity are assigned to the same functional unit, and then conducts the final WL optimization by iteratively modifying the WLs of the synthesized hardware model. A list-scheduling-based and an integer linear-programming-based algorithms are developed for the WL conscious high-level synthesis. The hardware cost function to minimize is generated by using a synthesized hardware model. Since fixed-point simulation is used to measure the performance, this method can be applied to general, including nonlinear and time-varying, digital signal processing systems. A fourth-order infinite-impulse response filter, a fifth-order elliptic filter, and a 12th-order adaptive least mean square filter are implemented using this software.

Performance-based constraints for multidimensional networks

A stochastic analysis of multidimensional networks with unidirectional or bidirectional links between nodes is presented. The analysis allows the development of an accurate model for examining the performance and cost trade-offs of different network configurations. The model is validated through simulation and does not rely on the simplifying assumptions of previous models. In addition, the model is valid for the hypercube network. Two new performance-based design constraints are introduced: constant maximum throughput and constant unity queue. These new constraints are fundamentally different than previous constraints, which are based on some characterization of hardware implementation costs. Both of the new constraints allow performance and cost comparisons of different network configurations to be made on the basis of an equal ability to handle a range of traffic load. Results under the new constraints clearly show that a low dimensional network, while offering the lowest message latency, must be significantly more expensive than a comparable high dimensional network and, in some cases, may be impractical to implement. In addition, the constraints demonstrate that performance is highly dependent on offered load.

Efficient primitive traversal using adaptive linear edge function algorithms

Graphics performance is today an important part of a PC's performance statistics. Although scan conversion performance is now overshadowed by texture mapping ability, the choice of primitive traversal algorithm can still introduce a bottleneck in the rasterisation pipeline. After all, the primitive traversal engine generates the pixel fragments on which the remainder of the rasterisation pipeline will operate to produce a pixel colour. Poor primitive traversal performance will limit the potential of the entire graphics pipeline. In this paper we discuss the implementation of triangle traversal algorithms that use linear edge functions. Methods for increasing algorithm performance and the cost of hardware implementation are examined. We show that traversal algorithm efficiency is very important for small primitives. This is very important as primitive size is reducing rapidly to increase the accuracy with which scenes can be modelled.

Design of smart power synchronous rectifier

In low-output-voltage DC/DC power converters, power losses due to the conduction of rectifying devices are significant. Using synchronous rectifiers instead of the conventional fast recovery diodes or Schottky diodes is an effective solution to this problem in most topologies. However, for synchronous rectifiers to perform effectively, this requires an external gate drive with proper sensing and timing control circuits. This can increase the complexity and cost in power converter hardware implementation. For the first time, a smart power synchronous rectifier (SPSR), which is a two-terminal MOS rectifier, is designed to overcome this difficulty. The SPSR integrates a simple control unit with a power MOSFET into a smart module to form a self-controlled synchronous rectifier. It has great advantages over the conventional discrete circuit composition, such as integrated gate control, precise timing switching and fast transient response, which are suitable for applications in high-frequency pulsewidth modulation (PWM) power converter circuits.

An efficient approach to mapping large anns onto fixed systolic architectures

One of the best solutions to the communication problems arising in artificial neural networks (ANNs), due to the high interconnectivity of neurons, is achieved through their implementation on systolic array architectures (SAAs). The case of systematical mapping policies from ANNs to SAAs, however, is little explored. In this work, an efficient mapping policy is explored, capable of implementing an ANN on the available fixed systolic array, while it still allows the exploitation of the training pattern pipelined parallelism and remains feasible from the aspect of the hardware implementation cost.

Choice of word length in the design of a specialized hardware for lossless wavelet compression of medical images

Image compression plays an important role in the archiving and transmission of medical images. Discrete cosine transform (DCT)- based compression methods are not suitable for medical images because of block-like image artifacts that could mask or be mistaken for pathology. Wavelet transforms (WTs) are used to overcome this problem. When implementing WTs in hardware, finite precision arithmetic introduces quantization errors. However, lossless compression is usually required in the medical image field. Thus, the hardware designer must look for the optimum register length that, while ensuring the lossless accuracy criteria, will also lead to a high-speed implementation with small chip area. In addition, wavelet choice is a critical issue that affects image quality as well as system design. We analyze the filters best suited to image compression that appear in the literature. For them, we obtain the maximum quantization errors produced in the calculation of the WT components. Thus, we deduce the minimum word length required for the reconstructed image to be numerically identical to the original image. The theoretical results are compared with experimental results obtained from algorithm simulations on random test images. These results enable us to compare the hardware implementation cost of the different filter banks. Moreover, to reduce the word length, we have analyzed the case of increasing the integer part of the numbers while maintaining constant the word length when the scale increases.

Efficient hybrid tree/linear array architectures for block-matching motion estimation algorithms

Execution latency and I/O bandwidth play essential roles in determining the effectiveness and the cost of a parallel hardware implementation for block-matching motion estimation algorithms. Unfortunately, almost all traditional architecture designs, e.g. the two-dimensional mesh-connected systolic array architecture (2DMCSA), and the tree-type structure (TTS), fail to take these two factors into account simultaneously. As a result, they suffer from either large execution latency or huge input bandwidth requirements. The authors propose a family of tree/linear architectures, which efficiently optimise the total implementation cost by combining the merits of the 2DMCSA and the TTS. Moreover, to facilitate hardware designs, the authors present the tree-cut techniques and the on-chip buffer design method to meet computational demands of various video compression applications. Since the proposed architectures are capable of executing the exhaustive search and the fast search block-matching algorithms, they offer relatively flexible and cost-effective hardware solutions for a wide range of video coding systems, including CD-ROM, portable visual communications systems and high-definition TV.

Simulation-based word-length optimization method for fixed-point digital signal processing systems

Word-length optimization and scaling software that utilizes the fixed-point simulation results using realistic input signal samples is developed for the application to general, including nonlinear and time-varying, signal processing systems. Word-length optimization is conducted to minimize the hardware implementation cost while satisfying a fixed-point performance measure. In order to minimize the computing time, signal grouping and efficient search methods are developed. The search algorithms first determine the minimum bound of the word-length for an individual group of signals and then try to find out the cost-optimal solution by using either exhaustive or heuristic methods.

Designing multilayer feedforward neural networks using simplified sigmoid activation functions and one-powers-of-two weights

A design method for multilayer feedforward neural networks with simplified sigmoid activation functions and one-powers-of-two weights is proposed. The designed multilayer feed-forward neural network can retain a nearly identical generalisation capability of the corresponding network using continuous weights, while having increased computational speed in applications and reduced cost in digital hardware implementation.

Jitter analysis of a phase-locked digital timing recovery system

An analytical approach is presented for the jitter performance of a timing recovery circuit consisting of a hard-limiter, an exclusive-or gate, followed by a second-order phase-locked loop. Exact expressions for the autocorrelation function and the power spectral density of the zero-crossing jitter in the data signal are derived, and then the phase jitter variance of the timing wave, generated at the output of the timing circuit, is obtained analytically as a function of various system parameters. Finally, numerical results and a comparative performance analysis show that considerable improvement can be achieved in jitter performance in addition to having the advantage of low cost and simple hardware implementation.

On reducing the Phong shading method

Today, the shading method of Phong plays an important role in the design of real-time image generation systems. Often, the model has been used in combination with a colour interpolation, suppressing a main property of this model, namely the visually acceptable rendering of highlights. Unfortunately, Phong's algorithm demands a normalisation step, which is expensive to implement in hardware. We will present several shading methods which are reductions of the Phong algorithm. They will be compared both visually and theoretically. The alternatives are judged with respect to their hardware implementation cost. The result is a hierarchy of shading methods that can be used to select the required cost-performance ratio for a given visualisation task.

A flexible VLSI core for an adaptable architecture

Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, for each architecture. The SCalable ARChitecture Experiment (SCARCE) aims to provide a framework for application-specific processor design. The framework allows scaling of functionality, implementation complexity, and performance. The SCARCE framework consists and will consist of: an architecture framework defining the constraints for the design of application-specific architectures; tools for synthesizing architectures from application or application-area; VLSI cell libraries and tools for quick generation of application-specific processors; a system-software platform which can be retargeted quickly to fit the application-specific architecture; This paper concentrates on the micro-architecture framework of SCARCE and outlines the process of generating VLSI processors.

An architecture framework for application-specific and scalable architectures

Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, for each architecture. The SCalable ARChitecture Experiment (SCARCE) aims to provide a framework for application-specific processor design. The framework allows scaling of functionality, implementation complexity, and performance. The SCARCE framework consists and will consist of: an architecture framework defining the constraints for the design of application-specific architectures; tools for synthesizing architectures from application or application-area; VLSI cell libraries and tools for quick generation of application-specific processors; a system-software platform which can be retargeted quickly to fit the application-specific architecture; This paper concentrates primarily on the architecture framework of SCARCE, but also presents briefly some software issues and outlines the process of generating VLSI processors.

Multilevel PRS/QPRS Above the Nyquist Rate

An improved efficiency partial-response signaling (PRS) and quadrature partial-response signaling (QPRS) data filtering strategy, which enables a higher transmission rate (more symbols/s/Hz) than feasible with conventional PRS and QPRS systems, is introduced. With the use of our technique, a smaller number of signal levels (states) can be chosen for specified spectrally efficient applications; thus, an increase in S/N immunity is obtained with a lower cost and simpler hardware implementation.

A Digital Approach to Symbol Timing Recovery Systems

An analysis of a symbol timing recovery (STR) technique using digital processing is presented. The ratio of the discrete spectral power at the symbol rate frequency to the nearby continuous spectral power is used as a criterion of STR performance. It is shown that this power ratio equals the quality factor of the narrow bandpass filter and that it does not depend on the value of the delay element. The performance of the STR subsystem is consequently determined by the quality factor of the bandpass filter rather than by the specific delay. In addition to this, some experimental evidence that the additive channel noise has little effect on the power ratio is given. A modified phase-locked loop with an LC prefiiter is proposed to extract the symbol timing clock. This prefilter improves the acquisition and synchronization performance of the PLL. The STR technique presented here has the advantages of lower cost and simpler hardware implementation over other serial STR techniques.