Correlated Double Sampling Research Articles

Design and performance of a low noise, 128-channel ASIC preamplifier for readout of active matrix flat-panel imaging arrays

Design architecture and performance measurements of a low noise, 128-channel application-specific-integrated-circuit (ASIC) preamplifier are reported. The ASIC was designed for readout of active matrix flat-panel imager (AMFPI) arrays. Such arrays, which presently can be made as large as 41 cm×41 cm and with pixel-to-pixel pitches down to ∼70 μm, require large numbers of low noise, high density, custom integrated readout circuits. The design of this new chip is specifically tailored for research and development of active matrix flat-panel arrays for various medical imaging applications. The design architecture includes the following features: (1) Programmable signal gain which allows acquisition of a wide range of signal sizes from various array designs so as to optimize the signal-to-noise ratio; (2) Correlated double sampling (CDS) which significantly reduces certain noise components; (3) Pipelined readout (simultaneously sampling and multiplexing signals) which reduces image acquisition time; (4) Programmable bandwidth controls which balance noise and acquisition speed; and (5) Two selectable modes of output multiplexing (64:1, 16:1) for slow or fast readout. In this paper, detailed measurements of various performance parameters are presented. These measurements include noise characteristics, the relationship between bandwidth and noise, signal response linearity, channel-to-channel and pipeline cross-talk, signal gain and gain variation across channels, and the effect of sampling methods on noise. These characterizations indicate that the performance of the ASIC has achieved the original design goals.

Correlated double sampling integrator insensitiveto parasitic capacitance

A new correlated double sampling (CDS) scheme is proposed which improves the operation of an integrator with a large parasitic capacitor at the input node of an op-amp. It suppresses the effects of the 1/f noise and offset voltage of the op-amp, as well as the kTC charge noise from the parasitic capacitor. It also reduces charge injection and clock feedthrough effects.

A 256/spl times/256 CMOS differential passive pixel imager with FPN reduction techniques

Passive pixel sensors provide an alternative to the conventional active pixel sensor (APS) for high-density CMOS imaging arrays. Similar to the history of the single-transistor DRAM cell, this one-transistor pixel cell has one main advantage over the APS. It has high fill-factor in a smaller area, leading to a high-density array of pixels with high quantum efficiency. Experiments reveal a major weakness in passive pixels is a signal-dependent parasitic current that can contaminate charge signals in different parts of the array. The origin of this parasitic current is explained here. A correlated double sampling (CDS) circuit in a differential architecture removes its effects.

A CMOS image sensor with a simple fixed-pattern-noise-reduction technology and a hole accumulation diode

A simple fixed-pattern-noise (FPN)-reduction technology, which consists of a five-transistor pixel circuit, a hole accumulation diode for sensing elements, and a correlated-double-sampling (CDS) circuit with an I-V converter in an output stage circuit, is applied to a 1/3-inch 640/spl times/480-pixel CMOS image sensor. The five-transistor pixel circuit outputs the current mode pixel signal with a reset level and a signal level successively in one pixel period. The I-V converter is designed to reduce a signal-line voltage to close to the ground level in order to give sufficient voltage to an amplification transistor in a pixel. The CDS circuit receives a pixel signal from the I-V converter and performs as an FPN-reduction circuit by subtracting a signal level from a reset level of a pixel signal. Owing to the technology, the CMOS image sensor achieved a sensitivity of 0.52 V/lx/spl middot/s, a saturation signal of 200 mV, a dynamic range of 61 dB and a dark current of 150 pA/cm/sup 2/.

Analysis and reduction of signal readout circuitry temporal noise in CMOS image sensors for low-light levels

In this paper, analytical noise analysis of correlated double sampling (CDS) readout circuits used in CMOS active pixel image sensors is presented. Both low-frequency noise and thermal noise are considered. The results allow the computation of the output RMS noise versus MOS transistor dimensions with the help of SPICE-based circuit simulators. The reset noise, the influence of floating diffusion capacitance on output noise and the detector charge-to-voltage conversion gain are also considered. Test circuits were fabricated using a standard 0.7 /spl mu/m CMOS process to validate the results. The analytical noise analysis in this paper emphasizes the computation of the output variance, and not the output noise spectrum, as more suitable to CDS operation. The theoretical results are compared with the experimental data.

Performance analysis of a color CMOS photogate image sensor

The performance of a color CMOS photogate image sensor is reported. It is shown that by using two levels of correlated-double sampling it is possible to effectively cancel all fixed-pattern noise due to read-out circuit mismatch. Instead the fixed-pattern noise performance of the sensor is limited by dark current nonuniformity at low signal levels, and conversion gain nonuniformity at high signal levels. It is further shown that the imaging performance of the sensor is comparable to low-end CCD sensors but inferior to that reported for high-end CCD sensors due to low quantum efficiency, high dark current, and pixel cross-talk. As such the performance of CMOS sensors is limited at the device level rather than at the architectural level. If the imaging performance issues can be addressed at the fabrication process level without increasing cost or degrading transistor performance, CMOS has the potential to seriously challenge CCD as the solid-state imaging technology of choice due to low power dissipation and compatibility with camera system integration.

Polyphase SC IIR Hubert transformer with reducedsensitivity to finite gain and bandwidth

A polyphase switched-capacitor (SC) IIR Hubert transformer with reduced sensitivity to finite opamp gain and bandwidth is proposed for high frequency applications. Low sensitivity is achieved by applying a predictive correlated-double-sampling (CDS) technique. Theoretical analysis and SWITCAP simulation results are given.

Hybrid infrared focal plane signal and noise model

A signal and noise model is presented for an infrared sensor with an advanced hybrid focal plane that uses a CMOS readout integrated circuit (ROIC). Part of the motivation for this work is to present a clear foundation for some of the well-known practical and useful rules that apply to infrared sensors in use today. The model shows explicitly how a correlated double sampler (CDS) eliminates kTC noise, explains the interesting dependence of output 1/f noise on integration and epoch times, and is generic enough to treat a large class of ROIC preamps. A sensor with a direct injection readout is treated as an example and user-friendly formulas are listed and used to calculate sensor signal and noise.

A 2.7 V CMOS Analog Front End for CCD Video Systems

A 2.7 V analog front end (AFE) is integrated with a 10-bit ADC for application in CCD video systems. The AFE consists of a correlated double sampler (CDS) and a programmable gain (from 6 dB–38 dB) amplifier (PGA). The PGA is implemented by two stages of digitally controlled transconductors. New circuit techniques are used to implement the AFE in CMOS technology using a 2.7 V supply to handle at least a 0.8 V input signal. The sampling rate of the chip is over 15 MHz. The AFE consumes less than 20 mA. The measured integral non-linearity (INL) of the chip with the CCD input under 0.7 V is 9 LSB. The differential non-linearity (DNL) is ±0.5 LSB.

A CMOS integrating amplifier for the PHENIX Ring Imaging Cherenkov detector

A CMOS integrating amplifier has been developed for use in the PHENIX ring imaging Cherenkov (RICH) detector. The amplifier, consisting of a charge-integrating amplifier followed by a variable gain amplifier (VGA), is an element of a photon measurement system comprising a photomultiplier tube, a wideband, gain-of-10 amplifier, the integrating amplifier, and an analog memory followed by an ADC and double correlated sampling implemented in software. The integrating amplifier is designed for a nominal full scale input of 160 pC with a gain of 20 mV/pC and a dynamic range of 1000:1. The VGA is used for equalizing gains prior to forming analog sums for trigger purposes. The gain of the VGA is variable over a 3:1 range using a 5-bit digital control, and the risetime is held to approximately 20 ns using switched compensation in the VGA. Details of the design and results from several prototype devices fabricated in 1.2 /spl mu/m Orbit CMOS are presented. A complete noise analysis of the integrating amplifier and the correlated sampling process is included as well as a comparison of calculated, simulated and measured results.

High-accuracy circuits for on-chip capacitive ratio testing and sensor readout

This paper presents novel CMOS switched-capacitor circuits for high-accuracy, on-chip capacitive-ratio testing and sensor readout. Using sigma-delta and correlated-double-sampling (CDS) techniques, these circuits provide accurate digitized capacitive-ratio readout. Both single-ended and fully differential circuits are presented. Simulation results show that the resolution can be as fine as 100 aF for 10 pF capacitors. Single-ended circuit and fully-differential circuits were implemented and tested. The measured standard deviation was below 20 aF when 10 pF capacitors were tested.

Offset-free black restoration and simplified correlateddouble sampling for linear CCDs

Black reference restoration and simple correlated double sampling techniques for a charge coupled device imaging system are discussed. A feedback loop which includes the entire video circuitry and analogue to digital conversion is used. The chief advantage of the technique is the elimination of offset errors.

A new low-noise CCD signal acquisition method based on a commutable band-pass filter

A new Correlated Double Sampling (CDS) method for low-noise CCD signal acquisition is presented. The method is based on the utilization of an active band-pass filter with adjustable frequency characteristics. By varying the filter parameters in sequence with the pixel readout, the signal information may be extracted while keeping the equivalent noise bandwidth low. This new acquisition method is simple to implement, offers low-noise performance (close to double integrators), and has several other advantages compared to the other acquisition systems in use. We also present the derivation of a mathematical model to simulate the signal-to-noise ratio for a given CCD output noise characteristic and pixel readout frequency. Our model considers the nonstationary nature of the signal at the sampling instant which implies that the usual way of calculating average noise power (using the filter's transfer function) is not valid. Theoretical results are compared with experimental data and the noise performance of this approach is compared with other CDS methods now in use.

A new cryogenic CMOS readout structure for infrared focal plane array

A new current readout structure for the infrared (IR) focal-plane-array (FPA), called the switch-current integration (SCI) structure, is presented in this paper. By applying the share-buffered direct-injection (SBDI) biasing technique and off focal-plane-array (off-FPA) integration capacitor structure, a high-performance readout interface circuit for the IR FPA is realized with a pixel size of 50/spl times/50 /spl mu/m/sup 2/. Moreover, the correlated double sampling (CDS) stage and dynamic discharging output stage are utilized to improve noise and speed performance of the readout structure under low power dissipation. In experimental SCI readout chip has been designed and fabricated in 0.8-/spl mu/m double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip at 77 K with 4 and 8 V supply voltages have successfully verified both the readout function and the performance improvement. The fabricated chip has a maximum charge capacity of 1.12/spl times/10/sup 8/ electrons, a maximum transimpedance of 1/spl times/10/sup 9/ /spl Omega/, and an active power dissipation of 30 mW. The proposed CMOS SCI structure can be applied to various cryogenic IR FPA's.

The HAWAII Infrared Detector Arrays: testing and astronomical characterization of prototype and science-grade devices

Two generations of prototypes of a HgCdTe infrared detector array with 1024 × 1024 pixels developed by the Rockwell International Science Center have been tested in the new Quick Infrared Camera (QUIRC) and an upgraded version of KSPEC a cross-dispersed near-infrared spectrograph, on the University of Hawaii 2.2 m telescope. The HAWAII (HgCdTe Astronomical Wide Area Infrared Imager) prototype devices achieved very good performance. The read-noise in correlated double sampling (CDS) is between 10 and 15 e − rms, depending on the conditions of the operations and the way read-noise is computed. The quantum efficiency in H and K is above 50%. The full-well capacity is above 10 5 e − at 0.5 V applied detector bias and is, in our system, limited by the dynamic range of the A/D converter. The residual excess dark-current problem known from NICMOS-3 devices (Hodapp et al., 1992) [PASP, 104, 441] is not fully resolved. However, it appears less serious in our first HAWAII prototype devices. Using KSPEC, operation under low background conditions has been tested. At an operating temperature of 65 K, and using up to 128 samples of multi-sampling, a read-noise of < 5 e − and a dark current < 1 e −1/min has been demonstrated. Tests of fast sub-array reads for wavefront sensing were conducted using QUIRC. For a sub-array frame repeat time of 11 ms, a read-noise of 6 e − has been demonstrated. An engineering-grade second-generation HAWAII device with reliable hybridization is now in routine operation in KSPEC. The first science-grade HAWAII device has now been installed in the QUIRC camera and is in routine operation. Steven Beckwith

Equivalent noise charge of double correlated sampling

The noise performance of double correlated sampling is analysed. The equivalent noise charge is minimised by the appropriate choice of time constants. The contribution of the serial flicker noise is also calculated.

A reflected-light receiver with 2 nA sensitivity using CDS and separate low-pass filtering of the input signal at each clock-phase

The design of an integrated receiver for reflected light using correlated double sampling (CDS) is presented. CDS has the disadvantage that input signals of high frequencies are folded back to the base band caused by sampling the continuous input signal. However, the circuit presented here uses a new method to limit the bandwidth of the CDS input signal. Two filter-capacitors, one for each clock phase, are periodically connected to the input of the CDS circuit. As the input signal is low-pass filtered by the ohmic output resistance of the optical sensor in conjuction with the filter-capacitors, aliasing can be avoided. Measurements of a test circuit demonstrate the effectiveness of this principle.

The SVX2 readout chip [Si strip detector

A new readout chip called SVX2 is being designed for silicon detector systems at Fermilab. SVX2 is essentially an upgrade of the presently used SVX chip and contains extensive performance and feature enhancements. SVX2 is designed to accommodate much shorter beam crossing times (132 ns to 400 ns) with minimal increase in noise and power. Analog signal delay is formed by a double correlated sampling pipeline in order to allow time for trigger formation. Signal digitization of up to eight bits is performed on the chip with an A/D converter per channel. This allows threshold setting, sparsification, and readout to be purely digital. Design philosophy will be discussed and test results presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An experimental photodiode array unit for ultrahigh-resolution recording of X-ray images

The geometrical resolution of modern solid-state X-ray imagers (photodiode arrays, PDA, and charge-coupled devices, CCD) is defined by their sensitive-pixel sizes and ranges from 10 up to 20 μm, i.e. these imagers yield considerably to photoemulsions in the resolution (0.1–1 μm of emulsions). In the present paper, an attempt to create a recording unit with a spatial resolution comparable to that of photoemulsions is described. First results of testing of the unit is described. The last was fabricated on the basis of a PDA containing 1024 sensitive pixels which are 150 μm high and are positioned with a 25 μm step. The feature of the given PDA consists of the presence of an individual charge-sensitive amplifier in each pixel. This allowed us to realize an algorithm of the digital double correlated sampling and to remove KTC noise which, under ordinary conditions, limits the PDA sensitivity. To diminish the noise level, the unit is provided with a double-correlated-sampling analog highway, which removes 1 f noises of the on-chip read preamplifiers and possesses the LF filter qualities, and with cooling of the PDA by a two-stage battery of Peltier cells. The unit was tested in the mode of the integrating X-ray imager. It is expected, by corresponding computer processing of the separate X-ray photon absorption events, that one will succeed in determining each event coordinate while allowing for the signal charge distribution between pixels due to charge diffusion in the PDA substratum.

A high-resolution multibit Sigma Delta ADC with digital correction and relaxed amplifier requirements

A second-order multibit Sigma Delta (sigma-delta) analog-to-digital converter (ADC) with a 4-b internal quantizer is described. It uses a simple and fast digital correction scheme. A correlated-double-sampling (CDS) fully differential integrator was used, in which the op amp needed only a low slew rate and moderate bandwidth for a sampling rate of 5.25 MHz. A second-order modulator was fabricated in the standard MOSIS p-well 2- mu m CMOS process. The excellent measured linearity and high S/(N+D) ratio (95 dB with an oversampling ratio of only 128) of the corrected converter verified the practical advantages of the proposed architecture. >