Correlated Double Sampling Research Articles

Biometrics for electronic eyes: system authentication with embedded CMOS image sensor

Identically designed electronic devices such as transistors may have random variations in their physical quantities. Inspired by human biometrics, this paper presents a novel approach that enables home appliances to have unique identities based on the intrinsic features of a CMOS image sensor (CIS) embedded in their electronic eyes (i.e., inbuilt cameras). More specifically, the column component of the fixed pattern noise (FPN) that inevitably exists in most modern CISs is utilized as a unique feature of the CIS for describing a unique ID for the embedded system. To practically capture column FPNs that were originally canceled out by a correlated double sampling (CDS) process, this paper also proposes a novel readout scheme. The feasibility of the proposed CIS-based identification is assessed with real measurements using 12 CIS prototypes. In conclusion, a set of applications requiring unique device identifications are presented for demonstrating the utility of the proposed approach in the domain of consumer electronics. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup>

A 14-bit 40-MHz analog front end for CCD application**Project supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044, 61376033), the National High-Tech Program of China (No. 2013AA014103), and the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory (No. ZHD201302).

A 14-bit, 40-MHz analog front end (AFE) for CCD scanners is analyzed and designed. The proposed system incorporates a digitally controlled wideband variable gain amplifier (VGA) with nearly 42 dB gain range, a correlated double sampler (CDS) with programmable gain functionality, a 14-bit analog-to-digital converter and a programmable timing core. To achieve the maximum dynamic range, the VGA proposed here can linearly amplify the input signal in a gain range from −1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth. A novel CDS takes image information out of noise, and further amplifies the signal accurately in a gain range from 0 to 18 dB in 0.035 dB step. A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity. An internal timing core can provide flexible timing for CCD arrays, CDS and ADC. The proposed AFE was fabricated in SMIC 0.18 μm CMOS process. The whole circuit occupied an active area of 2.8 × 4.8 mm2 and consumed 360 mW. When the frequency of input signal is 6.069 MHz, and the sampling frequency is 40 MHz, the signal to noise and distortion (SNDR) is 70.3 dB, the effective number of bits is 11.39 bit.

Reduction of Common Mode Noise and Global Multivalued Offset in Touch Screen Systems by Correlated Double Sampling

Touch-based interactivity has become an important function in displays. This paper reports on the signal processing of touch signals in which touch interactivity is processed as an image, and correlated double sampling (CDS) algorithm is applied for both common-mode noise reduction and global multivalued offset cancellation. Based on experimental results, we achieved a boost in SNR of 7.6 dB. The processed signal reduces detection errors and power consumption of the system.

A Fully Integrated 0.055% INL X-ray CCD Readout ASIC with Incremental &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\Delta \Sigma {\text{ADC}}$&lt;/tex-math&gt; &lt;/inline-formula&gt;

A fully integrated 100 kHz X-ray charge coupled device (CCD) readout application specific integrated circuit (ASIC) employing delta sigma ( $\Delta \Sigma $ ) digitization is presented. To achieve high linearity with small chip size and low power consumption, the correlated double sampling (CDS) is realized by the $\Sigma \Delta{\rm ADC}$ instead of the analog front end (AFE) as in conventional CCD readout circuits. Besides, the proposed decimation filter features simple structure and eases the integration. The chip is fabricated in $0.35 \upmu\hbox{m}$ CMOS technology and the measured integral nonlinearity (INL) throughout the input dynamic range of ASIC is 0.055% with $35.1 \pm 0.3 \upmu\hbox{V}$ input referred noise. A CCD detection system is built and tested with the sensitivity of CCD being $4 \upmu\hbox{V}/\hbox{e}^-$ . The integration test results show that the readout noise is $11.8 \hbox{e}^ {-} $ at 100 kHz readout pixel rate and the achieved energy spectrum resolution is $168 \hbox{eV} \pm 4.7 \hbox{eV}$ (Full Width at Half Maximum: FWHM) at 5.9 keV.

Characterization of total ionizing dose damage in COTS pinned photodiode CMOS image sensors

The characterization of total ionizing dose (TID) damage in COTS pinned photodiode (PPD) CMOS image sensors (CISs) is investigated. The radiation experiments are carried out at a 60Co γ-ray source. The CISs are produced by 0.18-μm CMOS technology and the pixel architecture is 8T global shutter pixel with correlated double sampling (CDS) based on a 4T PPD front end. The parameters of CISs such as temporal domain, spatial domain, and spectral domain are measured at the CIS test system as the EMVA 1288 standard before and after irradiation. The dark current, random noise, dark signal non-uniformity (DSNU), photo response non-uniformity (PRNU), overall system gain, saturation output, dynamic range (DR), signal to noise ratio (SNR), quantum efficiency (QE), and responsivity versus the TID are reported. The behaviors of the tested CISs show remarkable degradations after radiation. The degradation mechanisms of CISs induced by TID damage are also analyzed.

Design and implementation of camera CCD readout for a remote sensing LEO satellite

This paper presents the design and implementation of CCD readout circuits for a remote sensing satellite camera in visible band. CCD even and odd pixels are read out independently during image acquisition. The readout board receives control parameters of CCD and A/D such as CCD integration time and required gains of each analogue to digital convertor (A/D) of CCD even and odd channels. A/D gain should be programmed to provide equal amplitudes in 2 CCD channels (odd and even channels) in same conditions. After adjusting the CCD and A/D parameters the image is captured. The required deriving signals for CCD and A/D are generated in CCD readout board. Analogue output of CCD is amplified and then converted to the digital one. In order to decrease the system volume and weight and increase system capability, the timing and control signals are generated via FPGA. Correlated double sampling (CDS) process is performed on CCD output image data to increase the signal to noise ratio. Moreover, in this paper detail design of CCD readout implementation are presented and appropriate electrical elements are selected. Finally, schematic of constructed board of CCD readout circuits is presented.

Speedster-EXD: a new event-driven hybrid CMOS x-ray detector

The Speedster-EXD is a new 64x64 pixel, 40 $\mu$m pixel pitch, 100 $\mu$m depletion depth hybrid CMOS X-ray detector (HCD) with the capability of reading out only those pixels containing event charge, thus enabling fast effective frame rates. A global charge threshold can be specified, and pixels containing charge above this threshold are flagged and read out. The Speedster detector has also been designed with other advanced in-pixel features to improve performance, including a low-noise, high-gain CTIA amplifier that eliminates interpixel capacitance crosstalk (IPC), and in-pixel Correlated Double Sampling (CDS) subtraction to reduce reset noise. We measure the best energy resolution on the Speedster-EXD detector to be 206 eV (3.5 %) at 5.89 keV and 172 eV (10.0 %) at 1.49 keV. The average IPC to the four adjacent pixels is measured to be 0.25 $\pm$ 0.2 % (i.e. consistent with zero). The pixel-to-pixel gain variation is measured to be 0.80 $\pm$ 0.03 %, and a Monte Carlo simulation is applied to better characterize the contributions to the energy resolution.

A Circadian and Cardiac Intraocular Pressure Sensor for Smart Implantable Lens.

This paper presents a new system to measure the Intraocular Pressure (IOP) with very high accuracy (0.036 mbar) used for monitoring glaucoma. The system not only monitors the daily variation of the IOP (circadian IOP), but also allows to perform an spectral analysis of the pressure signal generated by the heartbeat (cardiac IOP). The system comprises a piezoresistive pressure sensor, an application-specific integrated circuit (ASIC) to read out the sensor data and an external reader installed on customized glasses. The ASIC readout electronics combines chopping modulation with correlated double sampling (CDS) in order to eliminate both the amplifier offset and the chopper ripple at the sampling frequency. In addition, programmable current sources are used to compensate for the atmospheric pressure ( 800-1200 mbar ) and the circadian component (± 7 mbar) thus allowing to read out the very weak cardiac signals (± 1.6 mbar) with a maximum accuracy of 0.036 mbar.

Area-efficient readout with 14-bit SAR-ADC for CMOS image sensors

This paper proposes a readout design for CMOS image sensors. It has been squeezed into a 7.5um pitch under a 0.28um 1P3M technology. The ADC performs one 14-bit conversion in only 1.5us and targets a theoretical DNL feature about +1.3/-1 at 14-bit accuracy. Correlated Double Sampling (CDS) is performed both in the analog and digital domains to preserve the image quality.

A 10 ps Time-Resolution CMOS Image Sensor With Two-Tap True-CDS Lock-In Pixels for Fluorescence Lifetime Imaging

A CMOS lock-in pixel image sensor with embedded storage diodes and lateral electric field modulation (LEFM) of photo-generated charge is developed for fluorescence lifetime imaging. The time-resolved CMOS image sensor (CIS) with twotap lock-in pixels achieves a very high time resolution of 10 ps when images are averaged over 30 frames, a very short intrinsic response time of 180 ps at 374 nm, and a low temporal random noise of 1.75e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> with true correlated double sampling (CDS) operation. In addition, by using the LEFM and optimized process, a very high extinction ratio of approximately 94% at 472 nm laser diode is achieved. The usefulness of the proposed CIS is demonstrated for fluorescence lifetime imaging with the simulation and measurement results.

A Wearable EEG-HEG-HRV Multimodal System With Simultaneous Monitoring of tES for Mental Health Management.

A multimodal mental management system in the shape of the wearable headband and earplugs is proposed to monitor electroencephalography (EEG), hemoencephalography (HEG) and heart rate variability (HRV) for accurate mental health monitoring. It enables simultaneous transcranial electrical stimulation (tES) together with real-time monitoring. The total weight of the proposed system is less than 200 g. The multi-loop low-noise amplifier (MLLNA) achieves over 130 dB CMRR for EEG sensing and the capacitive correlated-double sampling transimpedance amplifier (CCTIA) has low-noise characteristics for HEG and HRV sensing. Measured three-physiology domains such as neural, vascular and autonomic domain signals are combined with canonical correlation analysis (CCA) and temporal kernel canonical correlation analysis (tkCCA) algorithm to find the neural-vascular-autonomic coupling. It supports highly accurate classification with the 19% maximum improvement with multimodal monitoring. For the multi-channel stimulation functionality, after-effects maximization monitoring and sympathetic nerve disorder monitoring, the stimulator is designed as reconfigurable. The 3.37 × 2.25 mm(2) chip has 2-channel EEG sensor front-end, 2-channel NIRS sensor front-end, NIRS current driver to drive dual-wavelength VCSEL and 6-b DAC current source for tES mode. It dissipates 24 mW with 2 mA stimulation current and 5 mA NIRS driver current.

A digital CDS technique and its performance testing**Supported by National Natural Science Foundation of China (10978002)

Readout noise is a critical parameter for characterizing the performance of charge-coupled devices (CCDs), which can be greatly reduced by the correlated double sampling (CDS) circuit. However, a conventional CDS circuit inevitably introduces new noise since it consists of several active analog components such as operational amplifiers. This paper proposes a digital CDS circuit technique, which transforms the pre-amplified CCD signal into a train of digital presentations by a high-speed data acquisition card directly without the noisy CDS circuit, then implements the digital CDS algorithm through a numerical method. A readout noise of 3.3 e− and an energy resolution of 121 eV@5.9 keV can be achieved via the digital CDS technique.

A Modulated Feedback Approach to Improve Closed Loop MEMS Accelerometer Bias Instability

Bias instability serves as one important performance specification for MEMS accelerometer. The bias instability is affected by 1/f noise. Conventional operation adopts the correlated double sampling (CDS) to reduce the 1/f noise, but is only feasible with switch capacitors. The paper proposes a novel and universal modulated feedback approach to improve the bias instability of closed loop MEMS capacitive accelerometer. The modulated feedback method is utilized to isolate the 1/f noise the electronic interface brings to the system. The comparison experiments are set up and the Allan Variance show significant improvement for the bias instability. We achieve the bias instability around 8μg after applying modulated feedback approach, making the closed loop MEMS accelerometer being able to enter high precision inertial sensor level.

Design of 16 bit 200kHz Feedforward Sigma-Delta ADC Applied in Silicon Gyroscope

Due to the huge potential applications in military and civil fields, silicon micro mechanical gyro has become the most popular research direction in MEMS field today. Therefore, the corresponding interface circuit of silicon gyroscope has also become a hot topic at home and abroad. Now, integration, digitalization and intelligence has become the focus of future research directions of silicon gyroscope, so the research of analog to digital conversion circuit for gyroscope has become a research priority. Therefore, the conduct of Sigma Delta ADCs research for silicon gyro interface circuit has a very important significance and application prospects.This topic briefly introduces the working principle of Sigma Delta ADC. Based on the requirements of the modulator design, Sigma Delta modulator structures are carefully analyzed and also carried on the comparison and optimization. Hereby, a three order three bits quantization in single-loop with partial feedback of feed-forward summation system structure for modulator is designed in this paper, and then the ideal model of modulator system in Matlab is simulated. In addition, the focus of this topic is mainly on the nonlinear factors analysis and modeling, and the Data Weighted Average (DWA) technique used in multi-bit quantization is introduced as well as modeling in system level. Then, the non-ideal modeling of system is simulated in Matlab.In system level design, this paper adopts feed-forward summation and multi-bit quantization structure to reduce the output of the integrator, increase the noise performance of the modulator, and make it easier for the system stability. Furthermore, the use of partial feedback in the structure for zero-point optimization improves the noise shaping ability in signal bandwidth of modulator. This topic employs the single-loop third-order three-bit quantization structure, with the sampling rate 64, signal bandwidth 200 K Hz and the sampling clock frequency 25.6 MHz. For the ideal modeling, the Signal-to-Noise Ratio (SNR) is 125dB, and the Effective Number of Bits (ENOB) is 20.48. When in consideration of modulator’s nonlinear factors, the nonlinear systems Simulink simulation results obtained SNR of 104dB, and the ENOB is 16.98.In order to reduce the harmonic distortion of the modulator, transistor level is implemented by fully-differential switch capacitor circuit. The structure at all levels of the integrator was optimized. To reduce the influence of flicker noise, the integrator adopts Correlated Double Sampling (CDS) technology, and is improved by the partial feedback circuit. The fully-differential operational amplifier with high slew-rate and high bandwidth is designed, and uses switch capacitor circuit as common-mode feedback. Dynamic comparator and multi-bit quantizer are designed to improve the speed of the quantizer and reduce power consumption. The design the nonlinear compensation feedback DAC module--DWA module circuit--realizes noise shaping of capacitance matching error. The overall circuit was simulated in Cadence by 0.6um process. Transistor-level simulation result shows that the SNR is 101.3dB, and the effective number of bits is 16.54bits. The simulation results are consistent with the established non-ideal model of modulator, which verifies the correction of system level design method.

Study of self-calibrating MEMS accelerometers

Micro-electromechanical System(MEMS) accelerometers are widely used in a number of inertial navigation systems and vibration detection system thanks to their small size, low cost and low power consumption. In order to improve their performance, the accelerometers have been designed to compensate the zero-bias caused by process variations. A new method of self-calibration sensitivity applies a self-test structure to simulate standard acceleration; depending on the standard and real-time values of the accelerometer’s output and by adjustment of the time division feedback, the scale factor of capacitive accelerometers can be flexibly adjusted to achieve sensitivity in self-calibrating MEMS accelerometers. Moreover, this research also uses the following: a PID feedback structure to improve the stability of the closed-loop system; a correlated double sampling (CDS) circuit to attenuate noise, which can eliminate zero drift caused by offset voltage of the pre-amplifier; a time division multiplexing electrostatic force feedback circuit to achieve the operation of a closed-loop micro-accelerometer. The structure can completely avoid electrostatic feedback coupling with a capacitance change detection circuit, which can also improve the bandwidth and stability of the accelerometer. By means of capacitance compensation array the zero-bias performance of accelerometers can be improved. The bias stability of the accelerometer can be reduced from 173mg to 31mg by testing.

A high speed CMOS image sensor with a novel digital correlated double sampling and a differential difference amplifier.

In order to increase the operating speed of a CMOS image sensor (CIS), a new technique of digital correlated double sampling (CDS) is described. In general, the fixed pattern noise (FPN) of a CIS has been reduced with the subtraction algorithm between the reset signal and pixel signal. This is because a single-slope analog-to-digital converter (ADC) has been normally adopted in the conventional digital CDS with the reset ramp and signal ramp. Thus, the operating speed of a digital CDS is much slower than that of an analog CDS. In order to improve the operating speed, we propose a novel digital CDS based on a differential difference amplifier (DDA) that compares the reset signal and the pixel signal using only one ramp. The prototype CIS has been fabricated with 0.13 µm CIS technology and it has the VGA resolution of 640 × 480. The measured conversion time is 16 µs, and a high frame rate of 131 fps is achieved at the VGA resolution.

A Low-Jitter Fast-Locking Multi-phase Clock for High Resolution CCD Processor

ABSTRACTA multi-phase clock circuit for a 14 bit 80 MHz charge-coupled device (CCD) signal processor is designed based on the Delay-Locked Loop (DLL) structure. To accelerate the DLL locking time, a new fast locking controller circuit is proposed in this paper. Besides, a low jitter delay cell circuit is used to reduce the influence of the jitter generated by multiple phase clock generating circuit on the performance of correlated double sampling (CDS) and A/D conversion in the high resolution CCD signal processor. A clock signal with adjustable phase for the CCD signal processor can be obtained by changing the value of the edge selected register. The proposed clock circuit implemented and simulated with SMIC 0.18 μm 3.3 V 1P6M mixed CMOS process and the area of layout is 1000 × 350 μm. Under the condition of TT/3.3V/27 °C, the simulation results with the input clock frequency of 80 MHz show that the DLL locking time is 1.3 μs. Besides, the peak-to-peak jitter is 1.09 ps and the RMS jitter is 182 fs.

A New CDS Structure for High Density FPA with Low Power

Being an essential part of infrared readout integrated circuit, correlated double sampling (CDS) circuits play important roles in both depressing reset noise and conditioning integration signals. To adapt applications for focal planes of large format and high density, a new structure of CDS circuit occupying small layout area is proposed, whose power dissipation has been optimized by using MOSFETs in operation of subthreshold region, which leads to 720 nW. Then the noise calculation model is established, based on which the noise analysis has been carried out by the approaches of transfer function and numerical simulations using SIMULINK and Verilog-A. The results are in good agreement, demonstrating the validity of the present noise calculation model. Thermal noise plays a dominant role in the long wave situation while 1/f noise is the majority in the medium wave situation. The total noise of long wave is smaller than medium wave, both of which increase with the integration capacitor and integration time increasing.

Non-uniformity study on readout circuit for uncooled IR detector

For long line uncooled infrared detectors, the non-uniformity of different detecting elements is the key parameter in measuring the circuit performance. So far there have been few research reports in this area. Most uncooled infrared detector circuits require corresponding blind detector for readout circuit design, which increases the complexity of uncooled infrared detector. In addition, the performances of these circuits need to be further improved in practical applications. In order to achieve high performance readout of the long line uncooled infrared detectors, a kind of 160 element readout circuit based on current mirror is designed in this paper. The readout circuit is composed of current mirror input part, capacitor feedback transimpedance amplifier (CTIA), and correlated double sampling (CDS) output circuit. The circuit is fabricated by using the 0.5 micron technology. The non-uniformity of circuit is obviously improved by reasonable parameter setting and current mirror circuit layout. Transconductance amplifier CTIA with capacitance negative feedback is used in the circuit. The integral capacitor consists of three capacitors whose capacitances are 10 pF, 20 pF and 20 pF respectively, thus the circuit can realize different integration capacitances, which forms different magnifications. The circuit can meet different response rates of uncooled detectors. Folded-cascode structure is adopted as the CMOS differential amplifier. The open loop gain is over 80 dB. This single-state folded-cascode construct can overcome the two-stage amplifier’s disadvantages, which easily leads to oscillations. The CDS N SF (source follow) and P SF are adopted as the circuit output, the output swing can easily be greater than 2 V. On average, the CDS N SF and P SF power consumptions are very low. So the total power consumption of 160 line circuit is lower than 100 mW. In the test, the non-uniformity of the readout circuit decreases from 10% to 1%. This result is in accordance with simulation result on non-uniformity. The other test results of total power consumption and the output amplitude also agree with simulation results. The readout circuit has good noise characteristics and the output noise is lower than 1 mV. When the readout circuit and uncooled infrared detector are connected, the infrared signal can be well read out. When the integration time is 20 μups, the device response is 0.294 mV/Ω. The overall system performance is very good. This circuit design based on current mirror has laid the technical foundation for developing readout circuit of the very large scale uncooled infrared detector in the future.

A CMOS pixel sensor prototype for the outer layers of linear collider vertex detector

The International Linear Collider (ILC) expresses a stringent requirement for high precision vertex detectors (VXD). CMOS pixel sensors (CPS) have been considered as an option for the VXD of the International Large Detector (ILD), one of the detector concepts proposed for the ILC. MIMOSA-31 developed at IPHC-Strasbourg is the first CPS integrated with 4-bit column-level ADC for the outer layers of the VXD, adapted to an original concept minimizing the power consumption. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal noise and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with a self-triggered analog-to-digital converter (ADC). The ADC design was optimized for power saving at a sampling frequency of 6.25 MS/s. The prototype chip is fabricated in a 0.35 μm CMOS technology. This paper presents the details of the prototype chip and its test results.