Core Microarchitecture Research Articles

An Intelligent Fault Alert Mechanism for Dynamic IoT Communication Microarchitecture

The usage Internet of Things (IoT) was maximized throughout the entire world. Hence, the different core processors incorporated microarchitecture makes this IoT communication system. However, the rise of faults due to the malicious event and the data overload might maximize energy and power utilization. So, the current study has proposed a novel Chimp-based Domain adaptation Alert System (CbDAAS) for the dynamic IoT communication microarchitecture. Before initiating the communication sharing process, the present fault in the designed IoT dynamic core microarchitecture was predicted, and those cores were removed for the current data broadcasting process. Henceforth, the designed fault alert microarchitecture is tested in the MATLAB platform. The reliability was valued using different metrics like power usage, energy consumption and detection exactness value. Finally, the validated metrics were compared with the associated studies and scored the finest outcome in fault detection score as 98% and less energy usage at 0.025mj.

Design of High Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications

Abstract: Numerous current and future applications aim to create highly efficient central processing units (CPUs). The RISC V processor micro-architecture is one illustration of a design that satisfies the necessities. The RISC-V Instruction Set Architecture [ISA] provides support for the micro-architecture. The instruction set architecture and the micro-architecture of a processor are two of the most crucial aspects of its design. The multiplier and divider circuits have a relatively high level of hardware complexity compared to other stages of the instruction execution process, which must be taken into account in any core microarchitecture. The construction of an appropriate hardware circuit that is capable of multiplication and division determines the overall size, power, and performance of a core. This center has four phases, and during those stages, each guidance is done, except for stacking and putting away information. The arithmetic operations can be completed within one clock cycle. On the other hand, the division and multiplication operations are repeated in an effort to shorten the critical path latency.

The Forward Slice Core: A High-Performance, Yet Low-Complexity Microarchitecture

Superscalar out-of-order cores deliver high performance at the cost of increased complexity and power budget. In-order cores, in contrast, are less complex and have a smaller power budget, but offer low performance. A processor architecture should ideally provide high performance in a power- and cost-efficient manner. Recently proposed slice-out-of-order (sOoO) cores identify backward slices of memory operations which they execute out-of-order with respect to the rest of the dynamic instruction stream for increased instruction-level and memory-hierarchy parallelism. Unfortunately, constructing backward slices is imprecise and hardware-inefficient, leaving performance on the table. In this article, we propose Forward Slice Core (FSC ), a novel core microarchitecture that builds on a stall-on-use in-order core and extracts more instruction-level and memory-hierarchy parallelism than slice-out-of-order cores. FSC does so by identifying and steering forward slices (rather than backward slices) to dedicated in-order FIFO queues. Moreover, FSC puts load-consumers that depend on L1 D-cache misses on the side to enable younger independent load-consumers to execute faster. Finally, FSC eliminates the need for dynamic memory disambiguation by replicating store-address instructions across queues. Considering 3-wide pipeline configurations, we find that FSC improves performance by 27.1%, 21.1%, and 14.6% on average compared to Freeway, the state-of-the-art sOoO core, across SPEC CPU2017, GAP, and DaCapo, respectively, while at the same time incurring reduced hardware complexity. Compared to an OoO core, FSC reduces power consumption by 61.3% and chip area by 47%, providing a microarchitecture with high performance at low complexity.

A Next-Generation Cryogenic Processor Architecture

Cryogenic computing can achieve high performance and power efficiency by dramatically reducing the device’s leakage power and wire resistance at low temperatures. Recent advances in cryogenic computing focus on developing cryogenic-optimal cache and memory devices to overcome memory capacity, latency, and power walls. However, little research has been conducted to develop a cryogenic-optimal core architecture even with its high potentials in performance, power, and area efficiency. In this article, we first develop CryoCore-Model, a cryogenic processor modeling framework that can accurately estimate the maximum clock frequency of processor models running at 77 K. Next, driven by the modeling tool, we design CryoCore, a 77 K-optimal core microarchitecture to maximize the core’s performance and area efficiency while minimizing the cooling cost. The proposed cryogenic processor architecture, in this article, achieves the large performance improvement and power reduction and, thus, contributes to the future of high-performance and power-efficient computer systems.

Marvell ThunderX3: Next-Generation Arm-Based Server Processor

Marvell ThunderX3 is the third-generation Arm-based server processor from Marvell. This article describes the architecture of ThunderX3, going into details of core microarchitecture. ThunderX3 is distinctive among mainstream processors in supporting four SMT threads. The article describes the threading microarchitecture of ThunderX3 and highlights threading benefits. The article also touches on the on-chip interconnect and L3-cache and the power management subsystem. Initial benchmark results from silicon show 30%+ single thread and up to 3X socket level performance gains over the prior generation resulting in industry-leading single thread and socket level performance.

A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications

Design of high-performance processors with very low power requirement is the primary goal of many contemporary and futuristic applications. This brief presents a novel processor micro-architecture which is capable of achieving these requirements. The micro-architecture is based on RISC-V Instruction Set Architecture (ISA). The core is implemented and verified on Xilinx Virtex-7 FPGA board with a resource requirement of 7617 LUTs and 2319 FFs. This core could achieve a Dhrystone benchmark score of 1.71 DMIPS per MHz which is higher than ARM Cortex-M3 (1.50 DMIPS per MHz) and ARM Cortex-M4 (1.52 DMIPS per MHz). The Coremark benchmark is also tested on this core and it gives 4.13 Coremark per MHz. The physical design result of the core using commercial tools shows that it can achieve a maximum frequency of 198.02 MHz with 0.036 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area and 17.36 μW/MHz power requirement at UMC 40 nm technology node. The core consumes a dynamic power of 19.75 μW/MHz at UMC 90nm which is 36% and 40% better than ARM Cortex-M3 and Cortex-M4 respectively and also lower than many others cores. The results show that this core can outperform many existing commercial and open-source cores.

Micro-architectural analysis of OLAP

Understanding micro-architectural behavior is important for efficiently using hardware resources. Recent work has shown that in-memory online transaction processing (OLTP) systems severely underutilize their core micro-architecture resources [29]. Whereas, online analytical processing (OLAP) workloads exhibit a completely different computing pattern. OLAP workloads are read-only, bandwidth-intensive, and include various data access patterns. With the rise of column-stores, they run on high-performance engines that are tightly optimized for modern hardware. Consequently, micro-architectural behavior of modern OLAP systems remains unclear. This work presents a micro-architectural analysis of a set of OLAP systems. The results show that traditional commercial OLAP systems suffer from their long instruction footprint, which results in high response times. High-performance columnstores execute tight instruction streams; however, they spend 25 to 82% of their CPU cycles on stalls both for sequential- and random-access-heavy workloads. Concurrent query execution can improve the utilization, but it creates interference in the shared resources, which results in sub-optimal performance.

Design and implementation of an elastic processor with hyperthreading technology and virtualization for elastic server models

The server models functioning in the industry are required to be more elastic in nature. They are constantly scaling-up and scaling-down on required computation power depending on different conditions. These elastic cloud platforms use accelerators like DSP’s, TPU’s, GPU’s, FPGA’s, and multi-core processors to provide exponential computing power and outsource their services. This process is not only costly and non-efficient but is also responsible for damaging the server’s hardware architecture. Furthermore, these additions degrade the level of threading and symmetric parallel processing capability of the architecture. Intel uses hyperthreading technology (HTT) to split the workload between hardware and operating system to avoid additions, but that too is only possible up until a certain limit. This paper presents design methodology and implementation of an elastic-natured 32-bit RISC-pipelined processor inspired from Intel Xeon and MIPS to function as a standard integrated platform for server models. It implements concepts of hyperthreading technology (HTT) and virtualization on hardware basis. It will allow to derive multiple outputs from units on hardware basis to enhance security and performance without compromising compatibility. The designed elastic core uses a probabilistic node-based closed-queuing network model for server analysis and implementation. Hence, elastic behavior from individual core microarchitecture to server model architecture enables a generic automated scaling self-aware optimization architecture.

Simulation of the Super-scalar Processor Core Operation

The article considers the features of super-scalar processors, their way of performing several operations on several pairs of operands simultaneously. The research focuses on the organization of processor pipeline execution operation of several machine instructions in one processor core. The simulating kit was developed for better understanding of a processor core microarchitecture. It includes two parts: program and methodical recommendations with multiple task options. The simulating kit demonstrates the pipeline architecture consisting of two clusters: front-end and back-end and the principle of translating complex multi-cycle CISC-like instructions into simpler RISC-like micro-operations. The main types of machine instructions are considered: data transfer between registers and memory cells (four variations), data processing of couple of operands from registers and memory cells (four variations), conditional jump to the specified address. The program-simulator makes it possible to conduct a more detailed simulation of one of the three mechanisms for calculations accelerating in the processor core: multi-functional (super-scalar) processing, out-of-order processing, speculative instructions execution after the branch prediction. The simulating kit is used in educational process when training masters of Higher School of Economics National Research University.

IBM POWER9 processor core

The IBM POWER9 processor is the latest Reduced Instruction Set Computer microprocessor from IBM. POWER9 employs a new modular core microarchitecture to counter the technology trend of decreasing frequency and increasing power density from generation to generation. The new POWER9 design enables a family of processors optimized for a broad range of server applications. The new microarchitecture is closely coupled with a rich set of new instructions geared toward data-centric applications. In this paper, we describe the POWER9 core microarchitecture innovations, its new instructions and features, and the exploitation of this new design for computing in the cognitive era.

IBM Power9 Processor Architecture

The IBM Power9 processor has an enhanced core and chip architecture that provides superior thread performance and higher throughput. The core and chip architectures are optimized for emerging workloads to support the needs of next-generation computing. Multiple variants of silicon target the scale-out and scale-up markets. With a new core microarchitecture design, along with an innovative I/O fabric to support several accelerated computing requirements, the Power9 processor meets the diverse computing needs of the cognitive era and provides a platform for accelerated computing.

Asymmetry-aware work-stealing runtimes

Amdahl's law provides architects a compelling reason to introduce system asymmetry to optimize for both serial and parallel regions of execution. Asymmetry in a multicore processor can arise statically (e.g., from core microarchitecture) or dynamically (e.g., applying dynamic voltage/frequency scaling). Work stealing is an increasingly popular approach to task distribution that elegantly balances task-based parallelism across multiple worker threads. In this paper, we propose asymmetry-aware work-stealing (AAWS) runtimes, which are carefully designed to exploit both the static and dynamic asymmetry in modern systems. AAWS runtimes use three key hardware/software techniques: work-pacing, work-sprinting, and work-mugging. Work-pacing and work-sprinting are novel techniques that combine a marginal-utility-based approach with integrated voltage regulators to improve performance and energy efficiency in high- and low-parallel regions. Work-mugging is a previously proposed technique that enables a waiting big core to preemptively migrate work from a busy little core. We propose a simple implementation of work-mugging based on lightweight user-level interrupts. We use a vertically integrated research methodology spanning software, architecture, and VLSI to make the case that holistically combining static asymmetry, dynamic asymmetry, and work-stealing runtimes can improve both performance and energy efficiency in future multicore systems.

Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching

Mobile and PC/server class processor companies continue to roll out flagship core microarchitectures that are faster than their predecessors. Meanwhile placing more cores on a chip coupled with constant supply voltage puts per-core energy consumption at a premium. Hence, the challenge is to find future microarchitecture optimizations that not only increase performance but also conserve energy. Eliminating branch mispredictions—which waste both time and energy—is valuable in this respect. In this paper, we explore the control-flow landscape by characterizing mispredictions in four benchmark suites. We find that a third of mispredictions-per-1K-instructions (MPKI) come from what we call separable branches: branches with large control-dependent regions (not suitable for if-conversion), whose backward slices do not depend on their control-dependent instructions or have only a short dependence. We propose control-flow decoupling (CFD) to eradicate mispredictions of separable branches. The idea is to separate the loop containing the branch into two loops: the first contains only the branch’s predicate computation and the second contains the branch and its control-dependent instructions. The first loop communicates branch outcomes to the second loop through an architectural queue. Microarchitecturally, the queue resides in the fetch unit to drive timely, non-speculative branching. On a microarchitecture configured similar to Intel’s Sandy Bridge core, CFD increases performance by up to 55 percent, and reduces energy consumption by up to 49 percent (for CFD regions). Moreover, for some applications, CFD is a necessary catalyst for future complexity-effective large-window architectures to tolerate memory latency.

Manycore network interfaces for in-memory rack-scale computing

Datacenter operators rely on low-cost, high-density technologies to maximize throughput for data-intensive services with tight tail latencies. In-memory rack-scale computing is emerging as a promising paradigm in scale-out datacenters capitalizing on commodity SoCs, low-latency and high-bandwidth communication fabrics and a remote memory access model to enable aggregation of a rack's memory for critical data-intensive applications such as graph processing or key-value stores. Low latency and high bandwidth not only dictate eliminating communication bottlenecks in the software protocols and off-chip fabrics but also a careful on-chip integration of network interfaces. The latter is a key challenge especially in architectures with RDMA-inspired one-sided operations that aim to achieve low latency and high bandwidth through on-chip Network Interface (NI) support. This paper proposes and evaluates network interface architectures for tiled manycore SoCs for in-memory rack-scale computing. Our results indicate that a careful splitting of NI functionality per chip tile and at the chip's edge along a NOC dimension enables a rack-scale architecture to optimize for both latency and bandwidth. Our best manycore NI architecture achieves latencies within 3% of an idealized hardware NUMA and efficiently uses the full bisection bandwidth of the NOC, without changing the on-chip coherence protocol or the core's microarchitecture.

The load slice core microarchitecture

Driven by the motivation to expose instruction-level parallelism (ILP), microprocessor cores have evolved from simple, in-order pipelines into complex, superscalar out-of-order designs. By extracting ILP, these processors also enable parallel cache and memory operations as a useful side-effect. Today, however, the growing off-chip memory wall and complex cache hierarchies of many-core processors make cache and memory accesses ever more costly. This increases the importance of extracting memory hierarchy parallelism (MHP), while reducing the net impact of more general, yet complex and power-hungry ILP-extraction techniques. In addition, for multi-core processors operating in power- and energy-constrained environments, energy-efficiency has largely replaced single-thread performance as the primary concern. Based on this observation, we propose a core microarchitecture that is aimed squarely at generating parallel accesses to the memory hierarchy while maximizing energy efficiency. The Load Slice Core extends the efficient in-order, stall-on-use core with a second in-order pipeline that enables memory accesses and address-generating instructions to bypass stalled instructions in the main pipeline. Backward program slices containing address-generating instructions leading up to loads and stores are extracted automatically by the hardware, using a novel iterative algorithm that requires no software support or recompilation. On average, the Load Slice Core improves performance over a baseline in-order processor by 53% with overheads of only 15% in area and 22% in power, leading to an increase in energy efficiency (MIPS/Watt) over in-order and out-of-order designs by 43% and over 4.7×, respectively. In addition, for a power- and area-constrained many-core design, the Load Slice Core outperforms both in-order and out-of-order designs, achieving a 53% and 95% higher performance, respectively, thus providing an alternative direction for future many-core processors.

IBM POWER8 processor core microarchitecture

The POWER8™ processor is the latest RISC (Reduced Instruction Set Computer) microprocessor from IBM. It is fabricated using the company's 22-nm Silicon on Insulator (SOI) technology with 15 layers of metal, and it has been designed to significantly improve both single-thread performance and single-core throughput over its predecessor, the POWER7® processor. The rate of increase in processor frequency enabled by new silicon technology advancements has decreased dramatically in recent generations, as compared to the historic trend. This has caused many processor designs in the industry to show very little improvement in either single-thread or single-core performance, and, instead, larger numbers of cores are primarily pursued in each generation. Going against this industry trend, the POWER8 processor relies on a much improved core and nest microarchitecture to achieve approximately one-and-a-half times the single-thread performance and twice the single-core throughput of the POWER7 processor in several commercial applications. Combined with a 50% increase in the number of cores (from 8 in the POWER7 processor to 12 in the POWER8 processor), the result is a processor that leads the industry in performance for enterprise workloads. This paper describes the core microarchitecture innovations made in the POWER8 processor that resulted in these significant performance benefits.

Towards improved parallelism through order reduction of accessing data in nD matrices

This paper encompasses the presentation of an enhanced approach with the capacity to reduce the time complexity of accessing nodes in m-dimensional matrices from $$O(n^m)$$O(nm) to $$O(n\log n)$$O(nlogn). The accomplishment of this process is attained by the serialization of nD (nD) matrices to single-dimensional arrays followed by the access of nodes accordingly. Linear representation of nD matrix data structure induces a superior parallelism of matrix calculations over dense, parallel core micro-architecture computers, including NVIDIA GPGPU Supercomputing and Intel Xeon Phi processing boards. This approach is feasibly implemented as the core of matrix data representation in Math software such as Matlab, Mathematica and Maple, in IDEs for more optimized code generation and in Parallel Computing Libraries such as CUBLAS and Magma.

Improving the energy efficiency of big cores

Traditionally, architectural innovations designed to boost single-threaded performance incur overhead costs which significantly increase power consumption. In many cases the increase in power exceeds the improvement in performance, resulting in a net increase in energy consumption. Thus, it is reasonable to assume that modern attempts to improve singlethreaded performance will have a negative impact on energy efficiency. This has led to the belief that "Big Cores" are inherently inefficient. To the contrary, we present a study which finds that the increased complexity of the core microarchitecture in recent generations of the IntelR Core™ processor have reduced both the time and energy required to run various workloads. Moreover, taking out the impact of process technology changes, our study still finds the architecture and microarchitecture changes ---such as the increase in SIMD width, addition of the frontend caches, and the enhancement to the out-of-order execution engine--- account for 1.2x improvement in energy efficiency for these processors. This paper provides real-world examples of how architectural innovations can mitigate inefficiencies associated with "Big Cores" ---for example, micro-op caches obviate the costly decode of complex x86 instructions--- resulting in a core architecture that is both high performance and energy efficient. It also contributes to the understanding of how microarchitecture affects performance, power and energy efficiency by modeling the relationship between them

Flicker

Future microprocessors may become so power constrained that not all transistors will be able to be powered on at once. These systems will be required to nimbly adapt to changes in the chip power that is allocated to general-purpose cores and to specialized accelerators. This paper presents Flicker , a general-purpose multicore architecture that dynamically adapts to varying and potentially stringent limits on allocated power. The Flicker core microarchitecture includes deconfigurable lanes --horizontal slices through the pipeline--that permit tailoring an individual core to the running application with lower overhead than microarchitecture-level adaptation, and greater flexibility than core-level power gating. To exploit Flicker's flexible pipeline architecture, a new online multicore optimization algorithm combines reduced sampling techniques, application of response surface models to online optimization, and heuristic online search. The approach efficiently finds a near-global-optimum configuration of lanes without requiring offline training, microarchitecture state, or foreknowledge of the workload. At high power allocations, core-level gating is highly effective, and slightly outperforms Flicker overall. However, under stringent power constraints, Flicker significantly outperforms core-level gating, achieving an average 27% performance improvement.

Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management

To harness the potential of CMPs for scalable, energy-efficient performance in general-purpose computers, the Apple-CORE project has co-designed a general machine model and concurrency control interface with dedicated hardware support for concurrency management across multiple cores. Its SVP interface combines dataflow synchronisation with imperative programming, towards the efficient use of parallelism in general-purpose workloads. Its implementation in hardware provides logic able to coordinate single-issue, in-order multi-threaded RISC cores into computation clusters on chip, called Microgrids. In contrast with the traditional “accelerator” approach, Microgrids are components in distributed systems on chip that consider both clusters of small cores and optional, larger sequential cores as system services shared between applications. The key aspects of the design are asynchrony, i.e. the ability to tolerate irregular long latencies on chip, a scale-invariant programming model, a distributed chip resource model, and the transparent performance scaling of a single program binary code across multiple cluster sizes. This article describes the execution model, the core micro-architecture, its realization in a many-core, general-purpose processor chip and its software environment. This article also presents cycle-accurate simulation results for various key algorithmic and cryptographic kernels. The results show good efficiency in terms of the utilisation of hardware despite the high-latency memory accesses and good scalability across relatively large clusters of cores.