Copy Operations Research Articles

Component test toward single-flux-quantum processors

We have developed essential components for most of microarchitectures based on the single-flux-quantum (SFQ) logic. The circuit under test is composed of two registers, an ALU and a control unit, and made up of about 540 cells, 1600 Josephson junctions on 1.5 × 2.4 mm area. We have obtained the correct results by a sequence of several instructions, in which two integers are written into the registers with the LOAD and COPY operations, and then execute the ADD operation. Some of their functions were tested at both low and high frequencies. As a result, we found that the designed components could work at 15 GHz for the designed bias current and up to 18 GHz for higher bias currents.

Communication scheduling

The high arithmetic rates of media processing applications require architectures with tens to hundreds of functional units, multiple register files, and explicit interconnect between functional units and register files. Communication scheduling enables scheduling to these emerging architectures, including those that use shared buses and register file ports. Scheduling to these shared interconnect architectures is difficult because it requires simultaneously allocating functional units to operations and buses and register file ports to the communications between operations. Prior VLIW scheduling algorithms are limited to clustered register file architectures with no shared buses or register file ports. Communication scheduling extends the range of target architectures by making each communication explicit and decomposing it into three components: a write stub, zero or more copy operations, and a read stub. Communication scheduling allows media processing kernels to achieve 98% of the performance of a central register file architecture on a distributed register file architecture with only 9% of the area, 6% of the power consumption, and 37% of the access delay, and 120% of the performance of a clustered register file architecture on a distributed register file architecture with 56% of the area and 50% of the power consumption.

Communication scheduling

The high arithmetic rates of media processing applications require architectures with tens to hundreds of functional units, multiple register files, and explicit interconnect between functional units and register files. Communication scheduling enables scheduling to these emerging architectures, including those that use shared buses and register file ports. Scheduling to these shared interconnect architectures is difficult because it requires simultaneously allocating functional units to operations and buses and register file ports to the communications between operations. Prior VLIW scheduling algorithms are limited to clustered register file architectures with no shared buses or register file ports. Communication scheduling extends the range of target architectures by making each communication explicit and decomposing it into three components: a write stub, zero or more copy operations, and a read stub. Communication scheduling allows media processing kernels to achieve 98% of the performance of a central register file architecture on a distributed register file architecture with only 9% of the area, 6% of the power consumption, and 37% of the access delay, and 120% of the performance of a clustered register file architecture on a distributed register file architecture with 56% of the area and 50% of the power consumption.

Communication scheduling

The high arithmetic rates of media processing applications require architectures with tens to hundreds of functional units, multiple register files, and explicit interconnect between functional units and register files. Communication scheduling enables scheduling to these emerging architectures, including those that use shared buses and register file ports. Scheduling to these shared interconnect architectures is difficult because it requires simultaneously allocating functional units to operations and buses and register file ports to the communications between operations. Prior VLIW scheduling algorithms are limited to clustered register file architectures with no shared buses or register file ports. Communication scheduling extends the range of target architectures by making each communication explicit and decomposing it into three components: a write stub, zero or more copy operations, and a read stub. Communication scheduling allows media processing kernels to achieve 98% of the performance of a central register file architecture on a distributed register file architecture with only 9% of the area, 6% of the power consumption, and 37% of the access delay, and 120% of the performance of a clustered register file architecture on a distributed register file architecture with 56% of the area and 50% of the power consumption.

Operating system support for multimedia systems

Distributed multimedia applications will be an important part of tomorrow's application mix and require appropriate operating system (OS) support. Neither hard real-time solutions nor best-effort solutions are directly well suited for this support. One reason is the co-existence of real-time and best effort requirements in future systems. Another reason is that the requirements of multimedia applications are not easily predictable, like variable bit rate coded video data and user interactivity. In this article, we present a survey of new developments in OS support for (distributed) multimedia systems, which include: (1) development of new CPU and disk scheduling mechanisms that combine real-time and best effort in integrated solutions; (2) provision of mechanisms to dynamically adapt resource reservations to current needs; (3) establishment of new system abstractions for resource ownership to account more accurate resource consumption; (4) development of new file system structures; (5) introduction of memory management mechanisms that utilize knowledge about application behavior; (6) reduction of major performance bottlenecks, like copy operations in I/O subsystems; and (7) user-level control of resources including communication.

Development of CAM System Based on Simulation of the Copy Operation - An Application to the Boundary Representation Method and High Efficiency Machining -

A CAM system, based on a simulation of the servo data generation method of a copy milling machine, was developed. In this system, the tool path data can be calculated directly using the coordinates of the contact point between the defined shape and an imaginary stylus, without the preceding processes of generating an offset surface and checking the tool interference. For application of this algorithm to a model which is expressed using the boundary representation method, the algorithm was modified slightly. Since the contact point is regarded as the point nearest to the center of the imaginary stylus, which is on the model surface, all the intervals between the center of the imaginary stylus and the constructing surfaces which are close to it are calculated. The point which has the shortest interval is the nearest representative point of the model data and the contact point, in the case in which the interval is equal to the radius of the tool. A rough tool path, which is composed of an imaginary block and a spiral finishing tool path, which enables tools to feed with smooth cutting has been developed using this algorithm. Toolpath simulations and cutting tests show that the CAM system developed was able to generate appropriate CL data with high accuracy and reliability.

Design and implementation of flexible User Protocol Interface

This paper is focused on an efficient protocol implementation based on flexible User Protocol Interface (UPI) configurable for different service options and protocol processing architectures. The XTPL implementation discussed in this paper is developed based on the BERKOM eXpress Transfer Protocol (XTP) Lite version for HP 900017x Series using HP-UX 9.0 operating system. This implementation supports the dynamical configuration of user protocol interfaces intended to provide different objectives: - optimization of the user data copy operations (use of the copy architecture); - selectable QoS options for application layer framing, reliability and checksumming. Performance analyses are included to show the flexible use of user protocol interfaces, in particular the reliable single and dual copy interface, dependent on the application traffic of the connections.

Development of CAM System Based on Simulation of the Copy Operation

For high speed machining with rotating tools and a new type surface finishing with non-rotating cutting tools; it is necessary to develop a CAM system that can generate accurate CL data with high speed and high reliability. In order to extend CAM functions, a unified algorithm for CL data generation was developed that can be applied for both tools. This unified algorithm is based on simulating the servo data generation method of a copy milling machine. The tool path is defined in a calculation of contact points between the model and the stylus head. Therefore, preceding processes of offset surface generation and tool interference check can be abbreviated. The developed system has the following four tool path modes; (1) the scanning line, (2) the contour line, (3) the 3 D profile, and (4) the contour line roughing. Tool path simulations and cutting tests show that the developed system can generate CL data with high accuracy and reliability.

Update‐in‐Place Analysis for True Multidimensional Arrays

Applicative languages have been proposed for defining algorithms for parallel architectures because they are implicitly parallel and lack side effects. However, straightforward implementations of applicative‐language compilers may induce large amounts of copying to preserve program semantics. The unnecessary copying of data can increase both the execution time and the memory requirements of an application. To eliminate the unnecessary copying of data, the Sisal compiler uses both build‐in‐place and update‐in‐place analyses. These optimizations remove unnecessary array copy operations through compile‐time analysis. Both build‐in‐place and update‐in‐place are based on hierarchical ragged arrays, i.e., the vector‐of‐vectors array model. Although this array model is convenient for certain applications, many optimizations are precluded, e.g., vectorization. To compensate for this deficiency, new languages, such as Sisal 2.0, have extended array models that allow for both high‐level array operations to be performed and efficient implementations to be devised. In this article, we introduce a new method to perform update‐in‐place analysis that is applicable to arrays stored either in hierarchical or in contiguous storage. Consequently, the array model that is appropriate for an application can be selected without the loss of performance. Moreover, our analysis is more amenable for distributed memory and large software systems.

Development of CAM System Based on Simulation of the Copy Operation.

For a high speed machining and a new type surface finishing with non-rotating cutting tools, it is necessary to develop a CAM system that can generate accurate CL data with high speed and high reliability. In order to extend CAM functions, a unified algorithm for CL data generation that can be applied for both rotating cutting tools and non-rotating ones was developed which is based on simulating the servo data generation method of a copy milling machine. The model and the stylus head are represented by a CSG data structure, and the tool path is defined in a calculation of contact points between the model and the stylus head, and normal vector at contact point. Therefore, preceding processes of offset surface generation and tool interference check can be abbreviated. The developed system has following four tool path modes; (1) the scanning line mode, (2) the contour line mode, (3) the 3D profile mode, (4) the contour line roughing mode. The contour line mode is suitable for high-speed machining because it will provide stable cutting with a small variation in cutting loads. Tool path simulations and cutting tests show that the developed CAM system can generate CL data of various types of tool path mode with high accuracy and reliability.

Compile‐time copy elimination

AbstractSingle‐assignment and functional languages have value semantics that do not permit side‐effects. This lack of side‐effects makes automatic detection of parallelism and optimization for data locality in programs much easier. However, the same property poses a challenge in implementing these languages efficiently. This paper describes an optimizing compiler system that solves the key problem of aggregate copy elimination. The methods developed rely exclusively on compile‐time algorithms, including interprocedural analysis, that are applied to an intermediate data flow representation. By dividing the problem into update‐in‐place and build‐in‐place analysis, a small set of relatively simple techniques—edge substitution, graph pattern matching, substructure sharing and substructure targeting—was found to be very powerful. If combined properly and implemented carefully, the algorithms eliminate unnecessary copy operations to a very high degree. No run‐time overhead is imposed on the compiled programs.

An efficient and flexible method for archiving a data base

We describe an efficient method for supporting incremental and full archiving of data bases (e.g., individual files). Customers archive their data bases quite frequently to minimize the duration of data outage. Because of the growing sizes of data bases and the ever increasing need for high availability of data, the efficiency of the archive copy utility is very important. The method presented here minimizes interferences with concurrent transactions by not acquiring any locks on the data being copied. It significantly reduces disk I/Os by not keeping on data pages any extra tracking information in connection with archiving. These features make the archive copy operation be more efficient in terms of resource consumption compared to other methods. The method is also flexible in that it optionally supports direct copying of data from disks, bypassing the DBMS's buffer pool. This reduces buffer pool pollution and processing overheads, and allows the utility to take advantage of device geometries for efficiently retrieving data. We also describe extensions to the method to accommodate the multisystem shared disks transaction environment. The method tolerates gracefully system failures during the archive copy operation.

A treatment of unbounded dependencies in eurotra with an experimental coindexation tool

The purpose of this article is to present a treatment of unbounded dependencies which is currently being experimented with in Eurotra. The treatment is based on the coindexation tool designed by the authors as an extension to the E-Framework, Eurotra's NLP formalism. On the E-Framework, cf. Bech and Nygaard 1988, and Bech et al. (previous issue of this journal). A first extension to the framework, in terms of ‘recursion markers,’ was introduced by Allegranza (1988) and implemented in PROLOG by Giovanni Malnati. Allegranza and Bech (1989) integrated it with a structure-copying component due to Annelise Bech and Anders Nygaard. At present, the tool has been tested in a systematic way in the Danish, French, Italian, and Spanish modules of the Eurotra translation system. Testing work on other languages (especially German) is in progress. Our article is organized as follows: in section 1, we discuss the linguistic and translational motivations for the treatment presented here; in section 2, we give the syntax and semantics of the two main components of the coindexation tool, namely the recursion markers and the copy operator; section 3 shows how this machinery can be applied for the implementation of unbounded dependency constructions according to our approach.

Performance of a disk array protype

The RAID group at U.C. Berkeley recently built a prototype disk array. This paper examines the performance limits of each component of the array usiug SCSI bus traces, Sprite operating system traces and user programs.The array performs successfully for a workload of small, random I/O operations, achieving 275 I/Os per second on 14 disks before the Sun4/280 host becomes CPU-limited. The prototype is less successful in delivering high throughput for large, sequential operations. Memory system contention on the Sun4/280 host limits throughput to 2.3 MBytes/sec under the Sprite Operating System. Throughput is also limited by the bandwidth supported by the VME backplane, disk controller and disks, and overheads associated with the SCSI protocol.We conclude that merely using a powerful host CPU and many disks will not provide the full bandwidth possible from disk arrays. Host memory bandwidth and throughput of disk controllers are equally important. In addition, operating systems should avoid unnecessary copy and cache flush operations that can saturate the host memory system.

The Nature of Device Models: The Yoked State Space Hypothesis and Some Experiments With Text Editors

To construct a conceptual model of a device, the user must conceptualize the device's representation of the task domain. This knowledge can be represented by three components: a device-based problem space, which specifies the ontology of the device in terms of the objects that can be manipulated and their interrelations, plus the operators that perform the manipulations; a goal space, which represents the objects in terms of which user's goals are expressed; and a semantic mapping, which determines how goal space objects are represented in the device space. The yoked state space (YSS) model allows an important distinction concerning the mental representation of procedures. If a step in a procedure specifies a transformation of the user's device space, then it has an autonomous meaning for the user, independent of its role in the sequence or method. The device space provides a figurative account of the operator. However, some operators do not affect the minimal device space, and their only meaning for the user derives from their role in a method: The method affords an operational account of the operator. Figurative accounts can be constructed from operational accounts only by elaborating the device space with new concepts. The YSS is illustrated through a simple description of a device model for a cut-and-paste text editor. Three experiments addressed the claims of this model. The first experiment used a sorting paradigm to show that users do acquire the novel device space concept of a string of adjacent characters (including space and return). The second and third experiments asked novices to make inferences about text editor behavior on the basis of simple demonstrations. They showed that (a) the availability of the string concept is critically dependent on the details of interface design, (b) figurative accounts of the copy operation afford more efficient methods and may be promoted by appropriate names for procedure steps, and (c) a conceptual model may transfer from one device to another. Together, the three experiments supported the YSS hypothsis.

Modification of a multilevel indexed descriptor file

Multilevel indexed descriptor files have many advantages, such as fast retrieval of exact-, partial- and/or approximate-matches, easy file organization and record insertion, and little storage requirement for indexes. They, however, have a potential problem that a file search may need backtracking, i.e. the examination of more than one block at some level, even for retrieving exact-matches. This paper discusses a method of modifying the existing file structure so as to cope with this problem. The proposed modification algorithm copies the records requiring backtracking into new blocks from which each of them can be retrieved by examining only one block at any level. Also the copy operation does not involve additional costs for records not requiring backtracking. Computational experiments obtained from various generated and real-world data show that the algorithm can be implemented easily and work effectively.

The role of opaque types to build abstractions

This note examines the MODULA-2 approach to build data abstractions and abstract data types. MODULA-2 provides a byreference semantics by providing opaque types via pointers. The paper compares this mechanism with the one furnished by ADA (*). A comparison with object-oriented systems brings out the issue of assignment, copy and compare operations. That leads to a constructive methodology for abstract data types in MODULA-2. Any abstraction must furnish copy operations with two different semantics, respectively shallow and deep, and related equality and inequality operations.

Copying structured objects in a distributed system

A distributed system is modelled as a set of disjoint naming environments called contexts among which messages flow as the means of communication. A structured object is considered to be a list of the names of its components. Primitive objects contain no other objects as components. This paper presents an algorithm for copying objects across context boundaries. Each object resides within a context and has a locally unique name assigned to it. The components of a structured object may reside in other contexts. Three copy operations are proposed: (1) copy copies the complete structure without copying any component more than once; (2) copy-local copies all of the structure within the context of the object and directly accessible through the object without copying any component more than once, and sending to the receiver the globally unique names of those components not copied; (3) copy-top copies only the top level of the structure, sending to the receiver the globally unique names of all the components of the top level.