Coprocessor Research Articles

Design and Implementation of a 32-bit Floating Point Unit

A Floating Point Unit is a math co-processor that is in the most demand of Digital Signal Processing (DSP), Processors and more. It is used to perform functions or operations on floating point numbers like addition, subtraction, multiplication, division, square root and more. It is specifically designed to carry out mathematical operations and it can be emulated in CPU. Floating point unit is a common operation used in advanced Digital Signal Processing and various processor applications. The aim was to develop an optimized floating point unit so that the delay was reduced and efficiency was increased. The floating point unit has been written according to IEEE 754 standard and the entire design has been coded in Verilog HDL. The results are improved by 12% with the usage of Vedic multiplier that is a delay of 4.450ns as compared to 5.123ns with an array multiplier. Designs can be further optimized using low power designing techniques at architectural level. Different behaviour can be observed for different size and technologies.

Design of 128-bit Complex Number Multipliers for Co-Processor

Design of 128-bit Complex Number Multipliers for Co-Processor

A New Role for Coprocessors

A New Role for Coprocessors

Development of a low-cost quadrotor UAV based on ADRC for agricultural remote sensing.

Unmanned aerial vehicle (UAV) has the advantages of good repeatability and high remote sensing (RS) information acquisition efficiency, as an important supplement bridging the gap of high-altitude and ground RS platforms. A quadrotor UAV was developed for the agricultural RS application in this study. The control system consists of a main processor and a coprocessor, integrating a three-axis gyroscope, a three-axis accelerometer, an air pressure sensor and a global positioning system (GPS) module. Engineering trial method (ETM) was used to tune the parameters based on the active disturbance rejection control (ADRC) method. Also a ground control station (GCS) adapted to the quadrotor was developed realizing autonomously take-off and landing, flight route planning, data recording. To investigate the performances of the UAV, several flight tests were carried out. The test results showed that the pitch angle control accuracy error was less than 4°, the flight height control accuracy error was less than 0.86 m, the flight path control accuracy error was less than 1.5 m overall. Aerial multispectral images were acquired and processed. The reflected digital number (DN) values obtained from a height of 10-100 m with 10 m interval could be referenced to classify objects. The normalized-difference-vegetation index (NDVI) values obtained from the aerial multispectral images acquired at 15 m were compared with those obtained by the GreenSeeker (GS) and PSR-1100F. The maximum error was 20.37% while the minimum error was 1.99%, which demonstrated the developed quadrotor UAV’s satisfactions for low altitude remote sensing practice. This study provided a low-cost platform for agricultural remote sensing. Keywords: UAV, quadrotor, ADRC, agricultural remote sensing, NDVI, aerial spraying application DOI: 10.25165/j.ijabe.20191204.4641 Citation: Zhang S C, Xue X Y, Chen C, Sun Z, Sun T. Development of a low-cost quadrotor UAV based on ADRC for agricultural remote sensing. Int J Agric & Biol Eng, 2019; 12(4): 82–87.

A High‐Performance RSA Coprocessor Based on Half‐Carry‐Save and Dual‐Core MAC Architecture

A High‐Performance RSA Coprocessor Based on Half‐Carry‐Save and Dual‐Core MAC Architecture

30 Study on blood dynamic viscosity in arteries via CFD

Objectives Blood is a typical non-Newtonian fluid, and poor fluidity of blood is key to the pathogenesis of thrombus. The dynamic viscosity (high blood viscosity) of blood is a key factor in blood vessel embolization, especially cardiovascular and cerebrovascular embolisms. Computational fluid dynamics (CFD) is an efficient method for Newtonian or non-Newtonian fluid flow simulation. The finite volume method (FVM) is also an efficient numerical method for fluid dynamics simulation. This study aimed to investigate blood flow characteristics in arteries, and the dynamic viscosity is taken into account via the non-Newtonian fluids and CFD theory. Methods A series of numerical computations are presented to reproduce the process of blood flowing in arteries using the FVM code CFX. Blood flow simulation will be accelerated using the GPU parallel computation scheme with the CUDA-enabled GPU coprocessor. Results The dynamic viscosity and flow field of blood will be computed and shown by the contours. The velocity, shear strain rate and dynamic viscosity of blood can be calculated and monitored for different ages of people. Conclusions The dynamic viscosity and flow characteristics of blood in arteries can be reproduced using CFD and FVM. The mechanism of blood vessel embolization can be analyzed via the non-Newtonian fluids and CFD theory. Thrombus occurs when the rheology of blood is enhanced. Acknowledgements This research was financially supported by Shaanxi Hundred People Plan Foundation (Grant No. 302-253051601).

Double precision floating point core in verilog

A floating-point unit (FPU) is a math coprocessor, a part of a computer system specially designed to carry out operations on floating point numbers. The term floating point refers to the fact that the radix point can float; that is, it can placed anywhere with respect to the significant digits of the number. Double precision floating point, also known as double, is a commonly used format on PCs due to its wider range over single precision in spite of its performance and bandwidth cost. This paper aims at developing the verilog version of the double precision floating point core designed to meet the IEEE 754 standard .This standard defines a double as sign bit, exponent and mantissa. The aim is to build an efficient FPU that performs basic functions with reduced complexity of the logic used and also reduces the memory requirement as far as possible.

An Efficient Architecture for PCI Bus Design

In several application of embedded system, the digital components interconnects are needs flexible to power and area of the devices. Also it requires a bus width with several versions like 64 bits or 32 bits with different frequencies (Ex. 33 MHz or 66 MHz). PCI bus is used for connecting these hardware devices in computer. Instead of using different buses in computer, it can use single bus for different frequencies with multiplexing bus width. In order to solve this problem, this paper designs FPGA based PCI bus with these requirements. Through analysis of PCI bus, the top-down method applies on the PCI bus with several functional modules. Also it uses the master and target as coprocessor of the device which are programmed with finite state machine using VHDL language and structured in detail which helps to minimize the power consumption. For selecting bandwidth and frequency, it has used separate multiplexing module. Through the analysis of test bench and synthesis report it will prove that the bus complete requirements of power consumption on the basis of utilization of registers, CLB‟s and flip flops and helps to design with dual frequency.

A Customized Coprocessor Acceleration of Genome Re-Sequencing

A Customized Coprocessor Acceleration of Genome Re-Sequencing

A gentle introduction to the associative computing (ASC) model of parallel computation

Recent computing hardware technologies such as the Intel Xeon Phi and NVIDIA CUDA family of hardware coprocessors have had tremendous impact on how computer scientists program parallel computers. A...

MPI-CUDA sparse matrix–vector multiplication for the conjugate gradient method with an approximate inverse preconditioner

The preconditioned conjugate gradient (PCG) is one of the most prominent iterative methods for the solution of sparse linear systems with symmetric and positive definite matrix that arise, for example, in the modeling of incompressible flows. The method relies on a set of basic linear algebra operations which determine the overall performance. Therefore, to achieve improvements in the performance, implementations of these basic operations must be adapted to the changes in the architecture of parallel computing systems. In the last years, one of the strategies to increase the computing power of supercomputers has been the usage of Graphics Processing Units (GPUs) as math co-processors in addition to CPUs. This paper presents a MPI-CUDA implementation of the PCG solver for such hybrid computing systems composed of multiple CPUs and GPUs. Special attention has been paid to the sparse matrix–vector multiplication (SpMV), because most of the execution time of the solver is spent on this operation. The approximate inverse preconditioner, which is used to improve the convergence of the CG solver, is also based on the SpMV operation. An overlapping of data transfer and computations is proposed in order to hide the MPI and the CPU-GPU communications needed to perform parallel SpMVs. This strategy has shown a considerable improvement and, as a result, the hybrid implementation of the PCG solver has demonstrated a significant speedup compared to the CPU-only implementation.

A parallel MPI + OpenMP + OpenCL algorithm for hybrid supercomputations of incompressible flows

The work is devoted to the development of efficient parallel algorithms for large-scale simulations of incompressible flows on hybrid supercomputers based on massively-parallel accelerators. The governing equations are discretized using a high-order finite-volume scheme for Cartesian staggered meshes with the only restriction that, at least, one direction is periodic. Its “classical” MPI+OpenMP parallel implementation for CPUs was designed to scale till 100,000 CPU cores. The new hybrid algorithm is developed on a base of a multi-level parallel model that exploits several layers of parallelism of a modern hybrid supercomputer. In this model, MPI and OpenMP are used on the first two levels to couple nodes of a supercomputer and to engage its CPU cores. Then, computing accelerators are further used by means of the hardware independent OpenCL computing standard. In this way, the implementation is adapted to a general computing model with central processors and math co-processors. In this paper the work is focused on adapting the basic operations of the algorithm to architectures of Graphics Processing Units (GPU) without considering the multi-GPU communication scheme. Technology of porting the code to OpenCL is described, certain optimization approaches are presented and relevant performance results obtaining up to 80–90 GFLOPS on a GPU accelerator are demonstrated.Moreover, the experience with different GPU architectures is summarized and a comparison based on the particular application is given for AMD and NVIDIA GPUs as well as for CUDA and OpenCL frameworks.

An OpenCL-based Parallel CFD Code for Simulations on Hybrid Systems with Massively-parallel Accelerators

A parallel finite-volume CFD algorithm for modeling of incompressible flows on hybrid supercomputers is presented. It is based on a symmetry-preserving high-order numerical scheme for structured meshes. A multilevel approach that combines different parallel models is used for large-scale simulations on computing systems with massively-parallel accelerators. MPI is used on the first level within the distributed memory model to couple computing nodes of a supercomputer. On the second level OpenMP is used to engage multiple CPU cores of a computing node. The third level exploits the computing potential of massively-parallel accelerators such as GPU (Graphics Processing Units) of AMD and NVIDIA, or Intel Xeon Phi accelerators of the MIC (Many Integrated Core) architecture. The hardware independent OpenCL standard is used to compute on accelerators of different archi- tectures within a general model for a combination of a central processor and a math co-processor.

Enhancing Visual Rendering on Multicore Accelerators with Explicitly Managed Memories

Recent electronic devices are equipped with processors extended with multicore accelerators to take advantage of the powerful performance from acceleration co-processors. Applications on such high-end electronic products require capability to run graphic-rich applications. Scalable acceleration co-processors are frequently designed as multicores with explicitly managed memories. Such multicore architectures require sophisticated data management among the main memory and the local memories to fully exploit their potential performance. Ray tracing is a high quality rendering algorithm in computer graphics and has potentially many parallelism to exploit. On the explicitly managed memory hierarchies, however, ray tracing with complex data structures tends to suffer from irregular memory accesses and inefficient data management. Compared to other acceleration structures for ray tracing, grid structure is simple to manage but commonly regarded to produce too slow algorithms. However, recent improvements on grid structure with SIMD optimizations show comparable performance with kd-tree structure, which is one of the fastest acceleration structures. We introduce a grid structure based parallel ray tracer on a processor with a multicore accelerator. We adopt SIMD optimizations and double buffering to enhance the performance of grid-based ray tracer and propose a macrocell structure over the grid to fully exploit the memory bandwidth. In our experiment, our ray tracing scheme shows comparable performance with BVH-based ray tracer.

A user configurable data acquisition and signal processing system for high-rate, high channel count applications

Real-time signal processing in plasma fusion experiments is required for control and for data reduction as plasma pulse times grow longer. The development time and cost for these high-rate, multichannel signal processing systems can be significant. This paper proposes a new digital signal processing (DSP) platform for the data acquisition system that will allow users to easily customize real-time signal processing systems to meet their individual requirements.The D-TACQ reconfigurable user in-line DSP (DRUID) system carries out the signal processing tasks in hardware co-processors (CPs) implemented in an FPGA, with an embedded microprocessor (μP) for control. In the fully developed platform, users will be able to choose co-processors from a library and configure programmable parameters through the μP to meet their requirements.The DRUID system is implemented on a Spartan 6 FPGA, on the new rear transition module (RTM-T), a field upgrade to existing D-TACQ digitizers.As proof of concept, a multiply-accumulate (MAC) co-processor has been developed, which can be configured as a digital chopper-integrator for long pulse magnetic fusion devices. The DRUID platform allows users to set options for the integrator, such as the number of masking samples. Results from the digital integrator are presented for a data acquisition system with 96 channels simultaneously acquiring data at 500kSamples/s per channel.

A unified co-processor architecture for matrix decomposition

QR and LU decompositions are the most important matrix decomposition algorithms. Many studies work on accelerating these algorithms by FPGA or ASIC in a case by case style. In this paper, we propose a unified framework for the matrix decomposition algorithms, combining three QR decomposition algorithms and LU algorithm with pivoting into a unified linear array structure. The QR and LU decomposition algorithms exhibit the same two-level loop structure and the same data dependency. Utilizing the similarities in loop structure and data dependency of matrix decomposition, we unify a fine-grained algorithm for all four matrix decomposition algorithms. Furthermore, we present a unified coprocessor structure with a scalable linear array of processing elements (PEs), in which four types of PEs are same in the structure of memory channels and PE connections, but the only difference exists in the internal structure of data path. Our unified co-processor, which is IEEE 32-bit floating-point precision, is implemented and mapped onto a Xilinx Virtex5 FPGA chip. Experimental results show that our co-processors can achieve speedup of 2.3 to 14.9 factors compared to a Pentium Dual CPU with double SSE threads.

Parallel, Distributed and Network-based Computing: an Application Perspective

Parallel, distributed and network-based computing is a continuosly evolving field, driven by progress in microprocessor architecture and interconnection technology, as well as by the needs of computing- and data-intensive applications in science and engineering, and, more recently, in business. This field is currently undergoing a significant change, because of the development of multicore and manycore processors, GPUs, and FPGAs, which are the new building blocks of parallel architectures. At the other end of the parallel and distributed computing scenario, computational grids are far from being a mature infrastructure and are evolving toward cloud computing, to get a higher level of virtualization. The availability of programming models, algorithms and software tools capable of harnessing the processing power offered by the new technologies is a key issue to make them usable by application developers. This special issue provides a view of the efforts carried out in this direction. Barlas introduces an optimization approach for reducing data communication and load imbalance in medical image matching on Grids. Binzenhofer et al. present a distributed and scalable algorithm to monitor a p2p network. Cesario and Talia discuss the use of data mining models and services on Grid systems for analysis of large data repositories. Danelutto et al. describe a performance model for component-based applications with stream communication semantics running on Grids. Danese et al. describe a FPGA-based coprocessor to accelerate double precision floating point operations in high-performance applications. Gross and Marquardt introduce a graphical editor providing abstractions from base technology for user-friendly configuration of Ubiquitous Computing environments. The papers collected here are selected extended versions of papers presented at PDP 2007, the Fifteenth Euromicro Conference on Parallel, Distributed and Network-based Processing, held in Naples, Italy, in February 2007. The conference was organized by the Institute for High-Performance Computing and Networking (ICAR) of the Italian National Research Council (CNR) in collaboration with the Second University of Naples, the University of Naples Parthenope and the University of Naples Federico II. We thank the editors of Scalable Computing: Practice and Experience for providing us the opportunity of publishing this issue, the authors for their contributions, and the referees for their precious help in selecting good-quality papers. Pasqua D'Ambra Institute for High-Performance Computing and Networking (ICAR), CNR Naples, Italy pasqua.dambra@cnr.it Daniela di Serafino Department of Mathematics, Second University of Naples Caserta, Italy daniela.diserafino@unina2.it Mario Rosario Guarracino Institute for High-Performance Computing and Networking (ICAR), CNR Naples, Italy mario.guarracino@cnr.it Francesca Perla Department of Statistics and Mathematics for Economic Research, University of Naples Parthenope Naples, Italy francesca.perla@uniparthenope.it

A game loop architecture for the GPU used as a math coprocessor in real-time applications

This article concerns the use of a graphics processor unit (GPU) as a math co-processor in real-time applications in special games and physics simulations. To validate this approach, we present a new game loop architecture that employs GPUs for general-purpose computations (GPGPUs). A critical issue here is the process distribution between the CPU and the GPU. The architecture consists of a model for distribution, and our implementation offers many advantages in comparison to other approaches without the GPGPU stage. This architecture can be used either by a general-purpose language such as the Compute Unified Device Architecture (CUDA), or shader languages such as the High-Level Shader Language (HLSL) and the OpenGL Shading Language (GLSL). Although the architecture proposed here aims at supporting mathematics and physics on the GPU, it is possible to adapt any kind of generic computation. This article discusses the model implementation in an open-source game engine and presents the results of using this platform.

FAST BIVARIATE FUNCTION RENDERING FOR SMALL DEVICES

AbstractIn the actual scenario of small devices, such as smartphones and handhelds, the usual graphic algorithms need a deep adaptation. The characteristics that constrain small devices with respect to personal computers include significantly less CPU power, smaller memory, and small screen lacking specialized hardware.We propose an algorithm for hidden lines rendering of 3D surfaces that are mathematically represented by single-valued continuous functions of two variables. Our proposal is significantly faster than the traditional ones. Moreover, our proposal requires a predefined amount of memory that depends solely on the window size of the screen.Our approach takes advantage of a fast, coordinates transformation from the continuous to the discrete. The algorithm operates in screen coordinates, i.e., the pixels, hence almost all the computations are made by means of integer arithmetic and do not require any math coprocessor.

Fast Bivariate Function Rendering For Small Devices

In the actual scenario of small devices, such as smartphones and handhelds, the usual graphic algorithms need a deep adaptation. The characteristics that constrain small devices with respect to personal computers include significantly less CPU power, smaller memory, and small screen lacking specialized hardware.We propose an algorithm for hidden lines rendering of 3D surfaces that are mathematically represented by single-valued continuous functions of two variables. Our proposal is significantly faster than the traditional ones. Moreover, our proposal requires a predefined amount of memory that depends solely on the window size of the screen.Our approach takes advantage of a fast, coordinates transformation from the continuous to the discrete. The algorithm operates in screen coordinates, i.e., the pixels, hence almost all the computations are made by means of integer arithmetic and do not require any math coprocessor.