Coordinate Rotation Digital Computer Architecture Research Articles

A robust low-power fsm cordic lms filter design for exponential noise removal in pacemaker

ABSTRACT Heart disease is identified to be the major reason for death worldwide as recorded by World Health Organization. The use of cardiac pacemakers was estimated to be around 1.14 million in the year 2016 and is expected to increase to 1.43 million by the year 2023. Based on the frequency of usage, the lifetime of a pacemaker can last between 6 to 10 years. To prolong the lifetime of the pacemaker, a low-power filter design is presented. The pulse that comes out of the pacemaker has exponential noise and myo-potential noise. The least mean square (LMS) filter with Co-ordinate Rotation Digital Computer (CORDIC) filters the exponential noise signal and retrieves the desired pace pulse. The CORDIC architecture used here is realised using FSM computational technique, because FSM offers a simple hardware circuitry. Digital circuits highly rely on clock signal to track the time and execution of functions that are programmed. This irreplaceable signal requires a control module that would make it more efficient and audacious. This is the prime reason for the evolution of clock gating technique. Similarly, the leakage power caused by the power source also requires attention. With the boom of deep submicron technologies, leakage power has started to occupy 30–50% of the total power consumption. Power gating technique helps to resolve this issue significantly. In this proposed method, integrated coarse-grained power and clock gating technique is employed to reduce the power dissipation of the LMS filter. A comparative study of Latch-, AND- and OR-based clock gating with forced transistor stacking and sleep transistor whose width and length are doubled from the rest of the complementary metal oxide semiconductors is also performed. The design is implemented using 250 nm CMOS technology. The implementation of clock gating technique has resulted in a 41.35% average reduction in dynamic clock power dissipation. The power gating technique has resulted in 26.08% reduction in static input power dissipation. The total power savings on integration of clock and power gating techniques are found to be 36.95% from the non-gated CORDIC LMS filter design.

Research and Implementation of a Numerical Control Oscillator with Improved Pipelined CORDIC Algorithm

As the recognized core of electronic systems, frequency synthesizers have been applied in many communication fields. NC oscillator (NCO) is the main component of the frequency synthesizer. It helps to generate high-precision and high-frequency signals, so it has been widely used. NCO implementation methods include table lookup method, polynomial expansion method, coordinate rotation digital computer (CORDIC) algorithm, etc. CORDIC algorithm is one of many commonly used methods in trigonometric function calculation and digital signal processing, and is often used as the core of DDS (direct digital synthesis) to generate signals. Compared with table lookup and polynomial expansion, CORDIC algorithm has higher efficiency in signal generation and hardware utilization. In view of the disadvantages of traditional CORDIC algorithm, which takes up large resources and has relatively slow calculation speed, in order to improve the output efficiency, this paper uses an efficient 12-stage pipelined CORDIC architecture and a very small lookup table (LUT) to implement a sine wave generator. The system is coded and simulated in Quartus and ModelSim. The results show that the proposed structure can increase the operating speed of the system from 217.77 MHz to 291.04 MHz, and improve the output efficiency of the system.

VLSI Implementation of a Cost-Efficient Loeffler DCT Algorithm with Recursive CORDIC for DCT-Based Encoder

This paper presents a low-cost and high-quality, hardware-oriented, two-dimensional discrete cosine transform (2-D DCT) signal analyzer for image and video encoders. In order to reduce memory requirement and improve image quality, a novel Loeffler DCT based on a coordinate rotation digital computer (CORDIC) technique is proposed. In addition, the proposed algorithm is realized by a recursive CORDIC architecture instead of an unfolded CORDIC architecture with approximated scale factors. In the proposed design, a fully pipelined architecture is developed to efficiently increase operating frequency and throughput, and scale factors are implemented by using four hardware-sharing machines for complexity reduction. Thus, the computational complexity can be decreased significantly with only 0.01 dB loss deviated from the optimal image quality of the Loeffler DCT. Experimental results show that the proposed 2-D DCT spectral analyzer not only achieved a superior average peak signal–noise ratio (PSNR) compared to the previous CORDIC-DCT algorithms but also designed cost-efficient architecture for very large scale integration (VLSI) implementation. The proposed design was realized using a UMC 0.18-μm CMOS process with a synthesized gate count of 8.04 k and core area of 75,100 μm2. Its operating frequency was 100 MHz and power consumption was 4.17 mW. Moreover, this work had at least a 64.1% gate count reduction and saved at least 22.5% in power consumption compared to previous designs.

Implementation of FPGA design of FFT architecture based on CORDIC algorithm

ABSTRACT The coordinate rotation digital computer (CORDIC) is a class of shift-add algorithm for the rotation of vectors on a plane. The major problem in this CORDIC algorithm is the linear rate of convergence with the speed of the iteration. The main aim of the improved CORDIC algorithm is to utilise an integrated adder subtractor in place of binary adder subtractor to decrease the count of iterations and hardware reduction technique. The improved CORDIC splits the rotation angle into several series of micro-rotation angles to calculate the rotation and the new set of angle provides a fast convergence. The canonical signed-digit (CSD) approach together with Hcub algorithm employs for the number of adder subtractor reduction and shifters in CORDIC architecture design. The performances of the proposed CORDIC design have been verified by employing it in FFT implementation. The simulation result indicates the higher frequency of 77.20%, 82.78%, 78.30% and 76.57% when compared with conventional methods. The evaluation of FFT is also done by comparing with the conventional methods. The power consumption, number of iterations and the hardware complexity reduced by using the improved CORDIC and the working of this proposed algorithm is evaluated through the FPGA implementation.

An Efficient Fixed-Point Multiplier Based on CORDIC Algorithm

Fixed-point multiplication is an important operation that is frequently used in many digital signal processing (DSP) applications. The operation is computationally intense and very often the performance of multiplier determines the overall performance of DSP system. Evidently, a wide range of approaches have been proposed for efficient implementation of fixed-point multipliers on different hardware platforms. In this paper, we use Coordinate Rotation DIgital Computer (CORDIC) algorithm to perform fixed-point multiplication operation. The motivation for our approach is based on the fact that CORDIC is a hardware-efficient algorithm, wherein accuracy can be traded-off for performance. Our implementation targets field programmable gate arrays (FPGAs) and focuses on exploiting the underlying general and specialized fabric to the fullest. Performance comparisons against various traditional and recent approaches show that a substantial improvement is achievable by using CORDIC-based multipliers. We have also implemented a recently proposed convolution architecture using CORDIC-based multipliers. The results show that a proper choice of CORDIC architecture can result in an improvement of performance parameters like resource utilization, throughput and dynamic power. This, however, is achieved in lieu of a small cost in accuracy. Our analysis of an 8-stage CORDIC multiplier reports a mean absolute percentage error (MAPE) of 6.032 — a factor that reduces exponentially with increasing number of stages.

Efficient CORDIC Iteration Design of LiDAR Sensors' Point-Cloud Map Reconstruction Technology.

In this paper, we propose an efficient COordinate Rotation DIgital Computer (CORDIC) iteration circuit design for Light Detection and Ranging (LiDAR) sensors. A novel CORDIC architecture that achieves the goal of pre-selecting angles and reduces the number of iterations is presented for LiDAR sensors. The value of the trigonometric functions can be found in seven rotations regardless of the number of input N digits. The number of iterations are reduced by more than half. The experimental results show the similarity value to be all 1 and prove that the LiDAR decoded packet results are exactly the same as the ground truth. The total chip area is 1.93 mm × 1.93 mm and the core area is 1.32 mm × 1.32 mm, separately. The number of logic gates is 129,688. The designed chip only takes 0.012 ms and 0.912 ms to decode a packet and a 3D frame of LiDAR sensors, respectively. The throughput of the chip is 8.2105 bits/sec. The average power consumption is 237.34 mW at a maximum operating frequency of 100 MHz. This design can not only reduce the number of iterations and the computing time but also reduce the chip area. This paper provides an efficient CORDIC iteration design and solution for LiDAR sensors to reconstruct the point-cloud map for autonomous vehicles.

RICO: A low power repetitive iteration CORDIC for DSP applications in portable devices

Abstract COordinate Rotation DIgital Computer (CORDIC) is a unit that is widely used in the applications such as scientific calculators, signal/image processing, communication systems, robotics, 3-D graphics etc. exhibits huge computations and requires large power. This paper presents an approximate low power Repetitive Iteration CORDIC (RICO) architecture that calculates sine/cosine values very efficiently. In the proposed RICO, number of iterations are fixed and a specific iteration is repeated to reduce the implementation complexity. An additional comparator based logic that evaluates direction of micro-rotation within RICO reduces the data dependency between each iterations. The efficiency of the proposed RICO is evaluated in Discrete Cosine Transform (DCT) by implementing DCT using only three RICO units. Post-synthesis simulation results show that the proposed RICO achieves area and power savings of 37.19% and 94.05% respectively over the Conventional CORDIC at the cost of 29.39% increase in latency.

Very large‐scale integration architecture for video stabilisation and implementation on a field programmable gate array‐based autonomous vehicle

Autonomous vehicles engaged in terrain exploration are typically equipped with a camera. The camera is subjected to vibration as the vehicle moves so that the videos captured require stabilisation to facilitate accurate interpretation by remote operators. Dedicated architectures for video stabilisation that offer high performance while consuming low area and power are desirable for this application. This study presents a pipelined very large-scale integration architecture. It is based on exploiting the separability property of the two-dimensional (2-D) Sobel matrix and the 2-D Gaussian filtering matrix to obtain an efficient corner point detection architecture. It also employs the coordinate rotation digital computer architecture for global motion vector calculation. The proposed architecture has been coded in Verilog and synthesised for a field programmable gate array (FPGA), which offers massive parallelism at fairly low power. The proposed architecture is shown to be highly area efficient. An FPGA-based autonomous vehicle has been fabricated, and experiments with a camera mounted on the vehicle are presented and analysed.

IJIREEICE - Electrical, Electronics, Instrumentation and Control

4 Abstract: - In digital communication, there is a need of different modulation technique (such as ASK FSK PSK) to convey a message signal. A Universal modulation is the solution to obtain different modulation techniques. For the implementation of Universal Modulator on FPGA, different architecture have been proposed. One of the technique way to realize the Universal Modulator is Look up table (LUT). Here the CORDIC architecture is used for efficient realization of Universal Modulator. The coordinate rotation digital computer (CORDIC) algorithm is widely used in various technological fields such as digital signal processing (DSP), biomedical signal processing, robotics, communication systems, image processing etc. For simple shift and add operation, CORDIC based systems are increased drastically. For the realization of Amplitude modulation, Frequency modulation and Phase modulation, this Universal Modulation is used. The generation of SIN and COS output values will are tested for a given input angle (θ) value. The universal modulator will be designed around the CORDIC algorithms which can generate all most all digital modulation schemes such as ASK, PSK, FSK.

IS-CORDIC: a fixed-point inverse recoded single iteration CORDIC architecture

This paper presents a novel modified Coordinate Rotation Digital Computer (CORDIC) architecture that computes values of sine and cosine in a single cycle. The proposed method utilises angle-recoding technique to design a modified CORDIC algorithm. Multiple iterations are merged in the modified algorithm using memory storage for initial iterations and employing inverse recoding to generate constant multiplication factors for the remaining iterations. Scale factor of the algorithm remains constant, as these factors are independent of intermediate directions of rotation. In addition, the architecture is mapped onto a single CORDIC computation element that requires only a single cycle to compute the result. These multiplications are implemented using dedicated hardware multipliers in Field Programmable Gate Arrays and customised fixed-point multiplication techniques for Application Specific Integrated Circuits. Implementation results show that the proposed IS-CORDIC architecture is 7.9 times more efficient than basic CORDIC and has reduced area-delay product than current state of the art implementations.

CORDIC algorithm based on FPGA

It is an important problem that we implement floating point trigonometric functions of high precision with suitable hardware cost for high performance in digit image processing. The coordinate rotational digital computer (CORDIC) arithmetic to is used to solve the above problem in this paper. In order to increase the speed of operation, it chooses the pipeline architecture. The results are disposed by IEEE-754 standard. The CORDIC architecture is modeled by using the verilog HDL and verified with MATLAB program and ModelSim 6.2SE tool. A 32 bits radix-2 CORDIC architecture was implemented on the available FPGA platform. The entire CORDIC architecture operated at 126.34 MHz of clock rate with a power consumption of 318.56 mW. Its theoretical background, procedures, simulation results and conclusions are presented in this paper.

FPGA implementation of area time efficient CORDIC processor dedicated to compute exponentials in neural networks

This paper presents high-performance exponential computation based on the Coordinate Rotation Digital Computer (CORDIC) algorithm with emphasis on minimum hardware requirements. The redesigned unified CORDIC algorithm provides high throughput and is beneficial for the VLSI implementation of the activation functions in neural networks and realisation of exponent calculations in Gaussian Potential Functions (GPFs). Ease of design and scale-free operation of the proposed technique extend the range of convergence compared with the original CORDIC algorithm. Approximately, 57.1% hardware savings are accomplished in comparison with Flat CORDIC architectures for 32-bit word-length. The word-length of the processor is extendible and the experimental results confirm its efficacy.

50 Years of CORDIC: Algorithms, Architectures, and Applications

Year 2009 marks the completion of 50 years of the invention of CORDIC (coordinate rotation digital computer) by Jack E. Volder. The beauty of CORDIC lies in the fact that by simple shift-add operations, it can perform several computing tasks such as the calculation of trigonometric, hyperbolic and logarithmic functions, real and complex multiplications, division, square-root, solution of linear systems, eigenvalue estimation, singular value decomposition, QR factorization and many others. As a consequence, CORDIC has been utilized for applications in diverse areas such as signal and image processing, communication systems, robotics and 3-D graphics apart from general scientific and technical computation. In this article, we present a brief overview of the key developments in the CORDIC algorithms and architectures along with their potential and upcoming applications.

Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture

In this paper, we proposed a novel Coordinate Rotation Digital Computer (CORDIC) rotator algorithm that converges to the final target angle by adaptively executing appropriate iteration steps while keeping the scale factor virtually constant and completely predictable. The new feature of our scheme is that, depending on the input angle, the scale factor can assume only two values, viz., 1 and 1//spl radic/2, and it is independent of the number of executed iterations, nature of iterations, and word length. In this algorithm, compared to the conventional CORDIC, a reduction of 50% iteration is achieved on an average without compromising the accuracy. The adaptive selection of the appropriate iteration step is predicted from the binary representation of the target angle, and no further arithmetic computation in the angle approximation datapath is required. The convergence range of the proposed CORDIC rotator is spanned over the entire coordinate space. The new CORDIC rotator requires 22% less adders and 53% less registers compared to that of the conventional CORDIC. The synthesized cell area of the proposed CORDIC rotator core is 0.7 mm/sup 2/ and its power dissipation is 7 mW in IHP in-house 0.25-/spl mu/m BiCMOS technology.

Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications

The coordinate rotational digital computer (CORDIC) algorithm is a well-known iterative arithmetic for performing vector rotations in many digital signal processing (DSP) applications. However, the large number of iteration is a major disadvantage of this algorithm for its speed performance. Many researchers have proposed schemes to reduce the number of iterations. Nevertheless, in performing the existing CORDIC algorithms, the norm of the vector is usually enlarged so that extra scaling operations are required to deliver the normalized output. In this paper, we merge the two operation phases (microrotations and scaling phases) and propose a new vector rotational scheme called mixed-scaling-rotation coordinate rotational digital computer (MSR-CORDIC) algorithm. It can eliminate the overhead of the scaling operations that are inevitable in existing CORDIC algorithms; hence, it can significantly reduce the total iteration number so as to improve the speed performance. The proposed MSR-CORDIC can be applied to DSP applications, in which the rotational angles are known in advance [e.g., twiddle factor in fast Fourier transform (FFT) processor designs]. Moreover, most CORDIC algorithms generally suffer from the roundoff noise in the fixed-wordlength implementations. We also propose two schemes to control and reduce the impairment. Our simulation results show that the MSR-CORDIC algorithm can enhance the signal-to-quantization-noise ratio (SQNR) performance by controlling the internal dynamic range. We also investigate the first- and second-order statistical properties, including the mean and variance of the SQNR. Simulation results show that the MSR-CORDIC can enhance SQNR performance of both first- and second-order statistical properties. At the VLSI architecture level, we proposed a generalized MSR-CORDIC engine for the tradeoff between hardware complexity and quantization error performance. It can further reduce the hardware complexity when compared with the newly proposed extend elementary angle set CORDIC algorithm . The MSR-CORDIC scheme has been applied to a variable-length FFT processor design , and results in significant hardware reduction in implementing the twiddle factor operations.

A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes

The coordinate rotational digital computer (CORDIC) algorithm is a well-known iterative method for the computation of vector rotation. For applications that require forward rotation (or vector rotation) only, the angle recoding (AR) technique provides a relaxed approach to speed up the operation of the CORDIC algorithm. In this paper, we further apply the concept of AR technique to extend the elementary angle set in the microrotation phase. This technique is called the extended elementary-angle set (EEAS) scheme. The proposed EEAS scheme provides a more flexible way of decomposing the target rotation angle in CORDIC operation, and its quantization error performance is better than the AR technique. Meanwhile, to solve the optimization problem encountered in the EEAS scheme, we also proposed a novel search algorithm, called the trellis-based searching (TBS) algorithm. Compared with the greedy algorithm used in the conventional AR technique, the proposed TBS algorithm yields apparent signal-to-quantization-noise ratio (SQNR) improvement. Moreover, in the scaling phase of the EEAS-based CORDIC algorithm, we suggest a novel scaling operation, called Extended Type-II (ET-II) scaling operation. The ET-II scaling operation applies the same design concepts as the EEAS scheme. It results in much smaller quantization error than conventional Type-I scaling operation in the numerical approximation of scaling factor. By combining the aforementioned new schemes, the proposed EEAS-based CORDIC algorithm can improve the overall SQNR performance by up to 25 dB compared with previous works. Also, given the same target SQNR performance, we require only about 66% iteration number in the iterative CORDIC structure, or use 66% hardware complexity in the parallel CORDIC structure compared with conventional AR technique. Hence, high-performance/low-latency CORDIC very large-scale integration architectures can be achieved without degrading the SQNR performance.

P-CORDIC: A Precomputation Based Rotation CORDIC Algorithm

This paper presents a CORDIC (coordinate rotation digital computer) algorithm and architecture for the rotation mode in which the directions of all micro-rotations are precomputed while maintaining a constant scale factor. Thus, an examination of the sign of the angle after each iteration is no longer required. The algorithm is capable to perform the CORDIC computation for an operand word-length of 54 bits. Additionally, there is a higher degree of freedom in choosing the pipeline cutsets due to the novel feature of independence of the iterations and in the CORDIC rotation.

Efficient implementations of pipelined CORDIC based IIR digital filters using fast orthonormal μ-rotations

In this correspondence, an efficient implementation of pipelined coordinate rotation digital computer (CORDIC)-based IIR digital filters based on fast orthonormal /spl mu/-rotations is proposed. Using this method, the Givens rotations are approximated by angles corresponding to orthonormal /spl mu/ rotations, which are based on the idea of CORDIC and can perform rotation with minimal number of shift-add operations. We present various methods of construction for such orthonormal /spl mu/ rotations. A significant reduction (over 70%) of the number of required shift-add operations is achieved. All types of fast rotations can be implemented as a cascade of only four basic types of shift-add stages. These stages can be executed on a modified floating-point CORDIC architecture, making the pipelined filter highly suitable for VLSI implementations.

Design of a unified arithmetic processor based on redundant constant-factor CORDIC with merged scaling operation

An arithmetic processor is designed based on redundant constant-factor implementation of the coordinate rotation digital computer (CORDIC) algorithm with three different modes: circular, hyperbolic and linear. Both CORDIC types (angle calculation and vector rotation) are considered in this unified processor that is capable of computing a wide variety of arithmetic and elementary functions including: multiplication, division, some common trigonometric functions, natural logarithms, square roots, vector norm and phase. Furthermore, by merging the scaling operation with the regular CORDIC iterations, the processor based on folded (iterative) CORDIC architecture reduces by about 1/4 the total number of iterations in one complete CORDIC operation.

A CORDIC processor for FFT computation and its implementation using gallium arsenide technology

In this paper, the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.6 /spl mu/m gallium arsenide (GaAs) technology are presented. This processor computes a 1024-point FFT of 16 bit complex data in less than 8 /spl mu/s, working at a frequency beyond 700 MHz, with a power consumption of 12.5 W. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) algorithm, which avoids the use of conventional multiplication-and-accumulation (MAC) units, but evaluates the trigonometric functions using only add and shift operations, Improvements to the basic CORDIC architecture are introduced in order to reduce the area and power of the processor. This together with the use of pipelining and carry save adders produces a very regular and fast processor, The CORDIC units were fabricated and tested in order to anticipate the final performance of the processor. This work also demonstrates the maturity of GaAs technology for implementing ultrahigh-performance signal processors.