Conventional Wet Cleaning Research Articles

Electron Field Emission from Multiply-Stacked Si Quantum Dots Structures with Graphene Top-Electrode

Introduction Electron field emission from Si-based nanocrystals has been stimulated considerable interest because electron emission devices are expected to be used for various applications [1, 2]. In our previous work, we have demonstrated electron field emission from multiple-stacked Si-quantum-dots (Si-QDs) structures with ultrathin Au top electrodes under biases of 6V and over, in which electric field concentrates on the upper dot layers [3]. To reduce electron scattering in top electrodes, we fabricated the multiple stacked Si-QDs structures with single layer graphene top electrodes and evaluated their electron emission properties. Experimental After conventional wet chemical cleaning steps, n-type Si(100) wafers were oxidized at 1000 °C in dry O2 to form ~3.0 nm thick SiO2. After that, Si-QDs with an areal dot density as high as ~4.7×1011 cm−2 and an average dot size of ~4.5 nm were formed on SiO2 by low pressure chemical vapor deposition (LPCVD) using pure SiH4, followed by thermal oxidation to cover the surface of the dots with ~1.5 nm-thick SiO2. By repeating such a process sequence, 11-fold stacked Si-QDs layers were formed. Single layer graphene was formed on a Cu foil by solid-source LPCVD using Poly-styrene. After spin coating poly methyl methacrylate (PMMA) on the graphene, the Cu film and residual Fe were removed by dipping in the Fe(NO3)3·9H2O solution and nitric acid solution (HNO3: H2O = 1:5), respectively. After that, PMMA/graphene was transferred on the multiple stacked Si-QDs layers. Subsequently, the PMMA was removed by dipping in acetone and IPA. We also fabricated ~10 nm-thick Au films as top electrodes on the 11-fold stacked Si-QDs by electron beam (EB) evaporation as a reference. Finally, Al films were formed as bottom electrodes by thermal evaporation. Results and Discussion When forward bias (|V s|) exceeds ~6.0 V, electron emission current (I e) from the multiple stacked Si-QDs with the graphene top electrode appears. In addition, with an increase in the |V s|, the I e was exponentially increased as in the case of the Au top-electrodes. It is interesting to note that the I e for the sample with the graphene top electrode was larger than that for the sample with the Au top electrode although the sample current (I s) was suppressed by using graphene as the top electrode (Fig.1). This result implies reduction of electron tunneling current, which can be interpreted in terms of density-of-state difference between the graphene and Au. In addition, an effective contact area of the graphene might be smaller than that of a designed value. We also summarized emission efficiencies as a function of |V s|, as shown Fig. 2. Obviously, in both cases, with an increase in the |V s|, emission efficiencies were increased exponentially. Notice that, by using the graphene top electrode, the emission efficiency was increased by a factor of ~100 compared with that of the sample with the Au top electrode under the same |V s|. This result indicates that, by using a single layer graphene as a top electrode, electron emission efficiency can be enhanced by the reduction of electron scattering within the top electrode. Conclusion The graphene top electrode plays a role in high efficiency electron emission from the stacked structures of Si-QDs due to the reduction of electron scattering within the top electrode. Acknowledgment This work was supported in part by Grant-in-Aid for Scientific Research (A) No. 19H00762 of MEXT Japan. The formation of the graphene top electrode was supported by associate professor Karita Gorap at Nagoya Institute of Technology.

Removal of antireflection sol-gel SiO2 coating based on Ar ion beam etching

• We proposed a stripping method of antireflection coating based on ion beam etching. • This dry approach is greener than wet method for no waste water produced, like tritiated water. • Coating is etched 6 times faster than substrate, so ignorable modification of the optics. • This method is effective and does not degrade optics performance. • This method has been adopted to process the recycling optics of Chinese ICF facility. We proposed a new stripping method of sol-gel SiO 2 coating widely used in inertial confinement fusion facilities based on Ar ion beam etching, during which the coating is removed in the form of gaseous and solid particle. This dry approach is more environment-friendly than the conventional wet cleaning process for saving the trouble of treating tons of polluted water, especially highly toxic tritiated water. In the IBE process, porous coating is sputtered away at a constant etching rate just like other homogeneous materials. IBE parameters are systematically optimized to obtain a selective and gentle etching. The weakly bonded coating is etched 6 times faster than the fused silica substrate, which ensures the selective sputtering of coating over the underlying fine optics. Experiments on different off-line samples as well as the actual recycled optics from high power laser system show that this method is very effective. Moreover, this stripping process does not degrade the optic’s performance. Surface shape and roughness barely change after stripping. The laser damage threshold increases slightly, probably due to the removal of re-deposition layer introduced during polishing process. This method has been successfully adopted to process the optics of ICF facility in China.

Wet Cleaning by Using Amphoteric Electrolyzed Water for Mask Cleaning

Process achievement for manufacturing extreme ultraviolet(EUV) semiconductor device requires profound technical varieties such as extreme extension of the existing concepts or new evolutional ones. In this study, a new technology was proposed to fulfill technical details required for EUV semiconductor device cleaning and manufacturing. The special electrolysis technology of ultrapure water(UPW) was introduced to generate water possessing quite unexpectedly mixed character such as pH of 6.5 to 6.7 and oxidation reduction potential(ORP) of -540 to –560 mV at room temperature. Since ORP of –550 mV lasted for several days, it was postulated that water clustering reaction due to hydrogen bond could hinder or retard recombination of H+ and OH- ions by synchronously isolating them electronically and physically. This amphoteric water was applied to cleaning process of EUV device manufacturing to carry out the experiment requiring eventually no chemical use for wet cleaning because of 10 nm feature size. Some results were so excellent that it was convinced that this water clean was evolutional to meet EUV requirements. This water did eliminate adsorbed leftovers of previous chemical treatments and minimized surface modifications because of non-chemical character so that it did not provide any chance of haze formation. Since particle removal efficiency(PRE) was very high, it was proposed that there might be other cleaning mechanism than double layer repulsion(DLR) of colloids. Conclusively, it is time to review the conventional wet cleaning technology and to adopt new concept of the amphoteric water to realize the cleaning technology of EUV device era.

Effect of Pre-heat and Inert Gas Species on Cryogenic Aerosol Cleaning Performance in Semiconductor Manufacturing

Cryogenic aerosol cleaning is a dry cleaning method used in the back end of line (BEOL) semiconductor manufacturing to remove defects from planar hydrophobic surfaces such as SiCOH and SiCxNyHz. Cryogenic aerosol cleaning is preferred over conventional wet cleaning methods as it is a non-contact cleaning method, which uses inert gases to generate sub-micrometer-sized solid aerosol particles that physically remove nanometer-sized contaminants on wafer surfaces. Particle removal mechanism involves detachment of the particles upon impact with aerosol, diffusion, and finally entrainment away from the wafer. In BEOL metal line patterning, particles on the dielectric isolation surfaces translate through the subsequent lithography and copper fill steps in to single or multiple metal line open defects that are yield killers. In this study, we show that the particle removal performance of the standard aerosol cleaning can be enhanced by pre-heating the wafer and use of a higher molecular weight inert gas, namely Ar, for aerosol generation. Both the addition of a Pre-heat step and the use of Ar as the aerosol source showed 47–52% reduction in single and multiple line opens detected through wafer electrical tests during high volume semiconductor manufacturing process.

(Invited) A Novel Approach to Clean Surface for High Mobility Channel Materials with In Situ Atomic Hydrogen Clean

A number of non-silicon channel materials have been considered for advanced CMOS devices such as SiGe, Ge and GeSn (PMOS) as well as various III-V materials combinations including InGaAs and GaAs (NMOS). Surfaces cleaning process is critical to make a better interface contact in devices. This study demonstrates a method of surface cleaning on Ge/III-V channel using thermal atomic hydrogen source. This technique has several advantages over conventional wet, thermal, or plasma cleaning such as lower temperatures, no surface damage, less impurities, selective removal, and large area scalability. This will be a good candidate technology for the future non-Si CMOS technology beyond 10 nm node with scalability to 450 mm wafer size.

New Chemical Vapor Delivery Systems for Surface Cleaning

Conventional aqueous wet cleaning methods in semiconductor manufacturing are facing tremendous challenges, with decreasing line widths and high aspects ratio features on the order of a few nanometers. Water and other liquids have surface tensions that frequently prevent complete penetration into nanometer-sized trenches and vias now being fabricated on semiconductor wafers and other substrates. This problem is accentuated by the fact that particle sizes leading to Killer defects are now on the order of 10 nm or less. Nanometer-sized particles can adhere to a surface with a relatively strong force of over a million times its weight. An effective cleaning technique for submicron particle removal will require complete penetration of the device features to surround and dislodge particles, but at the same time not damage the features or etch the surface.

High Aspect Ratio Contact Clean Study in 58nm Flash Device

In the conventional wet cleaning process of contact holes landing on the Si substrate and WSi metal gate, the ILD BPTEOS bowing and CD enlargement were often found by using dilute HF solution. With the device design rule decreasing, the CD size control and cleaning efficiency enhancement are highly demanded. In this work, the high aspect-ratio contact (AR~10) cleaning in single wafer (SW) tool was demonstrated in 58nm flash device. With the facilitation of nano-spray function to enhance particle removal efficiency (PRE), AM1 cleaning in SW tool can achieve the low contact resistance and tighten Rc distribution with less ILD film damage and lower CD enlargement. The parameter dependency of SW tool, including chemical injection method, nozzle swinging effect and nano-spray function, on contact resistance was also investigated. Compared to AM1 cleaning in bench tool, AM1 process in SW tool performs the larger process window for less ILD film damage at higher temperature and concentration.

Effects of the wet air on the properties of the lanthanum oxide and lanthanum aluminate thin films

Lanthanum oxide and lanthanum aluminate thin films were deposited on Si substrates. The as-grown films were stored in wet ambient and dry ambient for days and annealed after storage and also the structural and the electrical properties of the films were investigated. As the storage time increased, the La 2O 3 films stored in wet ambient showed rapid reaction with moisture and the properties degraded. In case of the LAO films, although the thickness of the film also increased during hydration, the properties of the film did not so much changed due to the role of the incorporated aluminum. The LAO films showed better hydration resistance characteristics and so more suitable for conventional wet cleaning process in semiconductor fabrication.

Effects of Wafer Cleaning on the Interconnect Structure and Its Electrical Properties during the Al Dual Damascene Process for the Fabrication of Sub-100 nm Memory Devices

An Al dual damascene process for the metallization of sub-100 nm dynamic random access memory devices was performed, and the effects of wafer cleaning method on the damascene structures and their electrical properties were investigated. Interconnect structures obtained with the Al dual damascene process using the conventional NH4OH-based wet cleaning (Type I) and the wet cleaning followed by CF4/Ar-plasma dry cleaning (Type II) showed that the metal lines having the aspect ratio of 3 were patterned without gap-filling of inter metal dielectrics. All the sheet resistances of metal lines using the two different wafer cleaning methods during the Al dual damascene process were within specification. The via resistance distributions, however, depended on the cleaning method, and it was found that the cleaning Type II produced a 100% yield and very narrow distribution of the contact resistances of the 0.24 μm-diameter via due to the efficient removal of stable AlxOy species for cleaning Type II.

Multi-jet atmospheric glow plasma cleaning of ablation debris from micro-via drilling process

We devised a multi-jet atmospheric glow plasma system and successfully verified a possibility to ignite and maintain an atmospheric pressure discharge using helium, argon or a mixture of helium and oxygen gas. In this study, as an alternative method to the conventional wet cleaning process, the multi-jet atmospheric glow plasma system was applied to clean the ablation debris inside the blind via holes from micro-via drilling process of printed circuit boards (PCBs) prior to electroplating process. Scanning electron microscope images, after the multi-jet atmospheric glow plasma treatment of the PCBs, showed effective removal of residual organic impurities and massive fibrous debris when compared with low-pressure vacuum plasma treatment. Consequently, we demonstrated that multi-jet atmospheric glow plasma system could not only effectively remove organic impurities and massive fibrous debris generated during micro-via drilling process, but also enhance the electroplating process and the wire bondability.

An investigation on the plasma treatment of integrated circuit bond pads

Integrated circuit (IC) bond pads play an important role in the wire bond reliability of the microelectronic devices. Being the device’s only electrical connection to the package and electronic systems, it is mandatory that the bond pads are free of contaminants and possess excellent bonding characteristics. Contaminants such as oxides and organic residues impair the bondability to a considerable extent and are very resistant to conventional wet cleaning methods. In this paper, we report the effects of an Ar/H 2 plasma treatment on the surface chemistry and morphology of IC bond pads. Surface and sub-surface chemical analyses have been conducted using Auger electron spectroscopy (AES), X-ray photoelectron spectroscopy (XPS) and scanning electron microscopy (SEM). Results reveal that the oxygen level of the bond pad surface has decreased significantly after the plasma treatment. Although the treatment has successfully removed the surface crystallites on the bond pads on prolong etching; however, the aggressive process has also damaged the passivation layers that surround the pad areas.

Characterization of Oxide Etching and Wafer Cleaning using Vapor-Phase Anhydrous HF and Ozone

ABSTRACTA cleaning process using anhydrous HF (AHF)/methanol and ozone is carried out in a STEAG-AST Vapor Phase Cleaning module (VPC). This module is integrated in a state-of-the-art cluster tool also consisting of a STEAG-AST Rapid Thermal Oxidation module (RTO). The dependence of AHF vapor phase etch rate of thermally grown silicon dioxide on different process parameters, such as etch time, AHF-flow, and temperature is evaluated. The optimized etch process is found to be at a temperature of 40°C and at a pressure of 50 mbar for this VPC module. Using the above etch parameters various combinations of vapor phase surface preparation chemistries combining AHF etching and ozone/UV cleaning are evaluated.To demonstrate the feasibility of this cluster tool for advanced gate dielectric formation, 4.0 nm thin oxide is grown directly after the cleaning in the RTO module without breaking the vacuum. Time dependent dielectric breakdown results for oxides pre-oxidation-cleaned in AHF, and in AHF followed by ozone are compared to a reference sample without any dry pre-oxidation cleaning. It can be shown, that the cleaning in AHF with a subsequent ozone step at 200°C under UV light leads to improved breakdown characteristics compared to AHF/methanol cleanings without such subsequent ozone/UV step or conventional wet cleaning using HF-Dip.

Cleaning Process Optimization in a Gate Oxide Cluster Tool Using an in-Line XPS Module

ABSTRACTA cleaning process using anhydrous HF (AHF)/methanol and ozone was carried out in a STEAG AST Vapor Phase Cleaning module (VPC). This module was integrated in a state-of-theart cluster tool also consisting of a STEAG AST Rapid Thermal Oxidation module (RTO). To investigate the properties of silicon after cleaning a novel in-line XPS module was integrated into the gate oxide cluster. Measurements of fluorine, carbon, and oxygen contamination in the range from 0.01 to 1 monolayers on cleaned wafer surfaces and on regrown oxides (< 0.5 nm) have been performed and used for rapid optimization of the cleaning procedure. The in-line integration enabled measurements without exposing the wafers to atmosphere thus avoiding oxidation or contamination of the wafer surfaces. To demonstrate the feasibility of this cluster tool for advanced gate dielectric formation, 4.0 nm thin oxide was grown directly after the cleaning in the RTO module without breaking the vacuum. Time dependent dielectric breakdown results for oxides pre-oxidation-cleaned in AHF, and in AHF followed by ozone were compared to a reference sample without any dry pre-oxidation cleaning. It could be shown, that the cleaning in AHF with a subsequent ozone step at 200°C under UV light lead to improved breakdown characteristics compared to AHF/methanol cleanings without such subsequent ozone/UV step or conventional wet cleaning using HF-Dip.

Surface Treatment with UV-Excited Radicals for Highly-Reliable Gate Dielectrics

ABSTRACTThe UV-excited chlorine radical treatment effectively removed trace metal contaminants from Si ans SiO2 surfaces. We have found that this is predomonantly attributed to reactions between metal and chlorine, and metal oxides and silicon chloride, respectively. The former process was subjected to identify a breakdown spot on a thin gate dielectric film. After dielectric breakdown, a silicon crystallized filament as small as a few nanometers in diameter was formed and was selectively etched with chlorine radicals revealing a successively-etched region of the Si substrate. Nonuniformi t i es of native oxides on silicon were also detected using the same method. Gettering and etching with a poly Si layer showed a possibility to make a gate dielectric film damage free and contamination free. Densi fication of native oxides formed after conventional wet cleaning of silicon was made with UV-excited oxygen radicals. Electrical characteristics of gate dielectrics treated with UV-excited chlorine and oxygen radicals showed high reliability.

Atomically flat, ultrathin-SiO 2/Si(001)interface formation by UHV heating

Conventional wet cleaning and ultrahigh vacuum (UHV) heated cleaning prior to thermal oxidation were compared with respect to their effects on extremely thinSiO 2/Si(001)interface roughness. Atomically flatSiO 2/Si(001)interfaces were realized by preparing theSi(001)−2 × 1surface in UHV followed by thermal oxidation. This planarization is significant in the range of oxide thickness ( T ox < ∼ 9nm). As for the ‘wet-cleaned’ surfaces, a wide variety of the interface roughness was observed at T ox < ∼ 4nmwhich corresponds to the ‘initial oxide thickness ( T io)’ which appeared in the oxide growth kinetics. The electron scattering caused by the interface roughness might degrade the inversion electron mobility for the ‘wet-cleaned’ sample at T ox < T io.

In Situ Vapor Phase Pregate Oxide Cleaning and Its Effects on Metal‐Oxide‐Semiconductor Device Characteristics

Vapor phase cleaning of Si(100) surface in a cluster tool was studied. Electrical properties of the interface and the integrity of 55 Å films formed by in situ pregate oxide cleaning and rapid thermal oxidation (RTO) were characterized. Pregate oxide cleaning included anhydrous hydrofluoride (AHF) vapor for etching of native or sacrificial oxide, hydrocarbon removal, and trace metallic contamination elimination. Compared with a conventional wet cleaning procedure, in situ cleaning results in an equivalent interface and film with higher charge‐to‐breakdown . A two‐step cleaning procedure consisting of AHF etching and metal removal results in oxides with the highest .

Pre-Gate Oxidation Cleaning of Silicon Wafer by Electric Arc Plasma Jet Treatment

ABSTRACTThe effect of arc plasma jet treatment (APJT) of silicon surface used for pre-gate oxidation cleaning on the electrophysical parameters of MOS structures (Si/SiO2/Si*/Al) has been studied- We show that APJT etching cleaning considerably improves the constant current charge to breakdown of MOS structures in comparison with conventional wet chemical cleaning. We have analyzed the effect of plasma cleaning conditions on the quality of gate oxide and SiO2/Si interface.

Atomic-Order Planarization of Ultrathin SiO2/Si(001) Interfaces

Conventional wet cleaning and ultrahigh vacuum (UHV) heated cleaning prior to thermal oxidation were compared with respect to their effects on extremely thin SiO2/Si(001) interface roughness. Atomically flat SiO2/Si(001) interfaces were realized by preparing the Si(001) reconstructed surface in UHV followed by thermal oxidation. In contrast to conventional wet cleaning, this planarization is significant in the range of oxide thickness (T ox)<9 nm which is an important thickness for future gate oxides. As for the conventional wet-cleaned surfaces, maximum roughness of the interface was observed at T ox≃4 nm which corresponds to the “initial oxide thickness” which appeared in the oxide growth kinetics.

超高真空加熱による原子的に平滑なシリコン‐酸化膜界面形成

Conventional wet cleaning and ultrahigh-vacuum (UHV) -annealed cleaning prior to thermal oxidation were compared with their effects on SiO2/Si (001) interface roughness. In comparison with the wet cleaned surfaces, atomically flat interfaces were obtained and the roughness was reduced to less than 0.1 nm in RMS for the UHV-annealed surfaces by annealing the surface at 1100°C in UHV (<5×10-10 Torr). This planarizatin was remarkable in the ultrathin oxide region (<4 nm).

Native Oxide Growth and Organic Impurity Removal on Si Surface with Ozone‐Injected Ultrapure Water

To manufacture ULSI devices with high performance and reliability in large volume, further integration and miniaturization are being promoted. The key issue in realizing what we call “Noise‐Free Manufacturing” is to keep the wafer surface ultraclean all the time. To realize the ultraclean wafer, organic impurities adsorbed on the wafer surface must be removed first before other wafer cleaning procedures. This is because native oxide and metallic impurities on the wafer cannot be removed completely in the presence of residual organic impurities on the surface. The conventional wet cleaning process is designed to have the cleaning performed at the first stage to remove organic impurities on the wafer. Because the solution in this cleaning must be heated to about 130°C, the chemical composition of the solution cannot be maintained at a constant level. This means that the cleaning is not perfectly controlled. The cleaning has another serious problem: the cleaning step produces a large volume of chemical waste that must be treated properly. We have developed a cleaning technology using ozone‐injected ultrapure water. Ozone concentration in the water is 1–2 ppm. This process is capable of effectively removing organic contaminants from the wafer surface in a short time at room temperature. Processing waste from this process is simple. Chemical composition of the ozone‐injected ultrapure water can be controlled easily.