Conventional UMOSFET Research Articles

Single-Event Burnout Hardening 4H-SiC UMOSFET Structure

In this paper, we propose 4H-SiC UMOSFET structure with improved single-event burnout (SEB) hardening characteristics, and compare it with the conventional UMOSFET structure by conducting numerical technology computer-aided design (TCAD) simulations. The SEB safe operating areas are extracted when heavy ions with different linear energy transfer (LET) collide with the device. Because integrated heterojunction diode (HJD) in proposed structure features hole collection effect due to the difference of the valence band energy level, the generated hole current can be leaked off efficiently. With a LET value of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.01~{\sim }~0.09$ </tex-math></inline-formula> pC/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> , the proposed MOSFET has 25% higher SEB threshold voltage than conventional MOSFET due to the suppressed parasitic BJT operation. Therefore, proposed structure can provide superior SEB viability for space and atmospheric applications.

A Comparative Study of Single-Event-Burnout for 4H-SiC UMOSFET

SiC UMOSFET is a kind of significant power device in the supply of aerospace. But it is sensitive to space radiation. In this paper, the discrepancy of SEB behavior and research of 4H-SiC UMOSFET with the different values of particle linear energy transfer (LET) are proposed and investigated by the 2D numerical simulations. And the improved MOSFET with multi-Buff was compared with the conventional UMOSFET. At last, simulation results demonstrated that under high-intensity radiation environment (high LET value heavy ion incidence), the proposed UMOSFET could increase the single-event burnout (SEB) hardness, and using the lattice temperature of device as the SEB behavior characterization of the SiC UMOSFET after heavy ion incidence is more reasonable and accurate than only using high steady-state drain current.

Improved 4H-SiC UMOSFET with super-junction shield region* *Project supported by the National Natural Science Foundation of China (Grant Nos. 61774052 and 61904045), the Youth Foundation of the Education Department of Jiangxi Province, China (Grant No. GJJ191154), and the Youth Foundation of Ping Xiang University, China (Grant No. 2018D0230).

This article investigates an improved 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor (MOSFET) (UMOSFET) fitted with a super-junction (SJ) shielded region. The modified structure is composed of two n-type conductive pillars, three p-type conductive pillars, an oxide trench under the gate, and a light n-type current spreading layer (NCSL) under the p-body. The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer, thus improving the specific on-resistance (R on,sp). There are three p-type pillars in the modified structure, with the p-type pillars on both sides playing the same role. The p-type conductive pillars relieve the electric field (E-field) in the corner of the trench bottom. Two-dimensional simulation (silvaco TCAD) indicates that R on,sp of the modified structure, and breakdown voltage (V BR) are improved by 22.2% and 21.1% respectively, while the maximum figure of merit () is improved by 79.0%. Furthermore, the improved structure achieves a light smaller low gate-to-drain charge (Q gd) and when compared with the conventional UMOSFET (conventional-UMOS), it displays great advantages for reducing the switching energy loss. These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance, which also enables the charge carriers to be extracted quickly. In the end, under the condition of the same total charge quantity, the simulation comparison of gate charge and OFF-state characteristics between Gauss-doped structure and uniform-doped structure shows that Gauss-doped structure increases the V BR of the device without degradation of dynamic performance.

Numerical Simulation Analysis of Switching Characteristics in the Source-Trench MOSFET’s

In this paper, we compare the static and switching characteristics of the 4H-SiC conventional UMOSFET (C-UMOSFET), double trench MOSFET (DT-MOSFET) and source trench MOSFET (ST-MOSFET) through TCAD simulation. In particular, the effect of the trenched source region and the gate trench bottom P+ shielding region on the capacitance is analyzed, and the dynamic characteristics of the three structures are compared. The input capacitance is almost identical in all three structures. On the other hand, the reverse transfer capacitance of DT-MOSFET and ST-MOSFET is reduced by 44% and 24%, respectively, compared to C-UMOSFET. Since the reverse transfer capacitance of DT-MOSFET and ST-MOSFET is superior to that of C-UMOSFET, it improves high frequency figure of merit (HF-FOM: RON-SP × QGD). The HF-FOM of DT-MOSFET and ST-MOSFET is 289 mΩ∙nC, 224 mΩ∙nC, respectively, which is improved by 26% and 42% compared to C-UMOSFET. The switching speed of DT-MOSFET and ST-MOSFET are maintained at the same level as the C-UMOSFET. The switching energy loss and power loss of the DT-MOSFET and ST-MOSFET are slightly improved compared to C-UMOSFET.

Low on-resistance 4H-SiC UMOSFET with local floating superjunction

This paper introduces an improved on-resistance 4H-SiC UMOSFET structure. Compared to conventional p-shielding UMOSFETs, the proposed 4H-SiC UMOSFET with a local floating superjunction (LFS) exhibits lower on-resistance while maintaining a breakdown voltage of 1700 V. The structure has a superjunction located beneath the p-shielding. It was optimized for various parameters to reduce the on-resistance while maintaining the breakdown voltage. The on-resistances of a conventional UMOSFET and the optimized LFS-UMOSFET are 13.75 and 8.68 $$ {\text{m}}\Omega \,{\text{cm}}^{2} $$, respectively, when the gate voltage is 10 V. The proposed UMOSFET showed a 36.8% reduction in the specific on-resistance, the figure of merit was improved by 35.1%, and the maximum current density was improved by 29%. Also body diode characteristic and UIS test are confirmed. All the results are demonstrated by Sentaurus TCAD simulation.

High-blocking-voltage UMOSFETs with reformed electric field distribution

A high-performance vertical GaN metal–oxide–semiconductor field-effect transistor (MOSFET) with a U-shaped gate (UMOSFET) and high blocking voltage is proposed. The main concept behind this work is to reform the electric field distribution to achieve high blocking voltage. The proposed structure includes p-regions in the drift region, which we call reformed electric field (REF) regions. Simulations using the two-dimensional SILVACO simulator reveal the optimum doping concentration, and width and height of the REF regions to achieve the maximum depletion region at the breakdown voltage in the drift region. Also, the electric field distribution in the REF-UMOSFET is reformed by producing additional peaks, which decreases the common peaks under the gate trench. We discuss herein the impact of the height, width, and doping concentration of the REF regions on the ON-resistance (RON) and blocking voltage. The blocking voltage, specific ON-resistance, and figure of merit $$ \left( {{\text{FOM}} = \frac{{V_{{{\text{BR}}}}^{2} }}{{R_{{{\text{ON}}}} }}} \right) $$ are 1140 V, 0.587 mΩ cm2 (VGS = 15 V, VDS = 1 V), and 2.214 GW/cm2, respectively. The blocking voltage and FOM are increased by about 72 % and 171 % in comparison with a conventional UMOSFET (C-UMOSFET).

Investigation of SiC trench MOSFET with floating islands

The silicon carbide trench metal-oxide-semiconductor field-effect transistors (SiC UMOSFET) with P + floating island (FLI) which shields the gate oxide at the bottom of the gate trench from the high electric field during the blocking state and enhances the breakdown voltage (BV), is presented in this study using two-dimensional simulations. The effects of doping concentration, length and position of FLI on BV, electric field distribution and specific on-resistance ( R on,sp ) are studied, thereby providing particularly useful guidelines for the design of this new type of device when considering the breakdown of the gate oxide layer. For the suitable device design, the results indicate that BV and Baliga figure of merit are, respectively, increased by 150 and 439% compared with a conventional SiC UMOSFET. At the same time, the SiC FLI UMOSFET has smaller gate-drain capacitance and better switching performance compared with the conventional UMOSFET on the condition of the same drift layer parameters. FLI introduced have almost no influence on the recovery characteristics of body diode.

Control of electric field in 4H-SiC UMOSFET: Physical investigation

In this paper, we show how breakdown voltage (VBR) and the specific on-resistance (Ron) can be improved simply by controlling of the electric field in a power 4H-SiC UMOSFET. The key idea in this work is increasing the uniformity of the electric field profile by inserting a region with a graded doping density (GD region) in the drift region. The doping density of inserted region is decreased gradually from top to bottom, called Graded Doping Region UMOSFET (GDR-UMOSFET). The GD region results in a more uniform electric field profile in comparison with a conventional UMOSFET (C-UMOSFET) and a UMOSFET with an accumulation layer (AL-UMOSFET). This in turn improves breakdown voltage. Using two-dimensional two-carrier simulation, we demonstrate that the GDR-UMOSFET shows higher breakdown voltage and lower specific on-resistance. Our results show the maximum breakdown voltage of 1340V is obtained for the GDR-UMOSFET with 10µm drift region length, while at the same drift region length and approximated doping density, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534V and 703V, respectively.

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10µm drift region length the maximum breakdown voltage of 1274V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (Ron,sp) of 2mΩcm2, which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.

Schottky Body Diode를 집적하여 향상된 Reverse Recovery 특성을 가지는 50V Power MOSFET

In this paper, 50V power U-MOSFET which replace the body(PN) diode with Schottky is proposed. As already known, Schottky diode has the advantage of reduced reverse recovery loss than PN diode. Thus, the power MOSFET with integrated Schottky integrated can minimize the reverse recovery loss. The proposed Schottky body diode U-MOSFET(SU-MOS) shows reduction of reverse recovery loss with the same transfer, output characteristic and breakdown voltage. As a result, 21.09% reduction in peak reverse current, 7.68% reduction in reverse recovery time and 35% improvement in figure of merit(FOM) are observed when the Schottky width is and the Schottky barrier height is 0.8eV compared to conventional U-MOSFET(CU-MOS). The device characteristics are analyzed through the Synopsys Sentaurus TCAD tool.

Comparison of ultralow specific on-resistance UMOSFET structures: the ACCUFET, EXTFET, INVFET, and conventional UMOSFET's

Three new ultralow specific on-resistance, vertical channel, power UMOSFET structures, with a trench (UMOS) gate extending all the way between N/sup +/ source and the N/sup +/ substrate (drain), are compared with the conventional UMOSFET structure. Specific on-resistances in the range of 100-250 /spl mu//spl Omega/cm/sup 2/ have been experimentally demonstrated for devices capable of supporting 25 V. This is due to current conduction via an accumulation and/or inversion layer formed under gate bias along the trench gate surface, resulting in the lowest specific on-resistance ever reported. >

Comparison of ultralow specific on-resistance UMOSFET structures

The authors describe three novel UMOSFET structures, called the accumulation, inversion, and extended trench field-effect transistors (ACCUFET, INVFET, EXTFET). The principal difference between these structures and the conventional UMOSFET is that the trench (UMOS) gate extends all the way down to the n/sup +/ substrate. A detailed comparison of all the UMOSFET structures has been performed. Two-dimensional numerical simulations using PISCES have demonstrated that a specific on-resistance approaching 100 mu Omega -cm/sup 2/ can be obtained for devices capable of supporting 25 V. For experimental verification, devices were made using a six-mask process and SF/sub 6//O/sub 2/ RIE (reactive ion etching) to form trenches with gate oxide thickness ranging from 260 to 900 AA. The measured specific on-resistances of the experimentally fabricated devices with a gate oxide thickness of 720 AA were found to be 125, 195, and 245 mu Omega -cm/sup 2/ for the ACCUFET, EXTFET, and INVFET structures.