Conventional Topology Research Articles

Analysis of a Doubly-Fed Induction Motor for Soft Start Operation based on Stator Flux Vector Control

This paper aims at analysis of an operation of a doubly-fed induction motor (DFIM). The paper mainly focuses on the soft start method for the DFIM using the conventional topology that is normally used in the case of a doubly-induction generator (DFIG). Likewise, the details about reactive power control is also discussed. With the proposed method, the DFIM can start from zero to any speed by controlling the machine-side converter (MSC). The computer simulation is performed to a 5 kW wound rotor induction motor using PLECS software. The simulation results validate that the DFIM can operate from the rest to any speed while operating only under the conventional topology.

A 24–30‐GHz Modified Gilbert‐Cell Downconverter With High Linearity and Isolation

ABSTRACTThis paper introduces a downconverter mixer employing a modified double‐balanced Gilbert‐cell topology, designed using IHP's 0.13‐m SiGe BiCMOS technology. Distinct from the conventional topology, a resonator was employed at the emitter of the transconductance stage, which enables the utilization of transconductance stage as an active balun, allowing for direct feeding of the single‐ended input without sacrificing the advantageous of the double‐balanced topology. The integration of the resonator reduces the amplitude and phase errors within the active balun segment, thereby enhancing port‐to‐port isolation. The area occupied by the resonator is approximately 1.7 times smaller than that of an RF transformer balun typically employed in conventional double‐balanced topologies. The LO and IF differential signals are converted to single‐ended ones through transformer baluns for measurement purposes. The frequencies of operation for RF, LO, and IF are 24–30, 18–24, and 6 GHz, respectively. The conversion loss is 7.7 dB at 26 GHz, with port‐to‐port isolations exceeding 35 dB. The input 1‐dB compression point is 5.7 dBm, while the circuit consumes 65‐mW power from a 3.3‐V voltage supply. Excluding the pads, the active area of the design spans 1 mm2.

Dual‐state and self‐oscillating wireless charging system topology for direct‐drive battery

AbstractThis study proposes a novel topology with bi‐stable controlling for wireless charging system (WCS). The advantage of the proposal is that a desired charging current can be directly output from rectifier without requiring charging current manager, thereby greatly simplifying the structure of the receiver. The proposed topology not only improves the transmission efficiency of system, but also reduces the loss and heat dissipation in the receiver. The principle of the topology is outlined and the circuitry model and control strategy are established and analyzed in detail. The innovation of this method lies in treating the coupler as a current transformer, which enables more direct and simpler controlling of the charging current. The experiment is conducted to verify that when the peak charging current is increased from 5A to 10A, the system efficiency is increased up to 82.0% and the receiver efficiency up to 96.7%. Both computational simulation and experimental validation have confirmed the feasibility of the proposed method. Compared with conventional WCS topology with compensation, the proposed method improves the system efficiency by 3% and the receiver efficiency by 5%, which is more suitable for practical applications where compact and light‐weight receiver is required.

Nonlinear vibration analysis of sandwich plates with inverse-designed 3D auxetic core by deep generative model

Building on a deep generative model (DGM), this paper introduces an innovative sandwich plate structure featuring an inverse-designed auxetic 3D lattice core and conducts a detailed investigation of its nonlinear vibration characteristics and effective Poisson's ratios under various parameter settings. By incorporating a conditional estimator and quality loss evaluation functions, the enhanced conditional generative adversarial networks are capable of designing 3D truss auxetic topologies that achieve customized negative Poisson's ratios without reliance on subjective experience. Additionally, lattice specimens are created using 3D metal printing, and the mechanical properties of these DGM-based 3D auxetic structures are validated through vibration experiments and finite element models. These structures exhibit significantly superior natural frequencies compared to those obtained through conventional topology optimization methods reported in existing literature. The study also explores the impact of different functionally graded configurations, temperature variations, boundary conditions, and dimensional parameters on the natural frequency, nonlinear vibration response, and effective Poisson's ratio of the inverse designed auxetic sandwich plates.

Novel nine level switched capacitor multi-level inverter based STATCOM for distribution system

FACTS based devices are mostly used in power systems due to their capacity to improve system stability. The Static Synchronous Compensator (STATCOM), a shunt-connected device in the FACTS device family, is used for power compensation, power balancing, and enhancing dynamic stability in contemporary power systems. In the proposed work, STATCOM based novel nine level switched capacitor based multi-level inverter (MLI) is used to reduce power quality issues. The proposed novel inverter has a few number of switches with one voltage source. The placement of STATCOM based inverters in the wrong places may have detrimental effects on power loss and electricity quality. To overcome these issues, green anaconda optimization (GAO) is used to allocate the proposed system in an optimal place. The performance of the proposed inverter is examined using the MATLAB/Simulink tool. This inverter requires fewer switches and achieves DC link voltage balances in comparison to any other existing conventional topologies. STATCOM based inverter is validated under different faulty conditions to show the effectiveness of this inverter. The proposed new inverter has nine levels and compensates for the poor state while improving power quality. The proposed method has a substantially lower total harmonic distortion (THD) of 1.04 % while maintaining an efficiency of 99.02 %. Experimental validation is established using a dSPACE RTI1104 controller to validate the proposed method. Experimental results obtained 1.04 % of harmonics with the same output voltage as the simulation.

Axial, planar-diagonal, body-diagonal fields on the cubic-spin spin glass in d=3: A plethora of ordered phases under finite fields.

A nematic phase, previously seen in the d=3 classical Heisenberg spin-glass system, occurs in the n-component cubic-spin spin-glass system, between the low-temperature spin-glass phase and the high-temperature disordered phase, for number of spin components n≥3, in spatial dimension d=3, thus constituting a liquid-crystal phase in a dirty (quenched-disordered) magnet. Furthermore, under application of a variety of uniform magnetic fields, a veritable plethora of phases is found. Under uniform magnetic fields, 17 different phases and two spin-glass phase diagram topologies (meaning the occurrences and relative positions of the many phases), qualitatively different from the conventional spin-glass phase diagram topology, are seen. The chaotic rescaling behaviors and their Lyapunov exponents are calculated in each of these spin-glass phase diagram topologies. These results are obtained from renormalization-group calculations that are exact on the d=3 hierarchical lattice and, equivalently, approximate on the cubic spatial lattice. Axial, planar-diagonal, or body-diagonal finite-strength uniform fields are applied to n=2 and 3 component cubic-spin spin-glass systems in d=3.

Twice-topology optimized heat sinks for enhanced heat transfer performance: Numerical and experimental investigation

Since the heat dissipation problem is always confusing and hindering the computing power improvement of electronic chip, an effective thermal management strategy is critical to relieve these problems. In this work, a new twice topology optimization design method combining topology optimization and image processing to design heat sinks is presented, which extends topology optimization from 2Dimention (2D) to 3Dimention(3D). Firstly, on the horizontal design domain, the conventional topology optimization is conducted for the minimization of average temperature/standard deviation. Then the optimal shape of liquid domain is converted into 1D flow routine by thinning algorithm. After that, another topology optimization is performed on the flow channel cross-section plane to get the best cross-section shape of channels. The liquid domain of the final heat sink is then obtained by scanning the optimized flow channel cross-section along the 1 Dimension (1D) flow routine and solving the interference by introducing cylinder joints. Finally, two kinds of twice topology optimized heat sinks including TTOHS-1 with minimized temperature variation as optimal goal and TTOHS-2 with minimized average temperature as optimal goal are generated by combining the liquid domain and a cuboid using Boolean Operation. The performance of heat sinks is numerically investigated, and the results indicate that the thermal performance of TTOHS-1 and TTOHS-2 are much better than that of the traditional heat sink with straight channels (TSCHS). When Re = 689, the average temperature and the maximum temperature of the heat source surface of TTOHS-1 are decreased by 4.99 % and 6.29 % respectively, compared to the TSCHS. The Nusselt number is increased by 46.16 % while the thermal resistance is reduced by 33.13 %. At last, the thermal and flow performance of the TTOHS-1 is studied by conducting experiments, showing that the numerical results agree well with that of the experiment.

System-Level Implementation of a Parallel-Path Hybrid Switched-Capacitor Amplifier with an Embedded Successive Approximation Register for IoT Applications

A system-level implementation of a parallel-path hybrid switched-capacitor amplifier is presented in this paper. The proposed parallel-path amplifier incorporates a gain and slew rate-boosting switching path in parallel with an embedded assisted SAR path, aiming for IoT applications. As an alternative concept to the conventional analog topologies, the proposed amplifier combines nonlinear and linear paths to provide coarse and fine amplifications. In the coarse amplification, a high current is provided through a switching path for a fraction of time, which improves the slew rate and open-loop DC gain without adding significant static current. Moreover, high accuracy is achieved through the embedded assisted SAR path, which provides a resolution of 1/2N. In addition, each extra bit of the embedded SAR path improves the total open-loop DC gain by 6 dB. The theory of operation is performed to study how the switching and assisted SAR paths can enhance the amplifier’s settling error. In addition, an existence trade-off between the coarse amplification error and the capacitive digital-to-analog converter’s number of bits is investigated. The theory and system-level simulation show that the gain and slewing restrictions of the conventional topologies, especially in advanced CMOS technology, can be handled much easier by this parallel combination, where the switching path and assisted SAR path combination provides a high slewing capability and high DC open-loop gain.

Multi-switch-controlled multi-mode TRFE with a high-linearity ATRSW for 2.4-GHz ISM applications

This paper presents a multi-switch-controlled multi-mode transceiver front end (TRFE) designed for the 2.4-GHz industrial–scientific–medical (ISM) band, with a particular focus on enhancing the linearity of the transmit/receive switch (TRSW) on the antenna side. Considering the distinct power levels in the RX/TX paths, the TRSW is designed to be asymmetric. This design not only elevates IP-0.1dB by over 50 % compared to the conventional symmetric topology, but also absorbing its function into the input matching network (IMN) of the low noise amplifier (LNA), thereby minimally impacting the noise figure (NF) of the RX chain. For the TX path, the high-pass component of the power amplifier (PA) output matching network (OMN) is repurposed, with a singular inductor being redeployed to serve as an inductive ESD safeguard. Moreover, the driving stage employs a passive gain-boosting technique, which elevates the gain by 3 dB compared to the traditional cascode structure. For verification, this TRFE is fabricated in 0.18-μm CMOS with a die size of 1.53 mm2. It achieves a NF of 2.4 dB and a RX gain of 16.7 dB under a 3.3-V supply. A TX gain of 26.2 dB and a saturation output power of 23.3 dBm with a peak power-added efficiency (PAE) of 38.8 % are also demonstrated.

Visual depiction and numerical characterization of intricate flow in triply periodic minimal surface foams

Benefiting from the structural specificity and programmability, the bioinspired triply periodic minimal surfaces (TPMSs) bring excellent physicochemical properties that are distinct from conventional topologies. Especially with the rapid development of additive manufacturing and high-performance computing capacities, function-oriented design and synthesis of smart TPMS materials or devices have become feasible. Therefore, understanding the flow characterizations induced by TPMS foams is of remarkable importance to the successful design and practical operation. However, the in-depth studies and theoretical guidance on the relationship between structure and flow characterizations of TPMS foams are still limited. In this study, an Eulerian and Lagrangian coupled model is developed to investigate the internal flow behaviors and flow regime transition mechanism from creeping to inertial flow in four representative TPMS foams. The simulation accuracy is then validated by a high-resolution pore-scale flow field observation. Results show that the flow morphology and pressure drop characteristics are highly influenced by TPMS geometry and Re. Among which, Schwarz Diamond (D), Schoen Gyroid (G), and Fischer-Koch S (S) foams are more susceptible to radial flow disturbance, while Schoen inverted Weissenberg periodic foam to axial flow disturbance. In addition, higher porosities delay the transition to transitional regime of the flow. This work establishes firm theoretical and methodological foundations for the customization and intelligent development of bioinspired TPMS foam materials in broad fluidic applications.

A Reconfigurable Phase-Shifted Full-Bridge DC–DC Converter with Wide Range Output Voltage

This paper analyzes, designs and implements a reconfigurable phase-shifted full-bridge (PSFB) converter. It adopts the topology of the traditional PSFB converter and incorporates clamping circuits to solve some fundamental problems of conventional topology. In addition, auxiliary switches are employed for output reconfiguration, which allows expanding the output voltage range without compromising the system efficiency. Single pole double throw (SPDT) mechanical switches are used to realize series and parallel connections. In this paper, the characterization of the PSFB converter with clamping circuit and its design considerations are discussed. A 10 kW prototype with a power density of 0.485 W/cm3, 900 V input voltage and 400/800 V nominal output voltage was manufactured. The experimental results validated the analysis and confirmed the high conversion efficiency for a wide load range; an efficiency of 96.69% was obtained for the full load condition.

Innovative two-dimensional porphyrin-integrated metal-organic frameworks for enhanced photocatalytic hydrogen peroxide generation in pure water

In the quest for eco-friendly and efficient synthesis of hydrogen peroxide (H2O2), a chemical with extensive applications, photocatalytic production emerges as a promising clean technique. Metal-organic frameworks (MOFs), known for their exceptional porosity and geometric customizability, stand at the forefront of potential photocatalytic materials. Yet, the conventional three-dimensional topologies of MOFs pose a challenge, impeding the swift transit of photogenerated electrons and thereby curbing performance enhancements. In this vein, we have engineered novel 2D porphyrin-based MOFs, specifically Ce-TCPP and La-TCPP, utilizing diverse metal sources while maintaining a consistent topological framework. This design strategy streamlines the electron and hole transport pathways, thus elevating the photocatalytic activity. Delving into the structural nuances of these MOFs, our research unveiled that the photocatalytic activity experienced a marked shift upon altering the metal cluster types. Notably, La-TCPP, as an efficacious catalyst, demonstrated an H2O2 yield of 79.75 μmol/g/h in pure water, sans any sacrificial agents. Rigorous testing confirmed the robust stability of both MOFs. This study marks the inaugural design and synthesis of a single crystal structure of La-TCPP. By strategically varying metal cluster compositions, we have fine-tuned the architecture of two-dimensional MOFs. This approach sheds light on the intricate structure-activity relationship governing the photocatalytic synthesis of H2O2, paving the way for future advancements in the field.

Novel Dynamic Event-Triggered Consensus Control of Multiagent Systems With Markovian Switching Topologies Under DoS Attacks.

This article focuses on the issue of novel dynamic event-triggered consensus control of multiagent systems (MASs) with denial-of-service (DoS) attacks. Different from the conventional Markovian switching topologies, the generally uncertain semi-Markovian (GUSM) switching topologies with partially unknown elements and time-dependent uncertainties are constructed for the leader-following MASs by considering the equipment performance and external uncertain environment influence. To save communication resources, the novel dynamic memory event-triggered strategy (DMETS) is presented to decrease the frequency of communication between agents. Some secure consensus control criteria are established for the MASs with GUSM switching topologies and DoS attacks due to the potential system communication disruption caused by attackers. Finally, two physical system examples are designed to prove the effectiveness of the presented method.

A study on a low input current ripple high voltage gain cuk converter

Abstract In the realms of photovoltaic power generation and fuel cells, the application of traditional DC-DC boost converters faces significant constraints due to insufficient gain and pronounced input current ripple. This paper presents a design for a Cuk converter with low input current ripple and high voltage gain based on the conventional Cuk topology. The design incorporates a passive ripple circuit and a coat circuit. The operational principles of the converter are analyzed, followed by the construction of a simulation model in PSIM. Simulation results not only validate the theoretical analysis but also affirm the feasibility of the proposed converter.

Optical network topology design to execute many tasks simultaneously in a disaggregated data center

In a disaggregated data center (DDC), task execution is reliant on the communication between resources, making performance highly sensitive to network quality. An optimized physical network topology is crucial for a DDC. To enable the simultaneous execution of numerous tasks, a substantial number of communicable resource pairs satisfying performance requirements is necessary. We propose a physical topology evaluation metric called the capability of simultaneous task execution (CSTE) and a corresponding physical topology design leveraging CSTE for a DDC equipped with optical networks. CSTE represents the ratio of resources that could be used as a resource communicating with other resources without violating the performance requirements in a situation where tasks up to the maximum number of executable tasks are executed. In addition, we formulated a physical topology design problem aimed at generating a physical network topology capable of maximizing task execution based on CSTE. By solving this optimization problem, we generated topologies and validated their effectiveness via task allocation simulations. The results showed that an optimal topology based on CSTE reduces task blockages by over 50% compared to conventional topologies. In addition, the results exhibited a positive correlation with the number of executable tasks. Through a physical topology design based on CSTE, we could construct a DDC that could handle a larger volume of tasks.

Design, analysis, and implementation of a phase‐shift controlled cascaded H‐bridge and anti‐interleaved zeta converter‐based E‐bike battery charging circuitry

AbstractThe rapid extinction of the fossil fuels across the globe has led to the technological advancements in the field of renewable energy sector and the electric vehicular technology. In order to match the paradigm shift in the energy sector and the technology, the battery charging circuitry of electric vehicle (EV) led to the revolutionary changes in the field of power electronics. Accordingly, various conventional topologies of DC‐DC converters were evolved. But there are a few drawbacks such as bulkiness, nonmultiple ports, and less control over the output current ripple. This work proposes a DC‐DC converter which is a hybrid combination of the full‐bridge converter and the zeta converter. The current and the voltage reversals at the high‐frequency transformer (HFT) terminals are made steady by anti‐interleaving the zeta converters on the secondary side. The control pulses of the full‐bridge converter are phase‐shifted to have the tight grip over the output. The modes of operation of the proposed DC‐DC converter has have presented. The calculation of the energy, current, and the voltage for the active and the passive components of the proposed converter has been provided. The proposed system is simulated, and the plots of the voltages and currents of different components of the converter are presented. The converter prototype has been developed to charge a 36 V lithium‐ion battery, and the effect of the phase shift on input current can be seen from the exhaustive results. The comparison of the calculated and simulated currents and voltages has been graphically illustrated. The proposed converter provides a novel converter topology which includes better output control with phase shift and reduced size of memory elements due to high‐frequency switching.

Solar PV based seventeen level reduced switch symmetrical multilevel inverter topology fed induction motor

Multilevel inverters have received a lot of interest in recent years due to their ability to deliver more voltage levels than typical two-level inverters. Because of this property, multilevel inverters can produce output waveforms that closely resemble sinusoidal waveforms, lowering harmonic distortion dramatically. The emergence of reduced switch symmetrical multilevel inverter topologies has developed the curiosity of many different power conversion systems. These new topologies offer numerous advantages, including greater output voltage quality, fewer harmonic distortions, and increased power conversion efficiency. The inclusion of these inverters in the feeding of induction motors is one of their many prominent uses. A 17 levels of multi-level inverter (MLI) topology is presented with reduced switch count and harmonic reduction for power quality improvement. The inverter is fed by isolated equal photovoltaic panels which act as direct current or DC source. To reduce complexity, switching pulses are generated using hybrid pulse width modulation technique which is designed as controller. Through the use of MATLAB/Simulink, the performance assessment of a unique cascaded multilevel inverter-based reduced switch symmetrical inverter feeding an induction motor drive has been verified. The harmonic distortion with reduced switches obtained is 7.47% which is comparatively less than when compared with conventional cascaded H-bridge topology.

Low-Cost DTC Drive Using Four-Switch Inverter for Low Power Ranges

The direct torque control (DTC) strategy was proposed more than 25 years ago. It is one of the most successful and reliable techniques for AC motors. This paper presents the application of DTC using a four-switch inverter, as one of the non-conventional economic topologies suitable for low power ranges. The experimental prototype proves the validity and effectiveness of the investigated configuration. In addition, for comparison purposes, the DTC technique has been implemented using a conventional six-switch inverter. According to the experimental results, the DTC-based four-switch inverter would be competitive with the conventional topology in low power ranges to achieve an economic AC drive with a satisfactory transient and steady-state performance at moderate costs.

A non-isolated extended voltage gain quadratic boost converter with reduced device voltage stress and continuous input current

ABSTRACT This article presents an improved model of a high voltage gain DC-DC converter topology. The voltage gain of the proposed topology is extended using a newly structured cascaded boost converter with voltage doubler cells along with the Super Luo structure in the network. The ultimate aim is to improve the output voltage gain of the proposed converter to a higher level with a lower duty cycle. Additionally, the design considerations minimize the voltage stress of the components (diodes, capacitors, and semiconductor switches) compared to the conventional topology. Moreover, the proposed topology ensures a continuous input current to the structure. Mathematical modeling is developed using steady-state analysis, and the results are analyzed using the MATLAB/Simulink. Finally, the proposed converter provides a high gain, that is, 10, at a lower duty cycle of 0.32 with reduced voltage stress on the components.

A CMOS 12-Bit 3MS/s Rad-Hard Digital-to-Analog Converter Based on a High-Linearity Resistor String Poly-Matrix

This work presents a rad-hard 12-bit 3 MS/s resistor string DAC for space applications. The converter has been developed using rad-hardened techniques both at architecture and layout levels starting from a conventional topology. The design considers the different effects of the radiation that could damage the circuits in space environments. The DAC has been developed and integrated a standard CMOS 0.13 μm technology by IHP, using RHBD techniques. Low Earth Orbit (LEO) requires a TID value of around 100 krad (Si), according to the expected length of the mission. The temperature range is between −55 °C and 125 °C. The DAC power budget is similar to that of terrestrial applications. The measured INL (Integral Non-Linearity) and DNL (Differential Non-Linearity) are better than 0.2 LSB, while the ENOB (Effective Number Of Bits) at a 3 MS/s clock exceeds 9.7 bits while loading a 10 pF capacitor. The DAC has been characterized under radiation, showing a fluctuation in the analog output lower than 2 LSB (mainly due to measurement uncertainty) up to 500 krad (Si). Power consumption shows a negligible increase, too. A 10-bit version of the same DAC as the downscaled 12-bit one has been developed as well.