Conventional Thin-film Transistors Research Articles

Sputtered AlOx interlayer for improving performance of a-InGaZnO TFTs: A study on hydrogen diffusion mitigation and electron modulation

In this study, we developed an a-InGaZnO (a-IGZO) thin film transistor (TFT) structure that inserts a sputtered AlOx intermediate layer (IL) within the active layer. The IL not only effectively blocks hydrogen (H) diffusion from the gate insulation (GI) layer to the upper region of a-IGZO but also modifies the energy band structure of the bottom channel region and creates a locally low electron concentration that counteracts the excess electron donated by diffused H. Compared to conventional TFTs, the TFT with the IL exhibits impressive electrical characteristics, including a high saturation mobility (μsat) of 14.5 cm2 V−1 s−1, an on/off current ratio (Ion/Ioff) of 6.2 × 108, and a low subthreshold swing (SS) of 0.16 V/dec. Furthermore, this structure exhibits remarkable stability under negative bias stress and negative bias illumination stress, with ΔVth values of 1.1 and 1.5 V, respectively. The integration of the IL provides a promising approach for enhancing the performance of a-IGZO TFTs, paving the way for next-generation display technologies.

Intense pulsed light annealing of solution-based indium–gallium–zinc–oxide semiconductors with printed Ag source and drain electrodes for bottom gate thin film transistors

In this study, an intense pulsed light (IPL) annealing process for a printed multi-layered indium–gallium–zinc–oxide (IGZO) and silver (Ag) electrode structure was developed for a high performance all-printed inorganic thin film transistor (TFT). Through a solution process using IGZO precursor and Ag ink, the bottom gate structure TFT was fabricated. The spin coating method was used to form the IGZO semiconductor layer on a heavily-doped silicon wafer covered with thermally grown silicon dioxide. The annealing process of the IGZO layer utilized an optimized IPL irradiation process. The Ag inks were printed on the IGZO layer by screen printing to form the source and drain (S/D) pattern. This S/D pattern was dried by near infrared radiation (NIR) and the dried S/D pattern was sintered with intense pulsed light by varying the irradiation energy. The performances of the all-printed TFT such as the field effect mobility and on–off ratio electrical transfer properties were measured by a parameter analyzer. The interfacial analysis including the contact resistance and cross-sectional microstructure analysis is essential because diffusion phenomenon can occur during the annealing and sintering process. Consequently, this TFT device showed noteworthy performance (field effect mobility: 7.96 cm2/V s, on/off ratio: 107). This is similar performance compared to a conventional TFT, which is expected to open a new path in the printed metal oxide-based TFT field.

Enhancement of electrical performance in indium-zinc oxide thin-film transistors with HfO2/Al2O3 gate insulator deposited via low-temperature ALD

Several studies have been conducted on amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) with the aim of applying them to the next-generation low-power displays. To improve the electrical performance of conventional AOS TFTs, which are known for their poor switching characteristics, we fabricated indium-zin oxide (IZO) TFTs with HfO2/Al2O3 gate insulator deposited via low-temperature atomic layer deposition (ALD). We optimized the electrical performance of the fabricated TFTs by varying the thickness of the IZO channel and Al2O3 insulator, respectively. Compared to the samples with a thermally grown 150 nm thick SiO2 gate insulator, the samples with a 10 nm thick IZO channel and a 10/70 nm thick HfO2/Al2O3 gate insulator exhibited the subthreshold swing of 0.24 V/dec, saturation carrier mobility of 7.49 cm2/V∙s and on–off current ratio of 1.09 × 107, which were improved by more than 47 %, 64 % and 5 times, respectively. Also, the threshold voltage shift in positive and negative bias stress conditions were improved to + 0.90 and – 1.75 V, respectively.

Room-temperature fabrication of flexible oxide TFTs by co-sputtering of IGZO and ITO

Amorphous oxide semiconductors, especially indium gallium zinc oxide (IGZO), have been widely studied and obtained significant progress in flexible thin-film transistors (TFTs) due to the high carrier mobility and low deposition temperature. However, a further annealing step is generally required to activate electrical properties and improve the device performance, which limited their applications in flexible electronics. In this study, we achieved flexible TFTs and arrays using co-sputtered IGZO and indium tin oxide (ITO) as channels deposited at room temperature without post-annealing. It was found that better transistor switching properties could be effectively achieved by regulating the sputtering power of ITO in the co-sputtered deposition. The device performance is comparable to that of the conventional oxide TFTs with high annealing temperatures (⩾300 °C), exhibiting a high saturation mobility (μ sat) of 15.3 cm2 V−1s−1, a small subthreshold swing (SS) of 0.21 V dec−1, and a very high on–off ratio (I on/off) of 1011. In addition, a 12 × 12 flexible TFT array was achieved with uniform performance owing to the low-temperature processing advantage of this technique. The flexible TFTs exhibited robust mechanical flexibility with a minimum bending radius of 5 mm and bending cycles up to 1000. Furthermore, an inverter based on co-sputtered IGZO and ITO was demonstrated with the maximum gain of 22. All these achievements based on the proposed TFTs without post-annealing process are expected to promote the applications in advanced flexible displays and large-area integrated circuits.

High-Performance Indium-Based Oxide Transistors with Multiple Channels Through Nanolaminate Structure Fabricated by Plasma-Enhanced Atomic Layer Deposition

An atomic-layer-deposited oxide nanolaminate (NL) structure with 3 dyads where a single dyad consists of a 2-nm-thick confinement layer (CL) (In0.84Ga0.16O or In0.75Zn0.25O), and a barrier layer (BL) (Ga2O3) was designed to obtain superior electrical performance in thin-film transistors (TFTs). Within the oxide NL structure, multiple-channel formation was demonstrated by a pile-up of free charge carriers near CL/BL heterointerfaces in the form of the so-called quasi-two-dimensional electron gas (q2DEG), which leads to an outstanding carrier mobility (μFE) with band-like transport, steep gate swing (SS), and positive threshold voltage (VTH) behavior. Furthermore, reduced trap densities in oxide NL compared to those of conventional oxide single-layer TFTs ensures excellent stabilities. The optimized device with the In0.75Zn0.25O/Ga2O3 NL TFT showed remarkable electrical performance: μFE of 77.1 ± 0.67 cm2/(V s), VTH of 0.70 ± 0.25 V, SS of 100 ± 10 mV/dec, and ION/OFF of 8.9 × 109 with a low operation voltage range of ≤2 V and excellent stabilities (ΔVTH of +0.27, -0.55, and +0.04 V for PBTS, NBIS, and CCS, respectively). Based on in-depth analyses, the enhanced electrical performance is attributed to the presence of q2DEG formed at carefully engineered CL/BL heterointerfaces. Technological computer-aided design (TCAD) simulation was performed theoretically to confirm the formation of multiple channels in an oxide NL structure where the formation of a q2DEG was verified in the vicinity of CL/BL heterointerfaces. These results clearly demonstrate that introducing a heterojunction or NL structure concept into this atomic layer deposition (ALD)-derived oxide semiconductor system is a very effective strategy to boost the carrier-transporting properties and improve the photobias stability in the resulting TFTs.

Highly Robust Flexible Poly-Si Thin Film Transistor Under Mechanical Strain With Split Active Layer for Foldable Active Matrix Organic Light Emitting Diode Display

We report a novel active split structure of low-temperature polysilicon (LTPS) thin film transistor (TFT) on polyimide (PI) substrate showing robust electrical performance under mechanical strain. The compressive and tensile bending tests were carried out with cylinders of radii 3, 2 and 1 mm respectively. The active split TFT exhibits much more stable electrical performance than the conventional TFT. The conventional LTPS TFT shows electrical failure due to the crack generation during tensile or compressive bending test carried out with 1 mm radius cylinder. The split poly-Si islands could resist crack formation/propagation, resulting in a robust electrical performance.

Fabrication and characterization of T-gate polysilicon thin-film transistors with lightly-doped drain

We report detailed fabrication and characterization of poly-Si thin-film transistors (TFTs) with T-shaped gate (T-gate) and lightly-doped drain (LDD) structures. The formation of the LDD underneath the wings of a T-gate primarily relies on the shadowing of implanted dopants during the implantation of source and drain. Therefore, the fabrication of LDD structures in our proposed T-gate poly-Si TFTs can save a number of process steps as compared to conventional poly-Si TFTs with LDD structures. Our fabricated T-gated poly-Si TFTs with LDD structures not only exhibit suppressed off-state leakage current but also show a significant improvement in on-state current as compared to that of conventional poly-Si TFTs with the same top-gate dimension.

전기화학적으로 산화된 투과성 베이스 전극을 갖는 수직구조 유기 트랜지스터

Vertical organic thin film transistors (VOTFTs) are emerging electronic devices that can overcome the limitations of conventional organic thin film transistors (OTFTs) based on lateral architecture. Here, organic permeable base transistors (OPBTs) are formed with an oxide layer on the base electrode through an electrochemical process called anodization, and this oxide layer acts as a dielectric layer. Through this electrochemical method, the manufacturing process is simplified and the charge carrier transport of the VOTFT is improved. In this study, the thickness of AlOx formed by anodizing the Al electrode was calculated through the capacitance-voltage measurement of the metal-insulator-metal device, and OPBT operations were observed according to the anodizing potential and interfacial layer, respectively. In addition, we observed the specific behaviors of vertical OPBT depending on the applied potential correlations between middle base electrode and bottom collector electrode.

Process Development of Amorphous Indium Tin Gallium Oxide (ITGO) Thin Film Transistors

The invention of portable electronic devices had a huge impact on the growing interest in flat panel displays. Since the first report in 2004 on amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors (TFTs), many companies have become interested in this material. The main advantage of a-IGZO over conventional amorphous silicon TFTs is its steep subthreshold, low off state current, and high channel mobility. However, the demand for larger displays with higher resolution and refresh rates is driving the demand for TFTs with higher performance, while avoiding the cost and complexity associated with low temperature polycrystalline silicon. There is an increased focus on alternative amorphous oxide semiconductors for use as TFT channel materials, due to the success of a-IGZO.The focus of this study is an investigation on Indium-Tin-Gallium-Oxide (ITGO) TFTs. Unpassivated bottom-gate devices were fabricated with a 30nm a-ITGO film, sputter deposited with 1% and 10% oxygen gas ambient, followed by a 2 hour anneal at 300oC in oxygen. Devices fabricated with PO2 = 1% resulted in a highly conductive channel. Devices with PO2 = 10% displayed semiconducting behavior and a shallow subthreshold. This trend held for all device dimensions tested; lengths of 24µm, 12µm, and 6µm with a width of 24µm. Compared to a-IGZO devices with a length of 4µm, ITGO devices with a length of 12µm exhibit an equivalent current drive, implying a 3 to 4 times improvement in mobility.Following aging in room ambient for multiple days, a-ITGO devices displayed improved yet left-shifted transfer characteristics. In unpassivated a-IGZO devices, similar behavior can also be observed and is attributed to an inhomogeneous trap distribution across the channel. As the exposed channel reacts with room air, oxygen vacancies are filled resulting in a more homogeneous trap distribution. A radial variation of device performance from the center of the wafer to the edge was also observed. When measuring devices towards the edge of the wafer a considerable left shift in transfer characteristics was observed. This variation in device performance is believed to be attributed to non-uniformities in the as deposited ITGO film and will be related to material optical parameters. Figure 1

(Invited) Modeling Oect Devices for Circuit Simulations

Organic electrochemical transistors (OECTs) can be distinguished from conventional organic thin film transistors (OTFTs) by the use of an electrolyte in their gate stack. This results in a unique set of device properties, most notably, mixed ionic and electronic transport. Modeling of these devices has mainly been realized using MOSFET-like equations (often called the ‘Bernards model’) and extensions, which use a circuit diagram to include the different parasitics and capacitances involved [1]. While these models provide qualitative agreements with OECT devices, their quantitative agreement may not be sufficient for realizing circuit simulations. Physically, the discrepancy between the model and the devices are likely to stem from the assumption that the electrolyte behaves as a parallel plate capacitor, as in a conventional MOSFET. Recently, another model based on thermodynamics has been proposed that treats the OECT as a thermodynamic binary system with entropic mixing as the driving force for device operation [2]. Here we explore these different models and then show how they can be used to understand circuit behavior of OECTs.The authors thank the ANR and the Bundesministerium für Bildung und Forschung (BMBF) for funding of the BAYOEN project under contract ANR-21-FAI1-0006-01 and 01IS21089.[1] J Rivnay et al Organic electrochemical transistors. Nature Reviews Materials, 3(2):1–14, 2018[2] M. Cucchi et al ‘Thermodynamics of Organic Electrochemical Transistors’, accessed on researchsquare.com, https://doi.org/10.21203/rs.3.rs-1143463/v1 Figure 1

(Invited, Digital Presentation) Evaluation of Polycrystalline-Si1-XGex Thin-Film Transistors Grown Laterally on a Glass Substrate Using a Continuous-Wave Laser

System-on-glass requires high-performance thin-film transistors (TFTs). In order to realize high-performance polycrystalline-Si (poly-Si) TFTs, we grew high-quality poly-Si thin films using a continuous-wave solid-state laser, in a method known as continuous-wave laser lateral crystallization (CLC). The grain boundary (G.B.) of CLC poly-Si is characterized by being parallel to the laser scan direction with shape of nearly straight line. Ge-based devices are attractive because of the superior carrier mobility of Ge in comparison to Si; however, as carriers in poly-Ge thin film are high concentration of hole generated from defects, it is difficult to control the level of doping. Moreover, fabrication of stable gate dielectric GeO2 is highly challenging. Addition of Ge to Si is expected to improve carrier mobility in Si, leading to poly-Si1-xGex TFTs with better performance than conventional poly-Si TFTs. Hence, our work here is a step in that direction. The purpose of this study is to understand the performance of poly-Si1-xGex TFTs, and to highlight the issues pertaining to poly-Si1-xGex thin films by comparing the performance of poly-Si1-xGex TFTs with that of poly-Si TFTs.A typical TFT fabrication process is as follows. An amorphous Si1-xGex thin film (~100 nm) with a Ge concentration of 10% is grown on a quartz substrate. After cleaning the substrate surface with hydrogen fluoride solution, CLC is carried out in air without substrate heating, followed by the preparation of transistor islands using reactive ion etching (RIE). A 50-nm-thick SiO₂ film is deposited by plasma enhanced chemical vapor deposition (PECVD), followed by heat treatment in nitrogen atmosphere at 550 °C for 4 h and deposition of Mo film as the top gate. Next, P or BF₂ is ion-implanted into poly-Si1-xGex for source-drain (SD) respectively, at 10 keV and 3×1015 cm-2. After ion implantation is completed, interlayer dielectric SiO2 film is deposited by PECVD and activated by heating in nitrogen atmosphere at 550 °C for 6 h. Subsequently, contact holes and Mo electrodes are formed. Finally, hydrogenation using step-cooling is performed to complete the TFT. N-channel (n-ch) and P-channel (p-ch) poly-Si TFTs are also fabricated using identical processes. Two types of TFTs were fabricated for both poly-Si1-xGex TFTs and poly-Si TFTs: one with the G.B. lying parallel to the SD direction (parallel type) and the other with the G.B. perpendicular to the SD direction (perpendicular type).The transfer characteristics of n-ch TFTs showed that the threshold voltages (Vth) of poly-Si1-xGex shifted in the positive direction in comparison with those of poly-Si TFTs. The mobility and sub-threshold swing (s.s.) values of poly-Si1-xGex were inferior to those of poly-Si TFTs, for both the parallel and perpendicular types.Considering the p-ch TFTs, the transfer characteristics of parallel poly-Si1-xGex TFTs showed higher OFF current and lower ON current than the corresponding poly-Si TFTs. In case of perpendicular types, OFF currents of poly-Si1-xGex TFTs were comparable with that of poly-Si TFTs and ON currents of poly-Si1-xGex TFTs were lower than those of poly-Si TFTs. Moreover, Vth values of poly-Si1-xGex TFTs were shifted in the positive direction in comparison to those of poly-Si TFTs, for both parallel and perpendicular types.The segregation coefficient of Ge in Si is less than 1.0, and it has been shown that Ge segregates to G.B.s in poly-Si1-xGex thin films during solidification. As acceptors are generated in regions with high Ge concentration along G.B.s, p-type quasi-one-dimensional conduction regions were formed in Si1-xGex along G.B.s. Therefore, when SD regions are parallel to a G.B., a current path connecting those regions is formed along G.B.s in p-type poly-Si1-xGex TFTs, leading to enhancement of OFF current. However, when G.B.s lie perpendicular to SD regions, the latter remain unconnected, leading to normal OFF current values.The positive shift in Vth of poly-Si1-xGex TFTs can be explained by the formation of acceptors. It can also be concluded that the decrease of ON current in poly-Si1-xGex TFTs is due to ionized impurity scattering by the acceptors. In addition, the difference in the magnitude of ON current depending on the G.B. direction can be explained as follows: when G.B.s are parallel to the SD direction, ON current is higher than that of the perpendicular type, because G.B.s do not act as strong scattering centers.In summary, the characteristics of CLC poly-Si1-xGex TFTs can be explained by the formation of acceptors. In particular, the large OFF current in parallel p-ch poly-Si1-xGex TFTs is explained by Ge segregation along G.B.s, resulting in formation of quasi-one-dimensional p-type conduction channels and electrical connection between SD region.

(Invited) Hydrogenated Polycrystalline In2O3 (In2O3:H) Thin-Film Transistor with High Mobility Exceeding 100 cm2V−1s−1 Via Solid-Phase Crystallization

Oxide semiconductors have been extensively studied as active channel layers of thin-film transistors (TFTs) for electronic applications. However, the field-effect mobility (μ FE) of oxide TFTs is not sufficiently high to compete with that of low-temperature-processed polycrystalline-Si TFTs (50–100 cm2V−1s−1). Here, we propose a simple process to obtain high-performance TFTs, namely hydrogenated polycrystalline In2O3 (In2O3:H) TFTs grown via the low-temperature solid-phase crystallization (SPC) process. In2O3:H TFTs fabricated at 300 °C exhibit superior switching properties with µ FE = 139.2 cm2V−1s−1. The hydrogen introduced during sputter deposition plays an important role in enlarging the grain size and decreasing the subgap defects in SPC-prepared In2O3:H. The proposed method does not require any additional expensive equipment and/or change in the conventional oxide TFT fabrication process. We believe these SPC-grown In2O3:H TFTs have a great potential for use in future electronic applications.

(Invited) Approach to Oxide Tfts with High Mobility & Stability

Thin film transistors (TFTs) with the channel of amorphous oxide semiconductors (AOSs) represented by amorphous Indium-Gallium-Zinc Oxide (a-IGZO) are now applied to drive pixels of the state-of the art display based on high mobility, good homogeneity, easy fabrication and optical transparency [1]. Recently, larger mobility TFTs are highly demanded for emerging applications such as ultra-high vision and memories. However, there is a critical obstacle to be overcome, i.e., an empirical trade-off rule in oxide TFTs between mobility and stability. Higher mobility TFTs possess less stability to various types of stress (negative bias-thermal stress instability, NBTS, positive bias-thermal stress instability, PBTS, and negative bias-illumination stress instability, NBIS). The Elucidation of origin for this trade-off rule and new approach are required to realize high mobility and high stability TFTs. We clarify that the origin of this trade-off through comparison in TFTs between IGZO with low mobility and high stability and ITZO with high mobility and low stability. A critical phenomenon was noted during the conventional TFT fabrication; CO-related impurity donates electrons to Indium-Tin-Zinc Oxide (ITZO) with high mobility under the negative bias stress condition but such CO-related impurity effect is negligible in IGZO with lower mobility than ITZO [2]. This finding may be understood by considering that large difference in ECBM determines the transfer of electron generated by adsorbed CO-related species on the back surface of ITZO [3]. Based on this model and this finding, we successfully fabricated the most stable ITZO TFT with a high mobility of 70 cm2/Vs by eliminating CO-related impurity and further passivation; NBTS (-20V, 60 oC, 3600 s, ΔVth: -0.02 V), PBTS (+20 V, 60 oC, 3600 s, ΔVth: 0.12 V) and NBIS (-20V, 15000 lx, 3600s, ΔVth: -1.33 V).[1] Hosono, H., & Kumomi,K., (ed), Amorphous Oxide Semiconductors: IGZO and Related Materials for Display and Memory (Wiley, 2022); Hosono, H. (2018). How we made the IGZO transistor. Nature Electronics, 1(7), 428-428.[2]Shiah, Y. S., Sim, K., Ueda, S., Kim, J., & Hosono, H. (2021). Unintended Carbon-Related Impurity and Negative Bias Instability in High-Mobility Oxide TFTs. IEEE Electron Device Letters, 42(9), 1319-1322.[3] Shiah, Y. S., Sim, K., Shi, Y., Abe, K., Ueda, S., Sasase, M., Kim,J., & Hosono, H. (2021). Mobility–stability trade-off in oxide thin-film transistors. Nature Electronics, 4(11), 800-807.

P‐1.14: Comparison of the Short‐Channel Effects in Source‐Gated Transistors and Conventional Thin Film Transistors

P‐1.14: Comparison of the Short‐Channel Effects in Source‐Gated Transistors and Conventional Thin Film Transistors

Monolithic Integration, Performance, and Comparison of Self-Aligned and Conventional IGZO Thin-Film Transistors on a Flexible Substrate

Flexible electronics, most prominently thin-film transistors (TFTs) on plastic substrates are considered the prime building block for the realization of innovative wearable systems. Two of the currently most successful fabrication processes of transistors on free standing polymer foils are large-area compatible devices structured by conventional UV lithography and high-speed transistors realized by self-alignment. Here, both processes, based on InGaZnO technology, are combined for the first time. This demonstrates their compatibility, but also showcases the differences between the resulting devices. Concerning the geometry, TFTs with the same nominal designed channel length of 1.5 μm, exhibit real channel length of 1.5 μm (self-aligned) and 4.5 μm (conventional). Furthermore, the integrated side by side fabrication enables the electrical comparison of both types of TFTs excluding external factors. While all TFTs exhibit similar threshold voltages around 0 V and excellent on/off ratios of ≈10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> , conventional TFTs are easier to fabricate, and have comparably higher mobilities up to 16 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . At the same time, self-aligned TFTs demonstrate better AC performance, demonstrating a maximum oscillation frequency of 216 MHz. This integration shows new possibilities for the realization of complex systems made from building blocks optimized for reliability and speed.

A thin‐film transistor with no apparent channel for simplified, high aperture ratio pixel architectures

AbstractAdvances in practical electronics often result from the quest to improve the scalability of fundamental components, but improvements in the scalability of thin‐film transistors (TFTs) have been frustrated by performance degradation at reduced dimensions. In particular, many of these scaling issues are tied to a common feature of all transistors, the semiconductor channel. Here, we introduce TFTs with source and drain materials in direct contact. In the absence of a channel, these TFTs maintain excellent performance including high effective mobility and low voltage saturation. Central to our design is the combination of the depleting properties of a Schottky source electrode with a quasi‐metallic drain material, in this case indium‐tin‐oxide. As an example application, we propose a simpler, more compact pixel architecture for realizing high‐resolution displays, which reduces transistor area by two thirds and can reduce pixel power consumption by almost 80% when compared to conventional TFT structures.

Combustion-assisted low-temperature solution process for high-performance SnO2 thin-film transistors

In this study, high-performance SnO2 thin-film transistors (TFTs) were fabricated at temperatures below 300 °C using the combustion-assisted sol-gel method. The internal energy induced by the exothermic reaction of the fuel and the oxidizer in the combustion precursors facilitates precursor conversion even at low processing temperatures, leading to the development of crystalline SnO2. Compared to the conventional solution process, it was confirmed that the precursor was converted to crystalline SnO2 at below 300 °C through thermogravimetric analysis, differential scanning calorimetry, and grazing incidence X-ray diffraction. In addition, X-ray photoelectron spectroscopy spectra indicate the formation of complete metal-oxygen-metal networks with an increase in the oxygen corresponding to the lattice, as well as a decrease in hydroxyl groups. As a result, compared with the conventional SnO2 TFTs, the field-effect mobility of combustion-assisted SnO2 TFTs increased significantly from 0.014 ± 0.01 to 2.43 ± 0.22 cm2/Vs at 250 °C (by ∼ 170 times) and from 0.38 ± 0.15 to 6.53 ± 0.41 cm2/Vs at 300 °C (by ∼ 17 times). Therefore, the combustion-assisted solution process is expected not only to realize fully low-cost solution-processed electronics by fabricating high-quality SnO2 at low temperatures, but also to be combined with plastic substrates to fabricate flexible electronics.

High-mobility hydrogenated polycrystalline In2O3 (In2O3:H) thin-film transistors

Oxide semiconductors have been extensively studied as active channel layers of thin-film transistors (TFTs) for electronic applications. However, the field-effect mobility (μFE) of oxide TFTs is not sufficiently high to compete with that of low-temperature-processed polycrystalline-Si TFTs (50–100 cm2V−1s−1). Here, we propose a simple process to obtain high-performance TFTs, namely hydrogenated polycrystalline In2O3 (In2O3:H) TFTs grown via the low-temperature solid-phase crystallization (SPC) process. In2O3:H TFTs fabricated at 300 °C exhibit superior switching properties with µFE = 139.2 cm2V−1s−1, a subthreshold swing of 0.19 Vdec−1, and a threshold voltage of 0.2 V. The hydrogen introduced during sputter deposition plays an important role in enlarging the grain size and decreasing the subgap defects in SPC-prepared In2O3:H. The proposed method does not require any additional expensive equipment and/or change in the conventional oxide TFT fabrication process. We believe these SPC-grown In2O3:H TFTs have a great potential for use in future transparent or flexible electronics applications.

Multi-Segment TFT Compact Model for THz Applications.

We present an update of the Rensselaer Polytechnic Institute (RPI) thin-film transistor (TFT) compact model. The updated model implemented in Simulation Program with Integrated Circuit Emphasis (SPICE) accounts for the gate voltage-dependent channel layer thickness, enables the accurate description of the direct current (DC) characteristics, and uses channel segmentation to allow for terahertz (THz) frequency simulations. The model introduces two subthreshold ideality factors to describe the control of the gate voltage on the channel layer and its effect on the drain-to-source current and the channel capacitance. The calculated field distribution in the channel is used to evaluate the channel segment parameters including the segment impedance, kinetic inductance, and gate-to-segment capacitances. Our approach reproduces the conventional RPI TFT model at low frequencies, fits the measured current–voltage characteristics with sufficient accuracy, and extends the RPI TFT model applications into the THz frequency range. Our calculations show that a single TFT or complementary TFTs could efficiently detect the sub-terahertz and terahertz radiation.

Neutron flat-panel detector using In-Ga-Zn-O thin-film transistor.

Neutron imaging is a powerful tool for observing the internal structure of an object without destroying the object. Neutron imaging (neutron radiography) is a prominent application of neutrons but still requires significant improvements, for example, in sensitivity, resolution, radiation hardness, and handling of neutron imaging detectors. This paper presents the development and the first neutron imaging results of a neutron flat-panel detector (nFPD) based on an In-Ga-Zn-O (IGZO) thin-film transistor (TFT)/photodiode array coupled with a LiF/ZnS scintillator sheet. Direct photo-coupling to the scintillator increases the light collection efficiency. Moreover, unlike lens-coupled neutron cameras, the proposed detector is compact and easy to handle. Owing to the high off-state resistance of IGZO TFTs, their leakage current is lower than that of conventional TFTs, enabling the IGZO TFTs to hold an accumulated charge for a longer period of time and allowing longer exposure times for imaging. This would be a powerful feature for imaging at compact neutron sources with limited flux. This paper reports on the first neutron imaging results with an IGZO nFPD, its performance evaluation, and a demonstration of three-dimensional computed tomography with neutrons.