Conventional Synchronous Reference Frame Phase-locked Loop Research Articles

Analysis of optimized phase locked loop for grid synchronization of solar PV system under grid disturbances

AbstractIn this work, an optimal phase locked loop (PLL) is employed to estimate the fundamental grid frequency and phase angle under grid disturbances, which largely reduces the frequency and phase error. Conventional synchronous reference frame (SRF) offers considerable results for balanced grid conditions but has poor performance under grid disturbances with improper phase detection. In this regard, gravitational search algorithm (GSA)‐based optimization is utilized to optimally tune the proportional and integral (PI) gain values of conventional SRF PLL, which ensures the proper tracking of fundamental phase angle and frequency even during abnormal grid conditions, that is, voltage unbalance, frequency variations, high‐frequency harmonics, and phase variations. Further, integral square error (ISE) criteria, settling time, and overshoot are considered as objective functions to obtain the optimal value of current gain, present in the control loop of a grid‐tied solar photovoltaic (PV) system. The supremacy of the proposed work, compared to SRF and optimal SRF PLL, is tested with MATLAB®/Simulink studies and verified by dSPACE‐1104‐based hardware‐in‐loop (HIL) results for real‐time validation.

Sensorless Control Strategy for BLDC Motors Based on a Type-3 Phase Locked Loop

This paper presents the design procedure of a high-performance sensorless control strategy for the widely used brushless DC (BLDC) motors. Generally, conventional sensorless techniques are based on detecting the zero-crossing instants (ZCP) of the back electromotives forces (back-EMFs) of the three phases. These methods, although widely adopted and marketed on an industrial level, involve many limitations such as filtering delays, difficulty to operate at low speeds and immunity against Electromagnetic Interferences (EMI). In this paper, the main objective is to develop a sensorless control technique integrally independent from the zero-crossing points of the back-EMFs. In the proposed method, a zero-delay adaptive filter was used to extract the fundamental and the quadrature components of the line-to-line voltage of the motor. Then, the Synchronous Reference Frame Phase Locked Loop (SRF-PLL) is used to estimate the electrical angle of phase-to-phase back-EMF along with the rotor speed. The conventional SRF-PLL was implemented using a second-order loop filter (type-3 PLL) in order to improve synchronization performances and for better rejection of voltage spikes induced in motor phases during commutations. The benefits of the control technique are brought to light through simulation results. An experimental prototype was designed to confirm the validity of the proposed method.

DC offset elimination method of Phase-locked loop based on novel generalized integrator

When the renewable energy power is connected to the grid, distortion voltage interference and grid voltage frequency fluctuation will occur, which will cause the inverter output current to be abnormal. So the grid-connected environment of weak grid puts forward higher requirements on the performance of phase-locked loop (PLL). The synchronous reference frame PLL(SRF-PLL) has become a usually adopted method in grid synchronization technique for its simple structure and strong stability. However, the conventional SRF-PLL has insufficient capability to suppress DC offset, which easily causes fundamental frequency and phase oscillations. Therefore, this paper presents a novel generalized integrator(NGI), and according to the presented NGI structure, a modified novel generalized integrator (MNGI) that can eliminate DC offset voltage is proposed. Then a novel PLL based on dual MNGI(DMNGI) is proposed. This method improves the capability of the phase-locked loop to suppress DC offset. At the same time, this paper designs the parameters of the PLL, and the rationality of the novel PLL is tested effectively through the experimental comparison with the other two methods.

Hedge-Algebra-Based Phase-Locked Loop for Distorted Utility Conditions

This paper presents the first application of the hedge-algebra theory in the field of grid synchronization. For this purpose, an optimized hedge-algebra controller (HAC) is developed and incorporated within the three-phase phase-locked loop (PLL) with moving average filters (MAFs) inside its feedback loop. Optimized fuzziness parameters and linguistic rule base of the HAC are obtained by a genetic algorithm using the integral of absolute error as the performance index during optimization. Calculated optimal parameter values of the HAC depend on the most frequently occurring disturbance in the electric grid. Two different PLL structures are proposed, depending on the types of disturbances occurring in the electric grid. The first structure is the conventional synchronous reference frame PLL with the nonadaptive MAF (i.e., MAF without order adjustment), but with the PI/PID controller in the phase loop replaced by the developed HAC. Such PLL structure is suitable for all analyzed disturbance types, expect for step-changes in the grid frequency. The second PLL structure introduces the adaptive MAF (i.e., MAF with order adjustment) and a new feedback signal in the output stage of the controller to achieve zero steady-state error in the case of step-changes in the grid frequency. The disturbance rejection capability of the two developed PLLs with the HAC (HAC-PLLs) is tested separately and compared experimentally with the PID- and fuzzy-controller-based PLLs.

Comparison of Synchronization Techniques Under Distorted Grid Conditions

In grid-connected power converter applications, the phase-locked loop (PLL) is probably the most widely used grid synchronization technique, owing to its simple implementation. However, in power grids some very common problems, such as voltage distortion, voltage unbalance, and frequency instability make synchronization a challenging task. The performance of the conventional synchronous reference frame PLL (SRF-PLL) is greatly reduced in the presence of distorted grid conditions. For a polluted grid some advance PLL techniques have been proposed, such as moving average filter PLL (MAF-PLL) and cascaded delayed signal cancellation PLL (CDSC-PLL). These techniques have been mostly evaluated in the presence of odd and even harmonics but the effects of interharmonics on these synchronization techniques still needs to be investigated. In this paper, a detailed performance comparison has been made between SRF-PLL, MAF-PLL, and CDSC-PLL for grid voltages contaminated with interharmonics in the presence of different grid disturbances, such as frequency jump, phase angle jump, and dc offset. The techniques are simulated using Matlab/Simulink. The CDSC-PLL shows excellent performance as compared with other techniques in terms of dynamic response as it settles to frequency step change in a half cycle but the presence of interharmonics greatly reduces its filtering capability. On the other hand, MAF-PLL gives a ripple free behavior in frequency estimation but with a much slower dynamic response as it settles to a frequency step change in more than three cycles. SRF-PLL only performs well under harmonics free grid voltages.

A PLL-Based Controller for Three-Phase Grid-Connected Power Converters

The current control of three-phase grid-connected converters is typically carried out by using a proportional-resonant controller or synchronous reference frame (SRF) proportional-integral regulator. The implementation of these controllers often requires knowledge of the grid voltage frequency/phase angle, which is typically provided by a synchronization unit. It implies that dynamics and possible inaccuracies of the synchronization unit have a considerable impact on the current controller performance. The aim of this letter is to design an adaptive current controller by using a conventional SRF phase-locked loop. In this way, the current controller and synchronization part are merged into a single unit, which results in a simpler and more compact structure. The effectiveness of the proposed controller is verified using experimental results.

A Novel Type-1 Frequency-Locked Loop for Fast Detection of Frequency and Phase With Improved Stability Margins

The synchronous reference frame phase-locked loop (SRF-PLL) is a widely used synchronization technique in power electronics and power systems applications due to its ease of implementation and robust performance. The conventional SRF-PLL is a type-2 control system due to the use of proportional-integral controller as loop filter. With higher bandwidth design, it can achieve fast detection of frequency and phase under ideal grid conditions. However, its bandwidth should be sufficiently lowered to obtain proper disturbance rejection under unbalanced and distorted grid conditions. This results in a slower detection speed. Recently, several advanced PLLs with pre/in-loop filtering stage have been proposed to improve the detection speed. A major challenge with the PLLs is how to further improve their dynamic performance without compromising the disturbance rejection capability and stability. To resolve this issue, in this paper, a novel type-1 frequency-locked loop (FLL) is proposed. The disturbance rejection capability of the proposed FLL is improved using a modified structure low-pass filter with selective harmonics filtering ability. As the proposed FLL is type-1 control system, it achieves better dynamic performance with higher stability margins. The effectiveness of the proposed FLL is confirmed through experimental results and comparison with advanced type-2 PLLs.

An Efficient Implementation of Generalized Delayed Signal Cancellation PLL

The phase, frequency, and amplitude of the fundamental-frequency positive-sequence component of the grid voltage are crucial information in control of most grid-connected power electronic based equipment. Often, a standard phase-locked loop (PLL) with a prefiltering stage is employed for the extraction of this information. Inspired by the concept of delayed signal cancellation (DSC), the generalized DSC (GDSC) operator has recently been introduced as an interesting option for the PLL prefiltering stage. In its typical structure, the GDSC operator extracts the grid fundamental component and feeds it to a conventional synchronous reference frame PLL (SRF-PLL). The frequency estimated by the SRF-PLL is then fed back to the GDSC operator to make it frequency adaptive. This structure, however, suffers from two main drawbacks: 1) the system is highly nonlinear, and therefore, it is difficult to ensure its stability under all circumstances; and 2) adapting the GDSC to grid frequency variations increases the implementation complexity and computational effort, particularly when the interpolation techniques are used for this purpose. To avoid these problems while maintaining high accuracy in the extraction of grid voltage quantities, an efficient and low-cost implementation of the GDSC-PLL is suggested in this paper. The proposed structure, which is called the enhanced GDSC-PLL (EGDSC-PLL), uses a nonadaptive GDSC operator as its prefiltering stage and corrects the phase-shift and amplitude scaling caused by this operator by using two units, called the phase-error compensator and amplitude-error compensator. The effectiveness of the EGDSC-PLL is confirmed through simulation and experimental results.

A Three-Phase PLL Algorithm Based on Signal Reforming Under Distorted Grid Conditions

This paper proposes a novel three-phase phase-locked loop (PLL) algorithm, which focuses on the reforming of the primary signals before grid synchronization rather than improving the phase estimation methodologies. The unbalanced signals are reformed to balanced ones without damage to the phase angle, through which the negative sequence of the grid voltages is removed. This eliminates the estimation errors of conventional synchronous reference frame PLL and enhances its response speed with a higher bandwidth. The reforming process is supposed to be carried out at every zero-crossing point of the three-phase voltages and choose one phase as reference to balance the other two. Coefficients for the signal reforming are calculated at one zero-crossing point and updated until the next comes. In implementation, a certain phase is chosen as the reference all along and the reforming process will be suspended when it just crosses the zero line. This PLL algorithm has a fast and precise character to reform the three-phase grid voltages and is flexible for application. Under heavily distorted grid conditions, it can still perform effectively even with multiple zero-crossings. Comprehensive experimental results from a digital signal processor-based laboratory prototype are provided to validate the performance of this PLL algorithm.

Conventional Synchronous Reference Frame Phase-Locked Loop is an Adaptive Complex Filter

Despite the wide acceptance and use of the conventional synchronous reference frame phase-locked loop (SRF-PLL), no transfer function describing its actual input-output relationship has been developed so far. Arguably, the absence of such transfer function has hampered the application of SRF-PLL as a filter or controller inside the closed-loop control systems. In this paper, the transfer function describing the actual input-output relationship of the conventional SRF-PLL is presented. Using this transfer function, it is shown that the conventional SRF-PLL is a first-order adaptive complex bandpass filter. The accuracy of this transfer function is confirmed through numerical results.

Three-phase grid voltage synchronization using sinusoidal amplitude integrator in synchronous reference frame

Abstract Synchronization with the grid voltage is critical in the control of grid-connected power converters. Under unbalanced grid condition, the conventional synchronous reference frame phase-locked loop (SRF-PLL) does not work well due to the effect of the fundamental negative sequence component. This paper proposes a new synchronization method, the sinusoidal amplitude integrator based phase locked loop (SAI-based PLL), to efficiently eradicate the effect of the fundamental negative sequence component. As a result, it can accurately and quickly estimate the amplitude and phase angle of the fundamental components of grid voltages in unbalanced grid conditions. In addition, when dc offset and harmonics are contained in the grid voltage, a multi-SAI-based PLL method is developed to extract the synchronization signal. The proposed SAI-based PLL incorporates the sinusoidal amplitude integrator into the conventional SRF-PLL. Its operation is analyzed using the complex-vector notation. Simulation and experimental results on the performance of the proposed SAI-based PLL and comparison with other synchronization methods are presented.

A Novel Grid Synchronization PLL Method Based on Adaptive Low-Pass Notch Filter for Grid-Connected PCS

The amount of distributed energy resources (DERs) has increased constantly worldwide. The power ratings of DERs have become considerably high, as required by the new grid code requirement. To follow the grid code and optimize the function of grid-connected inverters based on DERs, a phase-locked loop (PLL) is essential for detecting the grid phase angle accurately when the grid voltage is polluted by harmonics and imbalance. This paper proposes a novel low-pass notch filter PLL (LPN-PLL) control strategy to synchronize with the true phase angle of the grid instead of using a conventional synchronous reference frame PLL (SRF-PLL), which requires a d-q-axis transformation of three-phase voltage and a proportional-integral controller. The proposed LPN-PLL is an upgraded version of the PLL method using the fast Fourier transform concept (FFT-PLL) which is robust to the harmonics and imbalance of the grid voltage. The proposed PLL algorithm was compared with conventional SRF-PLL and FFT-PLL and was implemented digitally using a digital signal processor TMS320F28335. A 10-kW three-phase grid-connected inverter was set, and a verification experiment was performed, showing the high performance and robustness of the proposal under low-voltage ride-through operation.

Advantages and Challenges of a Type-3 PLL

A phase-locked loop (PLL) is a closed-loop feedback control system, which synchronizes its output signal in frequency as well as in phase with an input signal. The phase detector, the loop filter, and the voltage controlled oscillator are the key parts of almost all PLLs. Within the areas of power electronics and power systems, which are focused on in this paper, the PLLs typically employ a proportional-integral controller as the loop filter, resulting in a type-2 control system (a control system of type-N has N poles at the origin in its open-loop transfer function). Recently, some attempts have been made to design type-3 PLLs, either by employing a specific second-order controller as the loop filter, or by implementing two parallel tracking paths for the PLL. For this type of PLLs, however, the advantages and limitations are not clear at all, as the results reported in different literature are contradictory, and there is no detailed knowledge about their stability and dynamic characteristics. In this paper, different approaches to realize a type-3 PLL are examined first. Then, a detailed study of dynamics and analysis of stability, followed by comprehensive parameters design guidelines for a typical type-3 PLL are presented. Finally, to get insight into the advantages/limitations of this type of PLLs, the performance of a well-tuned type-3 PLL is compared with a conventional synchronous reference frame PLL (which is a type-2 PLL) through extensive experimental results and some theoretical discussions.

An Adaptive Control System for Three-Phase Photovoltaic Inverters Working in a Polluted and Variable Frequency Electric Grid

The proportional + resonant (PR) controller has been proposed in the past as a suitable method to control the current generated by the grid-connected photovoltaic voltage source inverters. Due to the fact that information regarding the frequency of the grid is needed to use this control technique, the synchronous reference frame phase-locked loop (SRF-PLL) is commonly used. To assure that the total harmonic distortion of the injected current (THDi) meets the appropriate standards, even if the grid voltage is polluted and its frequency varies, an adaptive control strategy is presented in this paper. This control strategy can improve the behavior of both, the conventional SRF-PLL and the conventional PR controller, when they are used in a polluted grid with a time varying frequency. The experimental results obtained by means of a digitally controlled 10-kVA inverter, show up that the THDi of the injected current is improved when the proposed adaptive control strategy replaces the conventional one.