A Novel Type-1 Frequency-Locked Loop for Fast Detection of Frequency and Phase With Improved Stability Margins

Abstract

The synchronous reference frame phase-locked loop (SRF-PLL) is a widely used synchronization technique in power electronics and power systems applications due to its ease of implementation and robust performance. The conventional SRF-PLL is a type-2 control system due to the use of proportional-integral controller as loop filter. With higher bandwidth design, it can achieve fast detection of frequency and phase under ideal grid conditions. However, its bandwidth should be sufficiently lowered to obtain proper disturbance rejection under unbalanced and distorted grid conditions. This results in a slower detection speed. Recently, several advanced PLLs with pre/in-loop filtering stage have been proposed to improve the detection speed. A major challenge with the PLLs is how to further improve their dynamic performance without compromising the disturbance rejection capability and stability. To resolve this issue, in this paper, a novel type-1 frequency-locked loop (FLL) is proposed. The disturbance rejection capability of the proposed FLL is improved using a modified structure low-pass filter with selective harmonics filtering ability. As the proposed FLL is type-1 control system, it achieves better dynamic performance with higher stability margins. The effectiveness of the proposed FLL is confirmed through experimental results and comparison with advanced type-2 PLLs.