Conventional Soldering Method Research Articles

Heterogeneous System-In-Package (HSIP) Technology

Abstract A stitched test vehicle has been designed using molded wafer technology to characterize the assembly yield and reliability of a 4-layered topside Buildup (BU) and 4 layered bottom side BU package. In this design, the individual module uses 20 1mm square Si die elements, and one 10mmm square Si die and 8 through substrate vias (TSVs) arrayed on a 14mm square module size to produce a Reliability Test Vehicle (RTV) using Fan-out Wafer-Level (FOWL) technology. 17 individual RTV modules are molded on a 100mm wafer to create a reconstituted wafer. On the 1mm square Si die are two dog bone structures that allows for the design of a stitched net for each build layer with the embedded Si die. Therefore one can generate a stitched net between the first BU layer with the embedded Si die, the second BU layer with the embedded die layer, and so on. The layered stitched design feature, allows one to characterize the integrity of the individual BU layers during the sequential BU processing of the layers on both sides of the molded core. The TSVs allow for signal communication between the top 4 BU layers with the 4 backside BU layers. On top of each 4th layer is a ball grid array (BGA) pad on a 0.8mm pitch that can be used to stack this module using conventional soldering methods. This approach to embed die in a molded wafer and then BU layers on each side is referred to as Heterogeneous System-in-Package (HSIP) technology. Another feature to be included in this work is the use of Current Induced Thermal Cycle (CITC) testing. This is a fast and accurate test method developed by i3 Electronics in Endicott, NY to assess the reliability of vias in a BU package. It is widely used in the industry for circuit boards and build up organic substrates, and is now be applied to the finer via dimension (25um diameter) used for HSIP technology. As was discussed above for the RTV design, the same BU and TSV features will be tested in this CITC module design. The BU layers are exactly the same as that used in the above RTV design. For this wafer build, the die will be molded to create a reconstituted wafer. The first goal is to develop a molding process that has less than 20um die shift and produces a molded substrate with the acceptable amount of bow to accommodate the topside build up layers. For each BU layer, the assembly yield can be characterized by probing the stitched nets for the first, second, and so on BU layers for both sides. This data will provide assembly yield. The individual RTV and CITC modules can then be diced from the wafer, solder balls are attached to the topside BGA pads, and then tested using a conventional clam shell socket test fixture. The first set of reliability tests will be thermal cycling and temperature humidity. In this paper we will discuss the challenges with building HSIP modules, their yield and the first phase of reliability testing.

Copper‐Leaf‐Based Process for Imperceptible Computational Electronics

AbstractImperceptible electronics have a key role in tomorrow's wearable technologies. Individual elements such as ultra‐thin sensors, batteries, solar cells, and actuators are well described in literature, but there is a lack of methods to build the computing circuit itself. A new process is presented for the fabrication of flexible and imperceptible circuits that reach standards of microelectronics associated with significant integration density of components and interconnections, as well as multilayering. The stack uses a commercialized decorative copper leaf with a thickness of 450 nm as the conductive layer and a parylene substrate of a few micrometers. The copper leaf shows both high compliance and conductivity of bulk copper (5.96 × 107 S m−1), with electrical resistance stable over 5000 cycles of complete folding. The process requires stencil‐free laser patterning that reaches fine‐pitch integration, conventional soldering methods, and a three‐step via fabrication and assembly process for multilayered circuits. The functionality of an ultra‐thin, multilayered, lightweight, electrocardiogram‐monitoring device is demonstrated. This allows for direct transfer of microelectronic designs for rapid prototyping from rigid board to imperceptible electronics.

The interfacial Cu–Sn intermetallic compounds (IMCs) growth behavior of Cu/Sn/Cu sandwich structure via induction heating method

Forming full IMC solder joint technology has become one of the leading candidates to replace conventional high temperature Pb-based solder for wide bandgap (WBG) power modules (SiC and GaN) due to its excellent thermo-stability and high electrical/thermal conductivity. Few studies were investigated the formation and growth mechanism of interfacial Cu–Sn IMCs layer of Cu/Sn(10 μm)/Cu system during induction heating method. The results showed that the growth behavior of Cu–Sn IMCs of the Cu/Sn interface by induction heating method was different from Cu–Sn IMCs growth behavior of the Cu/Sn interface by conventional soldering method. The Cu6Sn5 thickness increased by Cu/Sn solid–liquid interfacial reaction before the bonding time of 45 s and then decreased by Cu6Sn5/Cu solid–solid interfacial reaction within the bonding time of 60 s. The Cu3Sn thickness increased by solid Cu/liquid Sn interfacial reaction and solid Cu6Sn5/solid Cu interfacial reaction within the bonding time of 60 s. A formation mechanism model of Cu–Sn compounds was also presented. The mathematic model of Cu layer consumption at different temperature was also illustrated, which indicated that higher temperature is in favor of the consumption of Cu layer. By knowing the relationship between the thickness of Cu layer on SiC power device at different temperature could be designed when evaluating the reliability of device by induction heating process.

Thermomechanical-stress-free interconnection of solar cells using a liquid metal

Research efforts to overwhelmingly fortify the economics of photovoltaics have focused on increasing the light-to-electricity conversion efficiency and reducing the overall manufacturing costs. Since lowering the consumption of silicon has the potential to greatly curtail the material costs, studies on wafering thin silicon substrates have been performed. However, current methods to interconnect solar cells with metal ribbons are not sufficient to employ thin silicon wafers. Therefore, this study explores a novel route to interconnect solar cells with metal ribbons without thermomechanical stress using a highly conductive liquid metal. Galinstan, which is notoriously difficult to print, is successfully harnessed to be printable by suspending submillimetre-sized Galinstan droplets in the carrier vehicle, as aided by the yield stress. By mechanically sintering the Galinstan paste with gentle mechanical pressure, solar cells are interconnected with metal ribbons at room temperature. Albeit the averaged maximum power of the unit modules interconnected using the Galinstan paste was significantly degraded after just 100 thermal cycles due to the possible formation of resistive intermetallic compounds of Galinstan, the power degradation of the best unit module using the Galinstan paste is −0.9%, which is smaller than the averaged one of the unit modules using a conventional soldering method (-1.35%), implying the thermomechanical-stress-free interconnection method using a liquid metal has a chance to be improved for being a comparable competitor to the conventional soldering method.

Axial Tension and Overcurrent Study on a Type of Mass-Producible Joint for ReBCO Coated Conductors

Given the limited length of ReBCO coated conductors (CCs), a large number of joints is necessary in high-temperature superconducting (HTS) applications. The quality of joints largely determines the stability of the HTS applications, because joints are usually weaker than ReBCO CCs themselves concerning mechanical and electrical characteristics. To address this problem, a novel type of CC joint, which employs a fabrication process similar to CC lamination, is developed (named after “lamination joint” for convenience). In this paper, the behaviors of the lamination joints under axial tension loads and dc/ac overcurrent are investigated. Single fully laminated CCs and joints fabricated by a conventional soldering method are also studied for comparison. The lamination joints exhibit similar critical axial tensile forces (around 700 N) to the single fully laminated CCs, which are much larger than that of the conventional soldering joints. Moreover, overcurrent tests show that the lamination joints have smaller possibilities to burn out than the single fully laminated CCs. Moreover, the lamination joints are much more stable in quality and are mass producible since they are automatically fabricated by a lamination system. Furthermore, a joint resistance of several <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{n}\Omega$</tex-math></inline-formula> can be achieved by simply extending the splicing length to several meters.

Novel Technique for Precision Soldering Based on Laser-Activated Gold Nanoparticles

This paper introduces a novel technique for repairing defective soldering joints in densely packed printed circuit boards and multichip modules. The new technique is not based on conventional soldering methods or tools, but rather on the remarkable properties of gold nanoparticles. Gold nanoparticles are deposited on the surface of the solder pad or joint that must be reworked, and a low-power laser with a wavelength in the range of 500–800 nm is directed to the area where the gold nanoparticles are present. The nanoparticles absorb the electromagnetic radiation at such wavelengths very effectively, and intense surface plasmons are generated in the nanoparticles. The surface plasmons cause the nanoparticles to heat up, where the temperature can reach several hundred degrees of Celsius. This in turn causes the solder that is in contact with the nanoparticles to melt, while other solder joints in the vicinity remain unaffected. The narrow wavelength range of 540–572 was determined to be the optimal range of wavelengths for the present application.

Direct Soldering of Electronic Components on Molded Devices

Using the great potential of the three–dimensional Molded Interconnect Devices (3–D MID) necessitates the adaption of the conventional soldering methods in electronic assembly. The different characteristics of the soldering technologies determine the suitability of various engineering thermoplastics as substrate material. So several investigations on application of different thermoplastic materials have been carried out. Furthermore the geometric design of the molded carriers and the impact on the temperature distribution on the board during the soldering process will be discussed and the possibilities and the limitations of conventional soldering equipment will be shown.

A technique for fabricating wrought wire clasps with metal rest by the room temperature casting method. Part 1: Evaluation of mechanical properties

The purpose of this study was to establish an effective connecting method between wrought wire clasps and cast rests.In this study, straight Co-Cr alloy wire samples connected by three different methods were evaluated with the tensile test and the bending test. The first method was the hightemperature (800°C) fusing method with Co-Cr alloy, the second one was the conventional soldering method using Ag alloy and the third was the newly developed room temperature fusing method using Co-Cr alloy.Following results were obtained:1) On room temperature fused samples about 80% of original wire strength were measured, while values of other were relatively small.2) The deflection under the unit bending load was slightly smaller in room temperature fused samples and slightly larger in soldered samples than original clasp wires. High-temperature fused samples did not endure the bending stress and broke easily.3) Mechanical properties of wrought wires hardly changed in the process of the room temperature fusing method.From above mentioned results, the newly developed room temperature fusing method have great potentialities for clinical usage.