Conventional Semiconductor Processing Research Articles

Hybrid nanofabrication processes utilizing diblock copolymer nanotemplate prepared by self-assembled monolayer based surface neutralization

Nanostructures including nanohole and metal dot arrays were fabricated by hybrid processes combing self-assembled diblock copolymer and conventional semiconductor processes. The interfacial energy between polystyrene-b-polymethylmetacrylate (PS-b-PMMA) diblock copolymer and substrate surface was controlled by employing a self-assembled monolayer (SAM), resulting in a polymer template with well-ordered cylindrical nanohole array. The nanohole sizes were controlled within 10 to 22 nm in diameter using block copolymers with different molecular weights. The PS nanotemplates were fabricated on various substrates, including oxides, nitrides, and poly-Si. Nanohole pattern was transferred by dry etching process, producing inorganic nanohole templates. Also, gold nanodot arrays with diameter smaller than 10 nm were fabricated through lift off process.

Alternative Substrates

To assess the future prospects of displays on alternative substrates one need to consider that the active electronics required to address large displays is never fabricated on the substrate but always on an deposited film. The compatibility of this inorganic film with the substrate, in particular thermal expansion, is poor for polymers, but excellent for flexible glass. The paper describes method to process flexible glass with conventional semiconductor processing equipment, and reports on results obtained to date in fabricating poly-Si TFTs on Corning Inc 00 Microsheet.

Single chip interdigitated electrode capacitive chemical sensor arrays

In this paper the design considerations, fabrication and first evaluation results of a capacitive type single chip chemical sensor array based on interdigitated electrode structure is presented. The electrode arrays have been fabricated with conventional semiconductor processes. The final structure consists of four interdigital capacitive sensors each one coated with a different polymer sensitive film by using only successive lithographic steps. The array sensors have good response to controlled concentrations of volatile organic compounds (∼35fF, ∼7fF, ∼12fF for the PHEMA covered sensor when exposed to 100 ppm of water, methanol and ethanol vapors and ∼2.5fF, in the case of 100 ppm of toluene vapors for the PDMS covered sensor).

Integration of lead zirconium titanate thin films for high density ferroelectric random access memory

Interests are being focused on types of nonvolatile memories such as ferroelectric random access memory (FRAM), phase change random access memory, or magnetoresistance random access memory due to their distinct memory properties such as excellent write performance which conventional nonvolatile memories do not possess. Among these types of nonvolatile memories, FRAM whose cell structure and operation are almost identical to dynamic random access memory (DRAM) can ideally realize cell size and speed of DRAM. Thus FRAM is the most appropriate candidate for future universal memory where all memory functions are performed with a single chip solution. Due to the poor ferroelectric properties of downscaled ultrathin lead zirconium titanate (PZT) capacitors as well as technical issues such as hydrogen and plasma related degradation arising from embedding ferroelectric metal-insulator-metal capacitors into conventional complementary metal oxide semiconductor processes, current FRAM still falls far below its ideally attainable cell size and performance. In this paper, based upon PZT capacitor, current mass-productive one pass transistor and one storage capacitor (1T1C), capacitor over bit line (COB) cell technologies are introduced upon which cell size of 0.937μm2 at 250nm minimum feature size technology node has been realized. And then, most recent 1T1C, COB cell technologies are discussed from which cell size of 0.27μm2 at 150nm minimum feature size technology node has been realized, and finally future three dimensional capacitor technologies for the FRAM with cell size of less than 0.08μm2 beyond 100nm minimum feature size technology node are suggested.

Fabrication of subwavelength structure for improvement in light-extraction efficiency of light-emitting devices using a self-assembled pattern of block copolymer

A new fabrication method to improve the optical extraction efficiency of light-emitting devices is presented. The morphology of a self-assembled block copolymer was transferred to the surface of a compound semiconductor to achieve a subwavelength columnar structure. The optical extraction efficiency of the substrates with subwavelength columnar structures of 350 nm pillar height, 130 nm diameter, and 180 nm pitch, improved 2.2 times compared to unprocessed substrates. This method does not require expensive exposure lithography tools and is therefore suitable for conventional semiconductor processes.

Modification of a CMOS microelectrode array for a bioimpedance imaging system

A complete microsensor array with integrated circuitry, fabricated using a conventional complementary metal oxide semiconductor (CMOS) process is presented. This sensor array is the first step towards a system-on-chip design intended for making cellular impedance measurements in a tissue culture. The microelectrodes that make up the sensor array were passivated using a modified electroless gold plating process. The process plates a layer of gold onto the native aluminium electrodes so that they are suitable for performing the cellular impedance measurement experiment. Successful trials were achieved from the plating process with uniform plating coverage over all the exposed aluminium surfaces.

Wafer-Scale Fabrication of Polymer-Based Microdevices via Injection Molding and Photolithographic Micropatterning Protocols

Because of their broad applications in biomedical analysis, integrated, polymer-based microdevices incorporating micropatterned metallic and insulating layers are significant in contemporary research. In this study, micropatterns for temperature sensing and microelectrode sets for electroanalysis have been implemented on an injection-molded thin polymer membrane by employing conventional semiconductor processing techniques (i.e., standard photolithographic methods). Cyclic olefin copolymer (COC) is chosen as the polymer substrate because of its high chemical and thermal stability. A COC 5-in. wafer (1-mm thickness) is manufactured using an injection molding method, in which polymer membranes (approximately 130 microm thick and 3 mm x 6 mm in area) are implemented simultaneously in order to reduce local thermal mass around micropatterned heaters and temperature sensors. The highly polished surface (approximately 4 nm within 40 microm x 40 microm area) of the fabricated COC wafer as well as its good resistance to typical process chemicals makes it possible to use the standard photolithographic and etching protocols on the COC wafer. Gold micropatterns with a minimum 5-microm line width are fabricated for making microheaters, temperature sensors, and microelectrodes. An insulating layer of aluminum oxide (Al2O3) is prepared at a COC-endurable low temperature (approximately 120 degrees C) by using atomic layer deposition and micropatterning for the electrode contacts. The fabricated microdevice for heating and temperature sensing shows improved performance of thermal isolation, and microelectrodes display good electrochemical performances for electrochemical sensors. Thus, this novel 5-in. wafer-level microfabrication method is a simple and cost-effective protocol to prepare polymer substrate and demonstrates good potential for application to highly integrated and miniaturized biomedical devices.

Detailed Kinetic Modeling of Silicon Nanoparticle Formation Chemistry via Automated Mechanism Generation

Thermal decomposition of silane can be used to produce silicon nanoparticles, which have attracted great interest in recent years because of their novel optical and electronic properties. However, these silicon nanoparticles are also an important source of particulate contamination leading to yield loss in conventional semiconductor processing. In both cases, a fundamental knowledge of the reaction kinetics of particle formation is needed to understand and control the nucleation of silicon particles. In this work, detailed kinetic modeling of silicon nanoparticle formation chemistry was carried out using automated reaction mechanism generation. Literature values, linear free-energy relationships (LFERs), and a group additivity approach were incorporated to specify the rate parameters and thermochemical properties of the species in the system. New criteria for terminating the mechanisms generated were also developed and compared, and their suitability for handling an unbounded system was evaluated. Four different reaction conditions were analyzed, and the models predicted that the critical particle sizes were Si5 for an initial H2/SiH4 molar ratio of 90:10 at 1023 K and Si4 for the same initial composition at 1200 K. For an initial H2/SiH4 molar ratio of 99:1, the critical particle size was larger than or equal to Si7 for both temperatures, but it was not possible to determine the exact critical particle size because of limitations in computational resources. Finally, the reaction pathways leading to the formation of nanoparticles up to the critical size were analyzed, and the important species in the pathways were elucidated.

Fabrication of Triode Type Field Emission Device Using Carbon Nanotubes Synthesized by Thermal Chemical Vapor Deposition

【We report a new fabrication process for high performance triode type CNT field emitters and their superior electrical properties. The CNT-based triode-type field emitter structure was fabricated by the conventional semiconductor processes. The keys of the fabrication process are spin-on-glass coating and trim-and-leveling of the carbon nanotubes grown in trench structures by employing a chemical mechanical polishing process. They lead to strong adhesion and a uniform distance from the carbon nanotube tips to the electrode. The measured emission property of the arrays showed a remarkably uniform and high current density. The gate leakage current could be remarkably reduced by coating of thin $SiO_{2}$ insulating layer over the gate metal. The field enhancement factor( ${\beta}$ ) and emission area( ${\alpha}$ ) were calculated from the F-N plot. This process can be applicable to fabrication of high power CNT vacuum transistors with good electrical performance.】

Fabrication of capacitive micromachined ultrasonic transducers by micro-stereolitholgraphty

An ultrasonic transducer is formed by a plurality of cMUT cells, each comprising a charged diaphragm plate capacitively opposing an oppositely charged base plate. The cMUT cells can be fabricated by conventional semiconductor processes and hence integrated with ancillary transducer circuitry such as a bias charge regulator. The cMUT cells can also be fabricated by micro-stereolithography whereby the cells can be formed using a variety of polymers and other materials.

Fabrication of diffractive optical elements using the CMOS process

In this paper we propose a novel diffractive optical element (DOE) which is fabricated by the conventional complementary metal-oxide semiconductor (CMOS) process. A simple post-CMOS process is employed to establish the relief pattern. The pattern can be used directly for its optical properties or can serve as a mould for subsequent replication. In this study we design a DOE with eight-phase-level gratings, which is compatible with the CMOS process. The eight-phase-level gratings have 81.4% diffraction efficiency calculated by computational and theoretical analyses. The experiment finished four-phase-level gratings.

Fabrication of a micromachined optical modulator using the CMOSprocess

This paper presents a new micromachined optical modulator designwith electrostatic actuation fabricated by the conventional complementarymetal-oxide semiconductor (CMOS) process. The modulator is operated bythe interaction of the fixed part, stationary gratings and the movablepart, sliding gratings. The period of the gratings varies with the slideof the movable part, thereby allowing different diffraction patterns ofthe reflected light. In addition, 100% modulation in the first order canserve as an optical switch. All procedures following the CMOS processmerely require a simple post-process with maskless etching. Withdifferent profiles of the shape and sacrificial layer, two types ofmodulator are developed to obtain a high-aspect ratio and high efficiencyof modulation, respectively.

The Ferroelectric Memory and its Applications

The ferroelectric memory is not only an ideal memory with clear advantages such as non-volatility, low power consumption, high endurance and high speed writing, but is also the most suitable device for memory embedded applications. Its manufacturing process makes it more compatible with the standard CMOS process than the traditional non-volatile memory process, since it does not require high voltage operation, and the ferroelectric process does not influence the characteristics of the CMOS devices used in logic cells, analog cells and core cells. In the spreading of Intellectual Property (IP) application for the LSI Industry, this embedded application takes on a more important role. In the near future, the ferroelectric memory technology will be taken into reconfigurable devices as programmable interconnect switches besides being used as embedded memories. These ferroelectric memory based reconfigurable devices can be used as Dynamic Programmable Gate Array (DPGA), which are able to be reconfigured from their original logic in a system under an operation mode. New logic circuits will operated with lower power consumption or a resume function by introducing ferroelectric gated transistors or ferroelectric capacitors. Even though ferroelectric memory technology has many advantages, it is not popular yet, since, the conventional semiconductor process degrades the ferroelectric layer easily. The means to prevent degradation of ferroelectric films in the silicon wafer process will also be discussed.

Application of highly oriented, planar diamond (HOD) films of high mechanical strength in sensor technologies

Abstract Diamond possesses many characteristics of an ideal material for microsensors, and has indeed emerged as a promising candidate. In comparison to its competitors Si and SiC, large area diamond films are still polycrystalline and inhomogeneous in grain size and orientation. This still determines the material properties, and thus the sensor technology and device performance. However, highly oriented diamond films of high quality have been developed recently, using a modified bias enhanced nucleation method [1]. These films can be described by highly planar, textured surfaces, mirror like backsides, low internal stress and high mechanical strength. Conventional semiconductor processing schemes can now be fully implemented, allowing one to scale high performance micromechanical sensor structures into th lower micrometer range. In this paper, a novel concept based on selective area epitaxy (SAE), pulse doping, reactive ion etching, multilayer contacts and wet chemical backside patterning with micron resolution is presented. The elastic properties and the piezoresistive characteristics of boron doped diamond have both been investigated from diamond cantilever beam deflection measurements. For 15 μm thin HOD-films, a Young's modulus of approximately 830 GPa has been extracted from resonance frequency measurements and nanoindentation measurements. From this data a fracture strength of σfr=2.72 GPa is calculated. To our knowledge, these data represent the highest values reported up to now for such thin films.

High Q CMOS-compatible microwave inductors using double-metal interconnection silicon technology

The authors' aim is to demonstrate the possibility of building high quality factor (Q) integrated inductors in the conventional complementary metal-oxide semiconductor (CMOS) process without any additional processes of previous papers, such as thick gold layer or multilayer interconnection. The comparative analysis is extensively carried out to investigate the detailed variation of Q performance according to inductor shape and substrate by varying the substrate resistivity with circular and rectangular shape. The high Q of nearly 12 is achieved from the fabricated inductors with 2 μm metal thickness on the 2 k/spl Omega//spl middot/cm silicon substrate using the CMOS process.

Screen printing: a technology for the batch fabrication of integrated chemical-sensor arrays

The commercialization of integrated chemical sensor has been slowed by the difficulty of device encapsulation and membrane application. For reasons of both cost and reproducibility, the sensor-specific structures should be mass fabricated, as are the microelectronics. The challenge lies in merging the standard semiconductor process sequence with the non-standard steps used to form the transducers. We demonstrate that screen printing can be used to partition the fabrication into two distinct sequences, semiconductor processing and sensor-specific steps. This simplifies process development and evolution, and makes semiconductor foundry services available for manufacturing sensors. After conventional semiconductor processing, our wafers have silver epoxy contacts screen printed on the aluminum sensor pads; the silver forms a stable chemical interface to the membranes, and the epoxy makes a strong physical bond to them. Next, the polymeric membranes are applied and patterned with screen printing. Membranes of different compositions can be deposited on the various sites of a multisensor chip by simply repeating the screen print/cure cycle. We show that the electrochemical performance of mass-fabricated passive and active sensor arrays is comparable to that of conventional liquid-junction ion-selective electrodes.

Bipolar Transistor with a Buried Layer Formed by High-Energy Ion Implantation for Subhalf-Micron Bipolar-Complementary Metal Oxide Semiconductor LSIs

We investigated a bipolar transistor with a buried layer formed by high-energy ion implantation without the epitaxitial silicon layer growth. We focused mainly on the reduction of junction leakage current related to implantation damages, which could be achieved by rapid thermal annealing. Consequently, the maximum current gain of 155 and the cutoff frequency of 17.3 GHz were achieved with BV CE0=5.0 V. Moreover, this fabrication process is applicable to the conventional complementary metal oxide semiconductor (CMOS) process with the retrograde twin wells without additional process steps. Therefore, this technique can be very promising for the fabrication of subhalf-micron BiCMOS LSIs.

Electrical characteristics and photolytic tuning of poly(3-hexylthiophene) thin film metal–insulator–semiconductor field-effect transistors (MISFETs)

In this paper, we present results on the electrical characteristics of both thick and thin film polymer metal–insulator–semiconductor field-effect transistors (MISFETs) based on poly(3-hexylthiophene) semiconducting substrate. These MISFETs were fabricated in eight steps using conventional semiconductor processing technology. The MISFETs had excellent current–voltage characteristics and showed little degradation with time. Electrical parameters of threshold voltage, mobility, and transconductance were − 1 V, 10−4–10−5 cm2 V−1 s−1, and 10−9 S, respectively. These values are typical of π-conjugated polymer-based MISFETs. Electrical transport in MISFETs were by both bulk (or resistive) and FET-like mechanisms in the thick film transistors. The resistive current component and the electrical characteristics were found to be tunable by photolytic degradation of the semiconducting polymer. In this process, the semiconducting π-conjugated regions were spatially converted to insulating regions by novel photo-oxidative chemistry. We were also successful in modelling the MISFETs as an intrinsic FET with parasitic source and drain resistances in series with it and a varistor (for the bulk current component) in parallel with the intrinsic FET. Using this circuit model, we obtained very good agreements between SPICE simulations and the experimental results.

A simple method to prepare carbon substrates for RBS analysis

We have investigated the possibility of forming 2 μm thick low Z (carbon, Z = 6) layers on Si wafers via simple and conventional semiconductor processing techniques. These carbon substrates were prepared by spinning a layer of photoresist (Shipley AZ1350J or 1400-33) onto Si substrates and then heating at temperatures of up to 900°C. The resulting carbon layer is sufficiently thick to shift the RBS signal due to the Si to energies below that corresponding to C on the surface. As an example we show the use of these carbon film in the investigation of the SiAu system. In this paper, we present a discussion on the preparation of the carbon substrate and application of these substrates in the investigation of oxidation of the AuSi system and other systems commonly encountered in thin film investigation. The objective of this investigation is to show that very simple techniques commonly available in semiconductor laboratories can be used to fabricate carbon substrates suitable for backscattering analysis.

An aluminum/SiO2/silicon−on−sapphire light valve matrix for projection displays

A new electron−beam−addressed light valve structure has been tested which is composed of a large array of 0.002×0.002−in. 3000−Å−thick aluminized silicon dioxide electrostatically deflectable squares, suspended by a centrally located 4−5−μm−tall silicon post over a transparent sapphire substrate. The device is fabricated using conventional semiconductor processing techniques and, in particular, slits are photolithographically defined in each picture element so as to spatially separate in the schlieren stop plane the signal light produced by deflected elements from the diffraction pattern from the matrix. Experimental results include 20 lines/mm resolution, 18:1 contrast ratio, picture storage times of several months, and full erasure times of 1/30 sec.