Conventional Power Amplifier Research Articles

A low-complexity and high-frequency ASIC transceiver for an ultrasound imaging system.

This article presents a high-frequency application-specific integrated circuit (ASIC) transceiver for an ultrasound imaging system designed with a focus on low complexity. To simplify the design, it employs a conventional Class-D power amplifier structure for the transmitter (TX) and a resistive feedback transimpedance amplifier (TIA), which consists of a common-source amplifier followed by a source follower for the receiver (RX). Through careful optimization, the RX achieves a measured transimpedance gain of 90 dBΩ and an input-referred noise of 5.6 pA/√Hz at 30MHz while maintaining a wide bandwidth of up to 30MHz for both the TX and RX. The power consumption of the TX and RX is measured to be 7.767 mW and 2.5 mW, respectively. Further acoustic performance, assessed using an annular capacitive micromachined ultrasonic transducer (CMUT), showed a 1.78kPa peak pressure from a 20V pulser and confirmed the full bandwidth compatibility of the CMUT's bandwidth. The ASIC transceiver has been fabricated using a 0.18μm HV bipolar-CMOS-DMOS (BCD) process.

Electromagnetics theory-based new equation to improve harmonically tuned power amplifier theory and design

ABSTRACT Power amplifiers (PA) are used to boost the power of signals. Recently, harmonically tuned power amplifiers (HTPA) offer high efficiency and wider bandwidth than conventional PA. HTPA achieves by shaping waveforms using varying drain terminal impedance conditions (open and short-circuited etc.), but this impedance creates reflected waves at the drain. Existing HTPA methods lack a foundation in Electromagnetic Theory (EM), leading them to miss reflected waves. As a result, the existing equations show problems Type I: generate unwanted and non-required higher-order harmonics (n > 3); and Type II: they cannot link with simulated/measured results properly. This paper proposes an alternative approach by applying EM theory to develop a general HTPA equation. This equation works for any HTPA class and overcomes problems (Type I & II). To validate the proposed theory and equation, continuous mode Class F PA is designed and fabricated. Theoretical, simulation and experimental results all showed good agreement.

Study on the frequency characteristics of split-gate AlGaN/GaN HFETs

In this study, we report on the direct-current (DC) and frequency characteristics of split-gate heterostructure field-effect transistors (HFETs) with different split-gate lengths. The split-gate HFET contains two distinct operating parts, the large and the small transconductance parts. The split-gate HFET has a current cutoff frequency ([Formula: see text]) of 814[Formula: see text]MHz and a maximum oscillation frequency ([Formula: see text]) of 18.8[Formula: see text]GHz in the large transconductance part. Meanwhile, in the small transconductance part, there is a higher unilateral power gain of [Formula: see text][Formula: see text]GHz. Also, the split-gate HFET exhibits a voltage gain greater than 1 (0[Formula: see text]dB) at both DC and frequencies. Additionally, compared to the large transconductance part, the small transconductance part of the split-gate HFET presents a 53.5% reduction in DC power consumption and a larger input signal voltage range. Split-gate HFETs can be used as conventional power amplifiers in the large transconductance part and are also suitable as low-power voltage amplifiers in the small transconductance part.

Dual-Band Dual-Output Doherty Power Amplifier for Unsynchronized Time-Division Duplexing

Conventional multiband power amplifiers (PAs), when working in time-division duplex (TDD), require the transmit–receive intervals of all bands to be synchronized. This is an undesirable constraint in modern radio base stations. This article proposes a dual-output dual-band Doherty PA (DB-DPA) that enables the loading of one band to be switched on-and-off without impacting the other band in normal transmission. A thorough analysis of the proposed dual-output DB-DPA architecture is presented, and a dual-output DB-DPA prototype operating at 1.4 and 2.6GHz has been designed as a proof of concept. The large-signal measurements of the prototype DB-DPA indicate Doherty behavior at both frequencies with over 56% saturation efficiency and 45% efficiency at 6-dB power back-off (PBO). Furthermore, single-band and concurrent dual-band linearized modulated measurements, using 10-MHz new radio (NR) signals with 6-dB peak-to-average power ratio (PAPR), demonstrate the linearizability of the proposed DB-DPA and its usefulness for unsynchronized TDD applications.

Digital Signal Recovery With Transmitter Nonlinear State Tracking for Satellite Communications

This brief proposes a digital signal recovery (DSR) method to compensate the nonlinear distortion introduced by power amplifiers (PAs) under dynamic nonlinear operating states. Unlike conventional PA linearization methods that extract the nonlinearity based on the baseband I/Q PA input and output signal samples, the proposed method attempts to derive the memory polynomial (MP) model parameters based on PA operating states using a deep neural network (DNN). This method allows the receiver to achieve DSR by tracking the operating states of the PA effectively with a few telemetry data. Validation results from simulations and experiments based on a GaN PA operating at 3.5 GHz reveal that the proposed method can maintain satisfactory DSR performance in terms of adjacent channel power ratio (ACPR) and error vector magnitude (EVM) while the transmitter PA is operating with fluctuating average input/output power, supply voltage, and bias voltage. The training data size and time are further reduced by using a transfer learning (TL) approach.

High-Efficiency Broadband Class-E PAs for More Than One Octave: Analysis and Design

This article presents a solution based on continuous mode for designing broadband class-E power amplifiers (PAs), which is realized by transmission of the second-harmonic current with appropriate phase to load network of a class-E PAs. This theory allows selecting appropriate second-harmonic impedance causing part of efficiency to be sacrificed to get a bandwidth over one octave. The mathematical formulation for optimum load impedance in main harmonic, second harmonic, output power, drain efficiency (DE), and load quality factor (QL) is developed in this case. Theoretical results are compared with conventional narrowband class-E counterparts. To check the authentication of mathematical analysis and simulation results, a proof-of-concept broadband continuous-mode class-E PAs is fabricated using the CGH40025F transistor. The manufactured PAs show 43-dBm output power, with average DE 70% over the 0.6–1.8-GHz frequency range. Also, a narrowband conventional class-E PA for frequency range 1.2–1.8 GHz with the same transistor as broadband class-E PA is fabricated for better comparison. The output power and average DE of the conventional class-E PA are 42.5 dBm and 80%, respectively.

A High-Efficiency Self-Synchronous RF–DC Rectifier Based on Time-Reversal Duality for Wireless Power Transfer Applications

An RF–DC rectifier is an important part in a wireless power transfer system. Diode-based rectifiers are widely used in low-power harvesting scenarios, and for high power, a transistor based on the time-reversal duality was proposed. This paper presents a high-efficiency self-synchronous RF–DC rectifier based on a waveform-guided design method and an improved rectification model of a commercial GaN device. The main contributions of this paper are that (1) an improved transistor model with correct reverse bias is built for accurate rectifier simulation, and (2) a new design method of self-synchronous RF–DC rectifier is proposed: as soon as the operating mode of the rectifier, input power, and DC load are set, matching and coupling network can be calculated directly based on waveform-guided method, thus design and adjustment process of a conventional power amplifier (PA) due to the duality between a PA and a rectifier would no longer be required. A 5.8 GHz self-synchronous RF–DC rectifier is designed for validation, and the optimum RF–DC conversion efficiency is 68% with 12 W input power as well as 19.9 V output DC potential with 50 Ω load resistance. The proposed rectifier is suitable for high input power rectification applications of wireless power transfer.

Clipper Classes [Microwave Bytes

It was, admittedly, rather early in my own business traveling career that the then most prominent U.S. airline, Pan Am, introduced the “Clipper Class” cabin, which had a bit more room, no movies, and a more continuous supply of booze. This of course evolved into the now familiar, and much coveted, business class, the exorbitant cost of which I never cease to be amazed that companies are still willing to pay. I once suggested the above title to my publisher, for a book in which I would throw a few wrenches into conventional power amplifier (PA) waveform theory. It did not receive a very positive response, (the title itself that is, rather than the subject matter), mainly because they were all too young to remember “Clipper Class.” However, my statutory <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">double entendre</i> still stands, and I will discuss some issues that relate to, and to a significant extent modify, the “textbook” concepts of high-efficiency PA “Classes,” by taking account of the clipping process that occurs when the device voltage dips into the “knee” region of the device.

A large beam high efficiency radio frequency neutron spin flipper.

A design for a radio frequency (RF) neutron spin flipper obtained from magneto-static and neutron spin transport simulations is presented. The RF flipper constructed from this design provides a flipping probability of 0.999 or better for a beam size 6cm wide and 15cm high and a wavelength band between 0.4 and 0.6nm. Three permanent magnet guide field sections with air gaps provide a linear field gradient along the beam propagation direction over a large cross-sectional area. An RF oscillator based on coupling the resonant coil of a Hartley oscillator to the excitation coil was developed, which provides a higher current and, thereby, a larger RF amplitude, as compared to a conventional RF power amplifier. Two opaque He3 neutron spin filters were employed to measure the flipping probability of the flipper with very high precision. A spatially uniform flipping probability of 0.9995(2) or higher was measured over the large cross-sectional area neutron guide. This RF neutron spin flipper will be employed in a polychromatic beam reflectometer at the National Institute of Standards and Technology Center for Neutron Research. This design can be applied to other polarized neutron instruments or applications requiring a very high continuous flipping probability of the neutron spin for a large cross-sectional area beam.

A Novel Baseband Generation Method for Modeling RF Power Amplifiers for Bit Error Rate Computations

In this article, we present a novel method for modeling radio frequency (RF) power amplifiers (PAs). The proposed method for baseband data generation introduced in this paper, enables us to specify operational power range and bandwidth criteria of the PA, yielding a generic power amplifier model, which includes both memory effects as well as non-linearity of the PA. Further, we show that, the modeling approach is useful for bit error rate (BER) computations with PA distortions for any digitally modulated signal. Estimated BER using the proposed PA model for the test case of QPSK and 16-QAM, shows a significant difference in BER at high input back-offs due to memory effects, compared to the conventional non-linear PA models.

Unbalanced Power Amplifier: An Architecture for Broadband Back-Off Efficiency Enhancement

In this article, we present a new broadband power amplifier (PA) architecture with a back-off efficiency enhancement that supports very wide modulation bandwidths. The unbalanced PA is composed of two cooperating sub-PAs using the Lange couplers as input power splitter and output power combiner. The PA operation is controlled by the transistors' width ratio and coupling coefficients of the Lange couplers. The output power back-off (OPBO) level is given by the transistors' width ratio and coupling coefficient of the output coupler, while the maximum efficiency is achieved at the back-off point. These features provide more design flexibility compared with the conventional Doherty PA, where the OPBO can be set only by the transistors' width ratio, and the maximum efficiency is achieved at the peak power. Using broadband harmonic matching networks, the main and auxiliary sub-PAs operate in the continuous mode to improve efficiency over a broad bandwidth. A fully integrated unbalanced PA, implemented in a 250-nm GaN-on-SiC process, achieves 32.2-34.3-dBm output power, 27%-37% efficiency at peak power, and 27%-40% at 5-6-dB back-off, across 4.5-6.5 GHz. The PA provides 3.7/4.5% (-28.6/-26.9 dB) rms error vector magnitude (EVMrms) and 30% average efficiency for a 256-QAM signal with 100-/200-MHz bandwidth, 7.2-dB PAPR, and 25.5-dBm average output power, without using any predistortion.

High efficiency continuous mode RF power amplifier based on second and third harmonic manipulation

AbstractContinuous mode class-J radio-frequency (RF) power amplifier is a promising technique that extends the operating bandwidth of the conventional class-B power amplifier. However, the maximum theoretical efficiency is limited to that of the class-B power amplifier. In this paper, an enhanced mode of operation for the class-J power amplifier is proposed by incorporating a third harmonic voltage component to produce an optimum waveform for maximizing the fundamental voltage component and thereby to increase the drain efficiency and introduce a new design space. A detailed derivation for the necessary relations of output power, drain efficiency, and the required harmonic load impedances is provided, showing a significant improvement in theoretical maximum efficiency from 78.5 to 89.8%. In order to confirm the developed analytic approach, a 10 W prototype amplifier model was designed and fabricated to operate within the global system for mobile communications (GSM) frequency band 850–950 MHz using a commercial GaN power high electron mobility transistor (HEMT). The experimental results have indicated that the drain efficiency of the circuit varies from 68 to 80% within the desired band.

A Current-Injection Class-E Power Amplifier

A novel class-E power amplifier (PA) using a current-injection (CI) technique is presented in this letter. An auxiliary current source, which injects the current into the load during each turn-off period of switching transistors, is introduced into the conventional class-E PA. Without the need of impedance transforming or increasing of the supply voltage, the proposed PA provides a new method to increase the output power. The proposed circuit is fabricated in a Taiwan Semiconductor Manufacturing Company's (TSMC's) 65-nm low power (LP) CMOS process. Measurement results show that the output power of the injected circuit reaches up to 14.12 dBm with a drain efficiency of 41% at 1.8 GHz. The output power improves more than 3 dB compared to the conventional class-E PA without CI.

A Reconfigurable CMOS Inverter-based Stacked Power Amplifier with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless Communications

A reconfigurable CMOS inverter-based stacked power amplifier (PA) is proposed to extend impedance coverage, while maintaining an output power exceeding the specific power level under the worst antenna impedance mismatch conditions. The adopted process technology supports multi-threshold metal-oxide-semiconductor field-effect transistor (MOSFET) devices, and therefore, the proposed PA employs high threshold voltage (Vth) MOSFETs to increase the output voltage swing, and the output power under a given load condition. The unit cell of the last PA stage relies on a cascode inverter that is implemented by adding cascode transistors to the traditional inverter amplifier. By stacking two identical cascode inverters, and enabling one or both of them through digital switch control, the proposed PA can control the maximum output voltage swing and change the optimum load Ropt, resulting in maximum output power with peak power added efficiency (PAE). The cascode transistors mitigate breakdown issues when the upper cascode inverter stage is driven by a supply voltage of 2 × VDD, and decrease the output impedance of the PA by changing its operation mode from the saturation region to the linear region. This variable output impedance characteristic is useful in extending the impedance coverage of the proposed PA. The reconfigurable PA supports three operation modes: cascode inverter configuration (CIC), double-stacked cascode inverter configuration (DSCIC) and double-stacked inverter configuration (DSIC). These show Ropt of around 100, 50 and 25 Ω, respectively. In the simulation results, the proposed PA operating under the three configurations showed a saturated output power (Psat) of +6.1 dBm and a peak PAE of 41.1% under a 100 Ω load impedance condition, a Psat of +4.5 dBm and a peak PAE of 44.3% under a 50 Ω load impedance condition, and a Psat of +5.2 dBm and a peak PAE of 37.1% under a 25 Ω load impedance condition, respectively. Compared to conventional inverter-based PAs, the proposed design significantly extends impedance coverage, while maintaining an output power exceeding the specific power level, without sacrificing power efficiency using only hardware reconfiguration.

Design of Class D Audio Power Amplifier Suitable to Hearing Aid Devices

An amplifier is an electronic circuit that improves the strength of the signal. Using an amplifier in an audio system is essential to improve the strength of the signal. Based on different applications and specifications different types of amplifiers are used. Generally in an audio system, the input signal is amplified to a minimum required power level and then the speaker is driven by it. Conventionally, the output stage of an audio amplifier uses Class-A or Class-AB operating in a linear transfer region. The power efficiency of the Class-D amplifier has a better output efficiency compared to Class-A and Class-AB amplifiers, and its distortion is lower than that of the Class-C amplifier. This is based on a known fact that the Class D amplifier has a switching action in which the transistors are either completely on or off. As a result, the amplification is achieved with no power dissipation. Hence, the size of the amplifier can be highly reduced and a smaller heat sink is required. This paper focuses on designing a Class-D power amplifier which is suitable for hearing aid devices to deliver 500mW output power and for the THD to be less than 3%. The circuit implementation is done using UMC high voltage 0.18μm technology. This amplifier consists of three stages such as the modulation stage, the driver stage, the bridge stage, and the demodulation stage. Unfortunately, the Class-D power amplifier has inherent non-linear distortion problems, which is more significant than conventional audio power amplifiers. In this thesis, negative feedback is employed to reduce THD. Without feedback, the THD is obtained as above 3%. By employing feedback, the THD was reduced by 1.96dB. This design result is discussed and through to realization; whereupon the effectiveness of each of the implementation is evaluated.

Seamless Integration of Active Antenna With Improved Power Efficiency

Loss reduction to improve the power efficiency in active integrated antenna (AIA) is a key design drive. This paper first analyzes the loss mechanism in a convention AIA structure. A new integration scheme of a GaN power amplifier (PA) transistor with an antenna without using any output matching network (OMN) and harmonic tuning network (HTN) is then proposed to construct a seamlessly integrated AIA. This is achieved by a novel design of a slot antenna with optimized input impedance at its fundamental frequency as well as for harmonic tuning, which essentially absorbs the OMN and HTN functions in the conventional Class-F power amplifier design. By eliminating these passive networks between the transistor and the antenna, the associated insertion and mismatch losses as well as the overall circuit size are reduced. For verification, two prototypes are designed, fabricated and measured, one with the integrated design and the other with a conventional design for comparison. Both AIAs operate between 3.4 and 3.6 GHz. Experimental results show that the power-added efficiency (PAE) of the seamlessly integrated AIA is over 52% within the operating band. Compared with the conventional cascaded design of a PA and an antenna, the PAE is improved by 14.2%.

A Super-Resolution Mixed-Signal Doherty Power Amplifier for Simultaneous Linearity and Efficiency Enhancement

This article presents a mixed-signal Doherty power amplifier (MSDPA) architecture for simultaneous linearity and efficiency enhancement. The MSDPA comprises one analog power amplifier (PA) as the main PA and one binary-weighted digital PA as the auxiliary PA. The MSDPA input is a generic envelope-varying complex-modulated signal. Based on the realtime amplitude-modulated (AM) envelope, auxiliary digital PA weightings are dynamically turned-on to perform optimum Doherty load modulation for superior linearity and back-off efficiency. Moreover, quantization noise is largely suppressed by the mixed-signal Doherty operation and nonuniform quantization (NUQ), while spectral images are substantially reduced by the quasi-first-order hold (quasi-FOH) operation, which together achieves super-resolution over conventional digital PAs; this makes the MSDPA conducive to millimeter-wave (mm-Wave) or compound PA designs by obviating the need for a large effective number of bits (ENOB) on AM digital controls. As a proof of concept, a 3-bit MSDPA is implemented at 27 GHz in a 45-nm silicon-on-insulator (SOI) CMOS process. The prototype PA achieves 40.1% peak power-added efficiency (PAE), 23.3-dBm saturated output power (Psat), and 39.4% PAE for 22.4-dBm P1dB at 27 GHz in continuous-wave (CW) measurements. The PAE at 6-dB power back-off (PBO) is 33.1%, which corresponds to a 1.68× improvement over a normalized Class-B PA. With only three control bits, the MSDPA PA supports a 12-Gb/s 64-QAM signal at -24.5-dB rms error vector magnitude (EVM) and average Pout/PAE of +15.6 dBm/27.8% without digital predistortion (DPD).

Design of a high‐efficiency dual‐band class‐J/J power amplifier considering concurrent‐mode input drive

This article analyses concurrent dual-band Class-J/J power amplifiers (PAs) with simultaneous input drive at both bands. Although it is well known that the Class-J PA has the same performance regarding the efficiency compared with the conventional Class-B PA, in this article, we show that concurrent-mode efficiency of Class-J/J dual-band power amplifier is higher than the Class-B/B counterparts much closer to their single-mode efficiency. Furthermore, it has been explained that the performance of concurrent operation of dual-band PAs is highly dependent to the design space of PA load reactance at intermodulation terms. We also explore that at intermodulation frequencies the design space includes an efficiency degradation region occurring around a specific impedance, which should be avoided when designing for concurrent operation mode. The dependency of the concurrent-mode efficiency to the nonlinearity performance of the transistor output capacitance is also considered. A concurrent dual-band Class-J/J PA operating at 1.842 and 2.655 GHz bands is implemented, where the harmonic and intermodulation control networks are designed based on closed-form equations. Measured results reveal that about 60% balanced concurrent-mode efficiency can be achieved, which outperforms recently reported counterparts. At the lower and upper bands, output powers of 41 and 40.5 dBm and efficiencies of 73.5% and 71.7% are obtained, respectively.

A Compact 5 GHz Power Amplifier Using a Spiral Transformer for Enhanced Power Supply Rejection in 180-nm CMOS Technology

We present a compact 5 GHz, class A power amplifier (PA) applicable for a wireless combo-chip that supports multiple radio systems in 180 nm CMOS technology. The proposed two-stage linear PA consists of a cascode input stage with a transformer-based balun, combined with a balancing capacitor as the load, where the single-ended signal is converted into the balanced output and a second-stage, class A push–pull amplifier with another transformer-based balun, which efficiently combines the output power differentially to drive a single-ended 50 Ω load. The proposed single-ended PA with an internal balanced configuration can achieve a power supply rejection ratio of 9.5 to 65.9 dB at 0.1 to 3.5 GHz, which is around a 12 to 37 dB improvement compared to a conventional single-ended PA with the same power gain. The results show that the proposed PA has a gain of 15.5 dB, an output-referred 1 dB gain compression point of 13 dBm, an output intercept point of 22 dBm with a 5 MHz frequency offset, an output saturated power of 15.4 dBm, and a peak power-added efficiency of 15%. The implemented PA consumes a DC current of 72 mA under 1.8 V supply. The core chip size is 0.65 mm2 without pads.

Analysis of Class-DE PA Using MOSFET Devices With Non-Equally Grading Coefficient

The design and analysis of a new operation-mode of the class-DE power amplifier (PA) using two MOSFETs with the non-equal grading coefficient is introduced. The PA uses the optimum shunt capacitance for each MOSFET to achieve zero voltage switching (ZVS) condition and wide range for the load-resistance point of view. As compared with the conventional class-DE PA, this configuration has low value of the series inductance that is reduced the power dissipation. A design procedure with intuitive curves is obtained that are implemented using a different grading coefficient for two MOSFETs. These criteria prepared an effective approach regardless of the fixed shunt capacitance for achieving ZVS condition. The desired operation of the class-DE PA is guaranteed by converging of design parameters and required output power. Moreover, non-similar switches provide reduced switch power dissipations and the number of the driving circuit PA. The simulation and experiment results are approved by implementing the outlined theoretical relationships for a fabricated class-DE PA at 4-MHz switching frequency and obtained 12.1-W output power.