Conventional Master-slave Flip-flop Research Articles

Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead

In this study, a self-shut-off pulsed latch (SSPL) is proposed as sequencing elements for reducing the hold time constraint. As SSPL captures the data input after the clock edge, the large setup-time problem that exists in the master–slave flip-flop (MSFF) is eliminated. In addition, the transparency windows are closed immediately after successfully capturing the data input (self-shut-off), and the proposed SSPL is devoid of the large hold-time problem existing in conventional pulsed latches. According to the 7-nm FinFET postlayout simulation results, the sequencing timing overheads improved by 40% and 36% in SSPL, in comparison with the conventional MSFF at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {DD}} =0.4$ </tex-math></inline-formula> and 1.0 V, respectively. Furthermore, the hold time reduced by 54% and 58% in SSPL and at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {DD}} =0.4$ </tex-math></inline-formula> and 1.0 V, respectively, in comparison with the conventional pulsed latch.

Low Overhead Warning Flip-Flop Based on Charge Sharing for Timing Slack Monitoring

Timing error predictors have a strong potential to reduce the worst case timing margins by monitoring timing slack of a design. However, these timing error predictors incur substantial amount of silicon area and power which limit the overall benefits in the system level. This paper presents a low overhead warning flip-flop (FF), which predicts setup time violations. It consists of a delay buffer and a warning generator along with a conventional master-slave FF. Low overhead FF can be designed by exploiting the concept of charge sharing to implement the warning generator. As the warning generator requires only seven transistors to predict the timing violation, the proposed warning FF occupies 30% less area and consumes 27% less power compared to the state-of-the-art timing error predictors. A test chip is fabricated using the proposed FF in a 130-nm CMOS technology to verify the functionality of the proposed warning FF in dynamic voltage and frequency scaling applications. Measurement results from the test chip show that a performance improvement of 44% can be achieved at a supply voltage of 0.9 V by employing the proposed technique compared to the worst case design. For a typical chip, the power consumption can be reduced by 36% compared to the worst case design.

Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI

In this paper, we propose pulse-triggered flip-flops (pulsed-FF) and register file in 28nm Ultra-Thin-Body-and-Box Fully-Depleted-Silicon-on-Insulator (UTBB-FDSOI) technology, dedicated to ultra-wide voltage range (UWVR) operation. A pulsed-FF composed of a latch and a pulse generator offers potential power/performance/area (PPA) advantages over the conventional master-slave flip-flop. A comparative study of 6 different latch topologies, in the energy-delay (E−D) space, points out the most efficient architectures. Furthermore, we demonstrate that the tuning capability based on the wide MOSFET back biasing range available in UTBB-FDSOI allows to cover the whole (E−D) space with a single sizing. For the pulse generation, we propose a new delay generator to guarantee the robustness at ultra-low voltage (ULV), down to 0.35V. The PPA and robustness improvement of the proposed pulsed-FF are demonstrated by silicon measurements, and its tuning capabilities based on back biasing are discussed. Finally, a register file based on the proposed pulsed-FF is reported with a pulse generator (PG) sharing technique, showing 28% and 72% (@Vdd=1V) improvements in area and energy-delay product, respectively, compared to its master–slave counterpart.

Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience

As dynamic variability increases with CMOS scaling, it is essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniques for timing error resilience help recover timing margins, improving performance and/or power consumption. This paper presents TIMBER, a technique for online timing error resilience that masks timing errors by borrowing time from successive pipeline stages. TIMBER-based error masking can recover timing margins without instruction replay or roll-back support. Three sequential circuit elements are described: TIMBER flip-flop, dedicated TIMBER flip-flop, and TIMBER latch. The TIMBER flip-flop uses two master latches and one slave latch to mask timing errors by borrowing discrete units of time from successive pipeline stages. It can be simplified to a dedicated TIMBER flip-flop that uses only two latches for time-borrowing (TB) at the expense of the flexibility of configuration as a conventional master-slave flip-flop. The TIMBER latch masks timing errors through continuous time-borrowing from successive pipeline stages, and supports runtime configuration as a conventional master-slave flip-flop. The TIMBER latch's continuous time-borrowing capability provides better time-borrowing capabilities at lower hardware cost, but the TIMBER flip-flop's discrete time-borrowing capability preserves the edge triggering property of a flip-flop, thus blocking the propagation of glitches and spurious transitions. In addition to evaluating the overhead and tradeoffs of TIMBER-based error masking on an industrial processor, the three circuits were also prototyped on an FPGA and their timing error masking capability was validated using a two-stage pipeline test structure.

SEU Hardened Flip-Flop Based on Dynamic Logic

A conventional master-slave flip-flop is very sensitive to particle strike that causes an SEU. When the clock is high, an SEU may upset the logic state of the master latch resulting in a faulty output of this flip-flop, and the erroneous value will also be locked in the slave latch when clock is low. When the clock is low, an SEU may also upset the logic state of the slave latch, resulting in a faulty output of this flip-flop. This paper presents an SEU hardened flip-flop that can mitigate SEU using an error detection circuit and a multiplexer. When the clock is high or low, an SEU in the master or slave latch of a flip-flop can be detected by the error detection circuit using dynamic logic. The multiplexer selects a correct output according to the error indication signal. The proposed flip-flop has small area, power and delay overheads and good radiation hardening capabilities.