Conventional K-best Algorithm Research Articles

VLSI Implementation of a Fully-Pipelined K-Best MIMO Detector with Successive Interference Cancellation

Multiple-input multiple-output (MIMO) technology is envisaged to play an important role in future wireless communications. To this end, novel algorithms and architectures are required to implement high-throughput MIMO communications at low power consumption. In this paper, we present the hardware implementation of a modified K-best algorithm combining conventional K-best detection and low-complexity successive interference cancellation at different levels of the tree search. The detector is implemented using a fully-pipelined architecture, which detects one symbol vector per clock cycle. To reduce the power consumption of the entire receiver unit, costly symbol-rate operations such as multiplication are eliminated both within and outside the detector without any impact on the performance. The hardware implementation of the modified K-best algorithm achieves area and power reductions of 16% and 38%, respectively, compared with the conventional K-best algorithm implementation, while incurring a signal-to-noise ratio penalty of 0.3 dB at the target bit error rate. Post-synthesis analysis shows that the detector achieves a throughput of 3.29 Gbps at a clock frequency of 137 MHz with a power consumption of 357 mW using a 65-nm CMOS process, which compares favourably with the state-of-the-art implementations in the literature.

Design and Implementation of Power-Efficient K-Best MIMO Detector for Configurable Antennas

In this brief, a power-efficient multiple-input multiple-output (MIMO) detector that can flexibly support multiple antenna configurations and modulations is presented. This detector uses a sorting-free K-best algorithm named distributed K-best (DKB) algorithm and successive interference cancellation (SIC) to decrease computational complexity. The DKB and SIC schemes are designed as several elementary building blocks. Then, the antenna configurable architecture can be flexibly constructed by these elementary blocks. The multistage hardware architecture is proposed to achieve that only K clock cycles are required to find out the best K candidates, and the sorting circuit for the conventional K-best algorithm is avoided in our design. In addition, a shift multiplier which simply uses bit shift and additions is applied to replace the conventional multiplier for further reducing power consumption. The proposed configurable MIMO detector has been fabricated in 90-nm CMOS technology with core area of 0.7744 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . For 8 × 8, 64-QAM, and K = 10 configuration, the proposed chip achieves 489-Mb/s throughput rate with 17-mW power consumption at 102-MHz operating frequency and 1 V supply voltage. The performance results show that the proposed design has better power efficiency and antenna configurability than other related works.

A Parallel Early-Pruned K-Best MIMO Signal Detector Up to 1.9Gb/s

Multiple inputs multiple outputs orthogonal frequency division multiplexing (MIMO-OFDM) technology is regarded as a promising solution to offer ultra-high data rate in wireless communications. This paper presents a field-programmable gate array (FPGA) implementation of an early-pruned K-Best detection algorithm applicable to ultra-high data throughput MIMO-OFDM communication systems. The algorithm simplifies the computation significantly compared to conventional K-Best algorithm with negligible bit error ratio (BER) degradation. A fully parallel structure is implemented on a FPGA platform, which achieves 1.9Gb/s detection throughput and is about three times over previous implementation. Moreover, a pre-processing method is realized to reduce the number of multipliers inside the detector and shrinks the critical path delay down to 8.32 ns. Together with candidate sharing and early-pruning architecture to further save the hardware cost, a high-speed, compact MIMO signal detector is demonstrated.