Design and Implementation of Power-Efficient K-Best MIMO Detector for Configurable Antennas

Abstract

In this brief, a power-efficient multiple-input multiple-output (MIMO) detector that can flexibly support multiple antenna configurations and modulations is presented. This detector uses a sorting-free K-best algorithm named distributed K-best (DKB) algorithm and successive interference cancellation (SIC) to decrease computational complexity. The DKB and SIC schemes are designed as several elementary building blocks. Then, the antenna configurable architecture can be flexibly constructed by these elementary blocks. The multistage hardware architecture is proposed to achieve that only K clock cycles are required to find out the best K candidates, and the sorting circuit for the conventional K-best algorithm is avoided in our design. In addition, a shift multiplier which simply uses bit shift and additions is applied to replace the conventional multiplier for further reducing power consumption. The proposed configurable MIMO detector has been fabricated in 90-nm CMOS technology with core area of 0.7744 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . For 8 × 8, 64-QAM, and K = 10 configuration, the proposed chip achieves 489-Mb/s throughput rate with 17-mW power consumption at 102-MHz operating frequency and 1 V supply voltage. The performance results show that the proposed design has better power efficiency and antenna configurability than other related works.