Conventional Integrated Circuit Research Articles

Recent Progress in Nanophotonic Light Sources

It is increasingly crucial in the information era to rapidly transmit and process vast quantities of data. However, conventional electronic integrated circuits that operate at rates below 10 GHz encounter significant challenges in effectively managing parallel signals. How can information be transmitted more quickly? Photonic integrated circuits (PICs) are the solution. PICs have the capability of processing multiple signals in parallel on a single optical waveguide by multiplexing wavelength, polarization, and angular momentum. This enables PICs to transmit at speeds exceeding 100 GHz, showing the potential to increase processing speeds while simultaneously reducing power levels. Nevertheless, one drawback of photonic devices is that they are typically several orders of magnitude larger than electronic devices. Consequently, nanophotonics researchers have been working to make photonic devices smaller without compromising their ability to control light. Advances in nanoscale light sources can present a viable solution to overcome these obstacles. With the formation of long-lasting, spatially confined resonances in nanocavities, it is possible to precisely manipulate far-field radiation. In this article, we provide an overview of the recent achievements in nanophotonic light sources, including topological nanolasers and single-photon emitters.

Fabrication of high aspect ratio, non-line-of-sight vias in silicon carbide by a two-photon absorption method

The future of Moore’s Law for high-performance integrated circuits (ICs) is going to be driven more by advanced packaging and three-dimensional (3D) integration than by simply decreasing transistor size. 3D ICs offer low-power consumption, high-performance and a smaller footprint compared to conventional 2D ICs. The key enabling technology to 3D integration is the interposer that provides interconnects to route signals between the chiplets that comprise the IC. However, the fabrication of high-aspect ratio through wafer vias (TWVs), that provide electrical and mechanical connection between chiplets on the top and bottom of the interposer, is one of the important challenges that limit interposer performance. Current fabrication technologies are limited by tapering effects and the need for direct line of sight to the fabrication surface. These limit the possible aspect ratios of vias and require large, complicated surface traces to connect the vias to the chiplets. Here, we demonstrate the fabrication of high-aspect ratio, non-line-of-sight TWVs in silicon carbide (SiC). SiC provides better mechanical, chemical, and thermal performance than silicon (Si). The technique uses an electro-chemical etch process that utilizes two-photon absorption to create any arbitrary 3D structure in SiC allowing for direct, subsurface routing between chiplets.

Ultra-Strong Comprehensive Radiation Effect Tolerance in Carbon Nanotube Electronics.

Carbon nanotube (CNT) field-effect transistors (FETs) have been considered ideal building blocks for radiation-hard integrated circuits (ICs), the demand for which is exponentially growing, especially in outer space exploration and the nuclear industry. Many studies on the radiation tolerance of CNT-based electronics have focused on the total ionizing dose (TID) effect, while few works have considered the single event effects (SEEs) and displacement damage (DD) effect, which are more difficult to measure but may be more important in practical applications. Measurements of the SEEs and DD effect of CNT FETs and ICs are first executed and then presented a comprehensive radiation effect analysis of CNT electronics. The CNT ICs without special irradiation reinforcement technology exhibit a comprehensive radiation tolerance, including a 1×104 MeVcm2 mg-1 level of the laser-equivalent threshold linear energy transfer (LET) for SEEs, 2.8×1013 MeV g-1 for DD and 2 Mrad (Si) for TID, which are at least four times higher than those in conventional radiation-hardened ICs. The ultrahigh intrinsic comprehensive radiation tolerance will promote the applications of CNT ICs in high-energy solar and cosmic radiation environments.

Printed Memtransistor Utilizing a Hybrid Perovskite/Organic Heterojunction Channel.

Neuromorphic computing has the potential to address the inherent limitations of conventional integrated circuit technology, ranging from perception, pattern recognition, to memory and decision-making ( Acc. Chem. Res. 2019, 52 (4), 964-974) ( Nature 2004, 431 (7010), 796-803) ( Nat. Nanotechnol. 2013, 8 (1), 13-24). Despite their low power consumption ( Nano Lett. 2016, 16 (11), 6724-6732), traditional two-terminal memristors can perform only a single function while lacking heterosynaptic plasticity ( Nanotechnology 2013, 24 (38), 382001). Inspired by the unconditioned reflex, multiterminal memristive transistors (memtransistor) were developed to realize complex functions, such as multiterminal modulation and heterosynaptic plasticity ( Nature 2018, 554, (7693), 500-504). Here we combine a hybrid metal halide perovskite with an organic conjugated polymer to form heterojunction transistors that are responsive to both electrical and optical stimuli. We show that the synergistic effects of photoinduced ion migration in the perovskite and electronic transport in the polymer layers can be exploited to realize memristive functions. The device combines reversible, nonvolatile conductance modulation with large switching current ratios, high endurance, and long retention times. Using in situ scanning Kelvin probe microscopy and variable-temperature charge transport measurement, we correlate the collective effects of bias-induced and photoinduced ion migration with the heterosynaptic behavior observed in this hybrid memtransistor. The hybrid heterojunction channel concept is expected to be applicable to other material combinations making it a promising platform for deployment in innovative neuromorphic devices of the future.

Systematic Control of Negative Transconductance in Organic Heterojunction Transistor for High-Performance, Low-Power Flexible Ternary Logic Circuits.

Organic multi-valued logic (MVL) circuits can substantially improve the data processing efficiency in highly advanced wearable electronics. Organic ternary logic circuits can be implemented by utilizing the negative transconductance (NTC) of heterojunction transistors (H-TRs). To achieve high-performance organic ternary logic circuits, the range of NTC in H-TRs must be optimized in advance to ensure the well-defined intermediate logic state in ternary logic inverters (T-inverters). Herein, a simple and efficient strategy, which enables the systematic control of the range and position of NTC in H-TRs is presented. Each thickness of p-/n-type semiconductor in H-TRs is adjusted to control the channel conductivity. Furthermore, asymmetric source/drain (S/D) electrode structure is newly developed for H-TRs, which can adjust the amount of hole and electron injection, independently. Based on the semiconductor thickness variation and asymmetric S/D electrodes, the T-inverter exhibits full-swing operation with three distinguishable logic states, resulting in unprecedentedly high static noise margin (≈48% of the ideal value). Moreover, a flexible T-inverter with an ultrathin polymer dielectric is demonstrated, whose operating voltage is less than 8V. The proposed strategy is fully compatible with the conventional integrated circuit design, which is highly desirable for broad applicability and scalability for various types of T-inverter production.

R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction

In this paper, a novel RRAM-based reconfigurable accelerator (R-accelerator) design is proposed, which makes special use of existing RRAM device for high-efficient reconfigurable application-specific computing. The proposed R-accelerator design consists of RRAM-based arithmetic unit (AU) array, fully integrated into commercial EDA design tools. A significant area saving is achieved compared with conventional digital counterpart due to the proposed logic contraction technique, as well as saving of storage space and routing congestions. For enabling the optimization of the AU array, this paper also proposes a systematical method on the synthesis of the AU array under routing channel constraint for application-specific designs. Two automatic mapping algorithms, including simultaneous mapping and incremental mapping algorithms, are proposed and compared. The experiments using 45-nm CMOS technology on a case study of dynamic time warping example and general benchmark programs show up to 49% area reduction and 28% performance enhancement using the proposed R-accelerator technique compared with conventional application-specified integrated circuit (ASIC) design.

Exploring the 3-D Integrability of Perpendicular Nanomagnet Logic Technology

Conventional integrated circuits’ design uses one layer to place logic gates and many additional layers to route interconnections. This design technique is built around the constraints of MOSFET transistors. To further improve the performance of integrated circuits, it is necessary to go beyond this limitation and to design true 3-D circuits. Although this possibility is difficult to implement with transistor technology, perpendicular nanomagnet logic (pNML) intrinsically enables the design of 3-D devices. It is very low-power consumption and offers the possibility to be integrated in the back end of traditional fabrication processes. These characteristics make pNML an ideal candidate to implement low-power coprocessors. In this paper, we demonstrate the possibilities offered by pNML technology by designing a 3-D coprocessor for the summed-area table, one of the most common algorithms used in image processing. We demonstrate the effectiveness of the design and the technology itself by comparing the performance with transistor implementations. The 3-D design makes it possible to obtain a small circuit footprint. Overall, the results presented here are a great step forward toward the design of 3-D coprocessors in pNML technology.

The Design and Implementation of an Embedded Real-Time Automated IC Marking Inspection System

This paper presents the system and algorithm designs of a real-time automated integrated circuit (IC) marking inspection system based on the embedded platform. Specifically, the system-level design and the integration of hardware and software components are illustrated in this paper. Furthermore, in order to enhance the accuracy of IC inspection, this paper presents a novel algorithm which integrates the classic template matching approach with an efficient angle estimation method, so that the rotation and location of the IC chip can be identified precisely. Formal outline of the proposed algorithm is given in this paper. Moreover, aiming at reducing the computation time, the algorithmic optimizations based on the multi-core embedded processor and the single instruction, multiple data architecture are presented. The experiment results show that, compared to the conventional IC marking inspection algorithm, the proposed system and algorithm greatly improve the efficiency and accuracy of image processing on the embedded system. In particular, when the size of the target image is 640 × 480 pixels and size of the template image is 80 × 100, the average inspection time is 31 ms, which is an approximately 20× improvement from the conventional inspection scheme.

Memristor-Based Hardware Accelerator for Image Compression

Memristor-based hardware accelerators are gaining an increased attention as a potential candidate to speed-up the vector-matrix operations commonly needed in many digital image processing tasks due to their area, speed, and energy efficiency. In this paper, a memristor-based image compression (MR-IC) architecture that exploits a lossy 2-D discrete wavelet transform is proposed. The architecture is composed of a computational memristor crossbar, an intermediate memory array that stores the row-transformed coefficients and a final memory that holds the compressed version of the original image. The computational memristor array performs in-memory computation on the initially stored transformation coefficients. Using the quantitative analysis approach, we demonstrate a $10\times $ reduction in a number of operations compared with a conventional application-specific integrated circuit implementation. This translates to five orders of magnitude reduction in area, around $11\times $ improvement in energy efficiency, and $1.28\times $ speedup in computation time. Image quality metrics, such as peak signal-to-noise ratio (PSNR), structural similarity (SSIM) index, and complex wavelet-SSIM (CW-SSIM), are used to quantify the reduction in image quality due to lossy compression. The achieved metrics for conventional versus MR-IC are: PSNR 57.24 versus 33.29 dB, SSIM 0.9994 versus 0.8853, and CW-SSIM 1 versus 0.9983. Simulation results show that the 32 quantization levels proposed architecture provides significant improvements in energy, area, and performance compared to the 32 levels CMOS implementation with comparable CW-SSIM.

HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs

To mitigate the excess timing margin in conventional digital integrated circuit design, resilient circuits were proposed. The current techniques however either have a large error-detecting register or have difficulty in wide-voltage-range (down to near-threshold) operation. In this paper, we propose a light-weight holosymmetrical transition detector (HTD) that can work reliably at near-threshold to normal VDD with fast response time. Combined with a conventional latch, the HTD-latch is used to replace the end point flip-flop for timing error prediction with an area overhead of only 9.5% over a conventional flip-flop. Besides, we optimize the speculation window and design an adaptive duty-cycle control mechanism to reduce the short-path padding overhead in a resilient circuit. In addition, with voltage scaling, we keep the system working at the point before the first failure by using local detection and global clock gating, which needs neither architectural circuit change nor complicated error recovery mechanism. We apply the above-mentioned three techniques on an eighth-order filter test chip in a 40-nm CMOS process. The measurement results demonstrate that the proposed HTD can work robustly at 0.474–1.1 V. With 4.37% area overhead in total, the proposed resilient technique improves performance by 179.31%/28.2% and energy efficiency by 45.6%/28.1% in a near- $V_{\mathrm {TH}}$ (0.474 V)/super- $V_{\mathrm {TH}}$ (1.1 V) operation, as compared with the baseline design. Therefore, our proposed HTD-based resilient technique can improve the energy efficiency of circuits by almost eliminating all the timing margins.

Three-dimensional integration of nanotechnologies for computing and data storage on a single chip.

The computing demands of future data-intensive applications will greatly exceed the capabilities of current electronics, and are unlikely to be met by isolated improvements in transistors, data storage technologies or integrated circuit architectures alone. Instead, transformative nanosystems, which use new nanotechnologies to simultaneously realize improved devices and new integrated circuit architectures, are required. Here we present a prototype of such a transformative nanosystem. It consists of more than one million resistive random-access memory cells and more than two million carbon-nanotube field-effect transistors-promising new nanotechnologies for use in energy-efficient digital logic circuits and for dense data storage-fabricated on vertically stacked layers in a single chip. Unlike conventional integrated circuit architectures, the layered fabrication realizes a three-dimensional integrated circuit architecture with fine-grained and dense vertical connectivity between layers of computing, data storage, and input and output (in this instance, sensing). As a result, our nanosystem can capture massive amounts of data every second, store it directly on-chip, perform in situ processing of the captured data, and produce 'highly processed' information. As a working prototype, our nanosystem senses and classifies ambient gases. Furthermore, because the layers are fabricated on top of silicon logic circuitry, our nanosystem is compatible with existing infrastructure for silicon-based technologies. Such complex nano-electronic systems will be essential for future high-performance and highly energy-efficient electronic systems.

Thermoelectrical modelling and simulation of devices based on VO2

Limits of development of conventional silicon-based integrated circuits get closer. More and more effort is done to develop new devices for integrated circuits. A promising structure is based on the semiconductor-to-metal phase change of vanadium-dioxide at about 67°C. In these circuits the information is carried by combined thermal and electrical currents. For device modelling and circuit design, accurate distributed electro-thermal transient simulation is mandatory. This paper is the first one to present an electro-thermal transient simulation method for VO2 devices operating in real-world conditions. The paper presents three VO2 material models, the algorithmic extension of an electro-thermal field simulator to be able to handle hysteresis and the transient simulation issues of VO2 and the modelling of VO2 based devices. The paper compares measured and simulated device characteristics.

Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

A Measurement Method on Nanoscale Thickness of the Ti Barrier Layer of TSV Structure for 3-D IC

As the characteristic dimension of an integrated circuit (IC) continuously scales down, together with the requirements of low power consumption, multiple functionality, and cost effectiveness, the conventional IC transforms into a 3-D IC. Through-silicon via (TSV) is a promising and preferred way to realize the reliable interconnection for a 3-D IC. Thus, accurate measurement of the critical structural parameters plays an important role in securing the integrity and reliability of TSV. In this paper, a novel image-processing-based measurement method is proposed to measure the barrier layer thickness and step coverage of TSV. Since the thickness of the barrier layer is generally less than 100 nm, which is a drawback of the conventional SEM method, we used the material information from SEM as well as structural prior of TSV to infer the barrier layer thickness on nanoscale. In addition, we further achieved the step coverage of thin films in TSV using the proposed measurement method.

Magnetic-free non-reciprocity based on staggered commutation

Lorentz reciprocity is a fundamental characteristic of the vast majority of electronic and photonic structures. However, non-reciprocal components such as isolators, circulators and gyrators enable new applications ranging from radio frequencies to optical frequencies, including full-duplex wireless communication and on-chip all-optical information processing. Such components today dominantly rely on the phenomenon of Faraday rotation in magneto-optic materials. However, they are typically bulky, expensive and not suitable for insertion in a conventional integrated circuit. Here we demonstrate magnetic-free linear passive non-reciprocity based on the concept of staggered commutation. Commutation is a form of parametric modulation with very high modulation ratio. We observe that staggered commutation enables time-reversal symmetry breaking within very small dimensions (λ/1,250 × λ/1,250 in our device), resulting in a miniature radio-frequency circulator that exhibits reduced implementation complexity, very low loss, strong non-reciprocity, significantly enhanced linearity and real-time reconfigurability, and is integrated in a conventional complementary metal–oxide–semiconductor integrated circuit for the first time.

An X‐band RLC matched power amplifier using quasi‐MMIC technology

ABSTRACTThis article presents an RLC matched power amplifier using quasi‐MMIC technology in the X‐band. The power amplifier consists of a GaN HEMT power device and several passive components including inductors, capacitors, resistors, and transmission lines using a silicon integrated passive device (IPD) process. The standard silicon process can drive the solution to cost down compared with conventional microwave monolithic integrated circuit (MMIC) technology. This technology using silicon IPDs provides small size matching networks close to MMIC dimensions. The input matching network using the RLC matched circuit is designed to obtain broadband characteristic and gain flatness. The dimensions of input and output silicon IPD are 1.5 mm × 1.2 mm and 1.9 mm × 2.2 mm, respectively, with a thickness of only 0.15 mm. The measured results show that the quasi‐MMIC power amplifier has a P3dB of more than 38.3 dBm with a drain efficiency of more than 51.2% in the frequency range from 8.2 to 10 GHz. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:2803–2807, 2015

An Ion Gel as a Low-Cost, Spin-Coatable, High-Capacitance Dielectric for Electrowetting-on-Dielectric (EWOD).

For many practical electrowetting-on-dielectric (EWOD) applications, the use of high-capacitance dielectric materials is critically demanded to induce a large surface tension modulation. Thin-film dielectric layers such as Parylene C, silicon dioxide (SiO2), and aluminum oxide (Al2O3) have been commonly used for EWOD. However, these dielectric materials are fabricated by conventional integrated circuit (IC) processes which are typically time-consuming and require complex and expensive laboratory setups such as high-vacuum facilities. In this article, a novel ion gel material was demonstrated as a spin-coatable and high-capacitance dielectric for low-cost EWOD applications. The ion gel offers a 2 or 3 order higher capacitance (c ≈ 10 μF/cm(2)) than conventional dielectrics commonly used for EWOD while being fabricated through a simple low-cost spin-coating process. We discuss the fundamentals of an ion gel dielectric, its fabrication process of spin coating, and the interaction with a hydrophobic layer for practical EWOD applications. The ion gel films, which consist of a copolymer, poly(vinylidene fluoride-co-hexafluoropropylene) [P(VDF-HFP)], and an ionic liquid, 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide [EMIM][TFSI], were successfully deposited on ITO substrates by using a simple spin-coating process. The experimental demonstrations validated the theoretical modeling of the ion gel layer as a high-capacitance dielectric. The EWOD performance of the ion gel samples was compared to that of other conventional dielectric materials to show the performance improvement.

Novel technique for lateral high‐voltage totem‐pole power devices

A novel technique and related structure for a high-voltage integrated circuit (IC) with totem-pole high-voltage devices are proposed. In this technique, a low control voltage with respect to the tub is used to drive the high-side device in the totem pole through a low-voltage tub circuit, as well as through very small low-side device to drive a low-voltage ground circuit, which in turn drives the low-side device in the totem pole. Therefore, the high-voltage level-shifting circuit can be replaced by the tub circuit which takes only a very small area and has no parasitic effects in comparison with that in the conventional totem-pole high-voltage IC. The structure of low-voltage power supplies for low-voltage ICs is also proposed. The results of numerical simulation verify the applicability of the proposed structure.

Characterization of a new fluorescence-enhancing substrate for microarrays with femtomolar sensitivity

The demand for high sensitivity in microarray technology has stimulated the research of new labeling strategies, new substrates with increased loading capacity and new approaches to amplify the fluorescence signals. Although these methods improve the sensitivity, they are based on non-routine procedures which limit their widespread usage. A simple way to achieve fluorescence enhancement is the optical interference (OI) coating technology based on the use of substrates with films of well-defined thickness that maximize photoabsorption of the dye molecules in the vicinity of the surface and reflect the emitted light toward the detector. Here we introduce a new substrate for fluorescence enhancement composed of a thin aluminum mirror and a single quarter wave silicon oxide as a dielectric layer. The use of such material allows the development of a substrate suited for parallel production in conventional IC (Integrated Circuit's) technology, which produces a 20-fold enhancement of fluorescence compared to glass, which is the most common material used in microarrays. The new substrate was coated with a copolymer of N,N-dimethylacrylamide, N-acryloyloxysuccinimide, and 3-(trimethoxysilyl)propyl methacrylate, copoly(DMA-NAS-MAPS), which forms, by a simple and robust procedure, a functional nanometric film that covalently binds bio-probes on the surface and efficiently suppresses non-specific adsorption. The performance of the new fluorescence-enhancing substrate in microarray technology was demonstrated for the detection of a panel of inflammation biomarkers pushing detection limits into the femtomolar range.

A Switched Inductor Topology Using a Switchable Artificial Grounded Metal Guard Ring for Wide-FTR MMW VCO Applications

In conventional integrated circuit technologies, a grounded metal guard ring (MGR) is widely used to mitigate the coupling effect between any pair of inductors. Full-wave electromagnetic (EM) simulation results indicate that the guard ring size can significantly affect the inductance value of a single-turn planar inductor. This paper proposes a switchable artificial grounded MGR technique that can not only serve as a guard ring but also change the inductance. Accordingly, an inductor, featuring switchable inductance and high quality factor, is developed for a 60-GHz millimeter-wave wide-frequency tuning range (wide-FTR) and low phase-noise voltage-controlled oscillator (VCO) in 90-nm bulk CMOS technology. The VCO testkey achieves a total tuning range of 9.43 GHz (17%). The measured phase noise levels are -92.2 and -119 dBc/Hz at 1- and 10-MHz offsets, respectively. The experimental results demonstrate that the proposed inductor topology offers the VCO an increase of 36% in the FTR and a competitive performance in phase noise, as contrasted with a conventional varactor-tuned VCO. This VCO achieves a record of -188 dBc/Hz for the FOM <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> .