Conventional Finite Impulse Response Filter Research Articles

Enhanced FPGA linear phase FIR filter with amalgam multiplier

ABSTRACT Designing high-performance integrated circuits that balance area, speed, and power is increasingly challenging. This study optimises hardware implementation of FIR filters using an innovative Amalgam Multiplier, minimising resource use without compromising performance. The key challenge in designing signal processing hardware is the multiplier design, which significantly affects efficiency. This study explores integrated circuit optimisation, addressing the delicate balance between area utilisation, speed, and power consumption. Focusing on hardware implementation of Finite Impulse Response (FIR) filters in signal processing, the article starts with a conventional FIR filter design using a standard array multiplier which consumed 1.790 W, with 8 s real-time completion. Then, Linear Phase FIR (LP-FIR) filter is designed using Braun and Dadda Multiplier. LP-FIR filter with Braun multiplier consumed 1.436 W power and 26 s of completion time whereas LP-FIR with Dadda multiplier consumed 1.363 W power and 23 s of completion time. Finally, the implementation of novel LP-FIR enhanced by Amalgam multiplier consumed 0.302 W power and 10.29 s of completion time, marking a significant advancement in integrated circuit design.

Estimation of High-Frequency Oscillation’s Magnitude and Frequency Based on Multi-Tone FIR Filter

Recently, several high-frequency oscillation (HFO) events have occurred, and have introduced a serious threat to power system stability. It is significant to estimate HFO magnitude and frequency in a fast and accurate way for HFO early warning and mitigation. This paper designs a novel finite impulse response (FIR) filter that is formed by several weighted window function-based FIR filters with different center frequencies, and is named the multi-tone FIR (MTFIR) filter. The frequency error introduced by the MTFIR filter is analyzed, and optimal MTFIR filter parameters are accordingly selected to achieve the smallest frequency error. Performance tests show that the proposed MTFIR filter estimator is more accurate than the conventional FIR filter, the interpolated discrete Fourier transform, and the P-class harmonic phasor estimator in HFO magnitude and frequency estimation. The response time of the proposed estimator is shorter than 20 ms, which meets the IEEE/IEC standard requirement on protection applications.

A reconfigurable high-speed and low-complexity residue number system-based multiply-accumulate channel filter for software radio receivers

PurposeFilter design plays an essential role in most communication standards. The essential element of the software-defined radio is a channelizer that comprises several channel filters. Designing filters with lower complexity, minimized area and enhanced speed is a demanding task in currently prevailing communication standards. This study aims to propose an efficient reconfigurable residue number system (RNS)-based multiply-accumulate (MAC) channel filter for software radio receivers.Design/methodology/approachRNS-based pipelined MAC module for the realization of channel finite impulse response (FIR) filter architecture is considered in this work. Further, the use of a single adder and single multiplier for realizing the filter architecture regardless of the number of taps offers effective resource sharing. This design provides significant improvement in speed of operation as well as a reduction in area complexity.FindingsIn this paper, two major tasks have been considered: first, the RNS number conversion is performed in which the integer is converted into several residues. These residues are processed in parallel and are applied to the MAC-FIR filter architecture. Second, the MAC filter architecture involves pipelining, which enhances the speed of operation to a significant extent. Also, the time-sharing-based design incorporates a single partial product-based shift and add multiplier and single adder, which provide a low complex design. The results show that the proposed 16-tap RNS-based pipelined MAC sub-filter achieves significant improvement in speed as well as 89.87% area optimization when examined with the conventional RNS-based FIR filter structure.Originality/valueThe proposed MAC-FIR filter architecture provides good performance in terms of complexity and speed of operation because of the use of the RNS scheme with pipelining and partial product-based shift and adds multiplier and single adder when examining with the conventional designs. The reported architecture can be used in software radios.

Design and Implementation of 6-Tap FIR Filter Using MAC for Low Power Applications

Abstract: A Significant number of mathematical operations, such as multiplication and accumulation, are often required by a digital signal processing (DSP) algorithm. Many DSP applications have latency limitations, which mean that the DSP operation must be performed within a certain amount of time for the system to function, and because DSP gives high accuracy, filters constructed in DSP have tighter control over the output accuracy. As a result, DSP applications must be fast, have a high throughput, and use little power. Filters with a finite impulse response (FIR) are commonly employed in digital signal processing (DSP) applications. A FIR filter that is efficient in terms of electricity is being built. The multiplier and accumulator (MAC) unit used a new implementation approach to develop this system. FIR filter is a type of filter. Multipliers, adders, and a variety of other components are commonly used in FIR filters. Multipliers, adders, and a series of delays are used to form the filter's output in FIR filters. The goal of this project is to design and implement a 6-tap finite impulse response (FIR) filter by replacing multipliers with an 8-bit Multiplier and Accumulator (MAC) unit within the FIR filter, where a low-power MAC unit is always a key to achieving high performance in a DSP system, and D flip-flops are used in place of delays and constructed using a latch-based design. The Wallace tree Multiplier was utilised in the construction of the MAC unit because it reduces the amount of partial products, and the adders used for accumulation are half adders and full adders. In the FIR filter, for the purpose of summing This work evaluates performance of FIR filter in terms of speed and power and synthesis are executed in Xilinx Vivado 2018.1 software environment and the implementation is done using VHDL codes. The result analysis shows that the proposed FIR filter consumes low power than conventional (standard) FIR filter. As the dynamic power results up to 11.932W and after implementation it results up to 12.029W. Keywords: MAC, Low power, latch-based design.

RETRACTED ARTICLE: Implementation of efficient reconfigurable FIR filter with control logic for 5G applications

Filters are used to achieve frequency selectivity on the spectrum of input signal. Due to the stability of finite impulse response (FIR) filters, they are used in most of the applications. In the conventional FIR filters, the frequency band is fixed and cannot be changed once it is designed. Hence, there is a necessity of an FIR filter with auto-adjustment of band width in modern day communication systems like 5G. The design of FIR filter requires more number of filter coefficients to get the desired bandwidth specification. This results in a large slice for field programmable gate array implementation. Here, it proposed a state machine to select different FIR filters with the designated set of coefficients. Each FIR filter is having different set of coefficients, and based on the frequency of the clock signal, the FIR filter is selected and thereby frequency selectivity can be achieved. The proposed method is to implement reconfigurable FIR (RFIR) filter with control logic for auto-adjustment of frequency selections to achieve better band width requirements. The filter order is initially selected as 4 and presented the simulation results. The order of the filter(n) increased to 24 for verifying the bandwidth selection. The proposed architecture is compared with the existing architecture with 16 bits and 11 taps. The proposed method saves 33.5% of look-up-tables (LUTs) compared to the existing methods. Simulation results presented are verified using Xilinx ISE design suite 14.7. The total number of four-input LUTs utilized are 630 for order(n) of the filter 24. Power consumed by the overall design is 195 mW.

시변 이산 선형 시스템에 대한 지수가중 유한 임펄스 응답 필터

In this paper, an exponentially weighted Finite Impulse Response (FIR) filter is proposed for discrete-time linear time-varying systems. The weighting method of measurements was first introduced for the FIR structured estimators, then an optimal design of the exponentially weighted FIR filter was developed with respect to a minimum variance criterion for discrete-time linear time-varying systems. The proposed filter is designed to be unbiased and independent of initial state information. Due to the inclusion of the weighting factor, it is expected to be less prone to model uncertainty and numerical errors than the conventional optimal FIR filter. Moreover, the proposed FIR filter is reduced to the optimal time-varying FIR filter with an equal weight, and can thereby provide a more general solution than the conventional optimal FIR filter. Through a numerical study, the performance of the proposed FIR filter was shown by comparing it with the exponentially weighted Kalman filter and the conventional optimal FIR filter when the modeling uncertainties exist.

Systolic Fir Filter using Bypass Multiplier

In DSP the most common function is Finite Impulse Response (FIR) filter which is realized in field Programmable gate Arrays (FPGAs). For efficient Very Large Scale Integration (VLSI) computation systolic FIR filter architecture has attractive models. High speed is the major concern for fast computation in real time Digital Signal Processing (DSP) applications. In conventional systolic FIR filter method uses general array multiplier structure which takes more time to compute the process with high design complexity with less power. To overcome this problem the systolic FIR filter utilizing Bypass Feed Direct Multiplier(BFDM) is proposed. The proposed method 16 tap systolic FIR parallel processing offers less delay with less design complexity which is used in image and signal processing applications. The proposed method is simulated using Xilinx ISE 12.4 ISE tool and the functions are evaluated by MODELSIM 6.3C.

Coefficient Reduction Method for Stopband Ripple Minimization of IFIR Filter

This paper presents a technique for minimization of ripples of interpolated finite impulse response (IFIR) filter. Single-stage and two-stage IFIR filters are designed using the Remez exchange algorithm. The performance of these filters is improved by minimizing the ripples in the stopband region by discarding zero-valued coefficients. The proposed technique yields the desired filter response of IFIR filters matching closely with the required response of finite impulse response (FIR) filter in the passband and stopband regions, providing very low computational complexity and sharp transition width as compared to the conventional FIR filter. In comparison to other existing techniques, the proposed algorithm reduces the stopband ripples significantly (the distortion in the frequency domain is reduced up to 61.20%). As a result, the power losses in the filtered signal are reduced, thereby enhancing the sensitivity and its consistency during the filtering process.

Exploiting Coefficient Symmetry in Conventional Polyphase FIR Filters

The conventional polyphase architecture for linear-phase finite impulse response (FIR) filter loses its coefficient symmetry property due to the inefficient arrangement of the filter coefficients among its subfilters. Although, existing polyphase structures can avail the benefits of coefficient symmetry property, at the cost of versatility and complex subfilters arrangement of the conventional polyphase structure. To address these issues, in this paper, we first present the mathematical expressions for inherent characteristics of the conventional polyphase structure. Thereafter, we use these expressions to develop a generalized mathematical framework which exploits coefficient symmetry by retaining the direct use of conventional FIR filter coefficients. Further, the transfer function expressions for the proposed Type-1/transposed Type-1 polyphase structures using coefficient symmetry are derived. The proposed structures can reduce the requirement of multiplier units in polyphase FIR filters by half. We also demonstrate the decimator design using the proposed Type-1 polyphase structure and the interpolator design using the proposed transposed Type-1 polyphase structure. Moreover, the phase and magnitude characteristics of the proposed Type-1/transposed Type-1 polyphase structures are presented. It is revealed via numerical examples that all subfilters of the proposed symmetric polyphase structure possess linear-phase characteristics.

A 750-nW 1-MHz 9-tap analog finite impulse response filter for wireless senor network chip

This paper presents a low power Finite Impulse Response (FIR) filter based on discrete-time analog computing. The analog FIR filter is first presented to deal with analog signal. To improve linearity, two-double boost technique is introduced in the sample and hold cells which are used to achieve delay-time function. Meanwhile, the four-quadrant voltage-mode multiplier consists of PMOS substract cell and combiner cell, which is independent of device parameters. To realize the shift registers function, the rotating switch matrix circuit is adopted controlled by phase shift clocks. All MOS transistors implemented in this architecture are biased in subthreshold region with a supply voltage of 0.6 V to reduce the power consumption. Simulation results show that the analog FIR filter dissipates 750 nW at 1 MHz sample frequency and the effective number of bits of the proposed analog FIR filter is more than 7 bits. Compared to the conventional digital FIR filter, power consumption is reduced by 72.22% at 1 MHz in a 0.18μm CMOS process.

Implementation of High Speed Operating FIR Filter with DA Algorithm Comparing Results with MAC Algorithm and Simple FIR Filter Result

Recent years there has been a increasing trend to implement digital signal processing functions in Field ProgrammableGate Array (FPGA). therefor, we need to put great effort in designing efficient architectures for digital signal processing functionssuch as FIR filters, which are widely used in audio and video signal processing, telecommunications etc. We are going to present amethod for implementing high speed Finite Impulse Response (FIR) filters using MAC (MULTIPLY AND ACCUMULATE) andDistributed Arithmetic (DA) method. MAC is a conventional FIR filter In these method adders, multipliers and delay elements areused. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general symmetric version of an FIR filter dueto its high stability and linearity by taking optimal advantage of the look-up table (LUT) based structure of FPGAs. The performanceof the DA technique for FIR filter design is analyzed and the results are compared to the MAC design technique.

Implementation of High Speed Operating FIR Filter with DA Algorithm Comparing Results with MAC Algorithm and Simple FIR Filter Result

Recent years there has been a increasing trend to implement digital signal processing functions in Field Programmable Gate Array (FPGA). therefor, we need to put great effort in designing efficient architectures for digital signal processing functions such as FIR filters, which are widely used in audio and video signal processing, telecommunications etc. We are going to present a method for implementing high speed Finite Impulse Response (FIR) filters using MAC (MULTIPLY AND ACCUMULATE) and Distributed Arithmetic (DA) method. MAC is a conventional FIR filter In these method adders, multipliers and delay elements are used. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general symmetric version of an FIR filter due to its high stability and linearity by taking optimal advantage of the look-up table (LUT) based structure of FPGAs. The performance of the DA technique for FIR filter design is analyzed and the results are compared to the MAC design technique.

Design of multiplier-less sharp transition width non-uniform filter banks using gravitational search algorithm

In this paper, multiplier-less near-perfect reconstruction tree-structured filter banks are proposed. Filters with sharp transition width are preferred in filter banks in order to reduce the aliasing between adjacent channels. When sharp transition width filters are designed as conventional finite impulse response filters, the order of the filters will become very high leading to increased complexity. The frequency response masking (FRM) method is known to result in linear-phase sharp transition width filters with low complexity. It is found that the proposed design method, which is based on FRM, gives better results compared to the earlier reported results, in terms of the number of multipliers when sharp transition width filter banks are needed. To further reduce the complexity and power consumption, the tree-structured filter bank is made totally multiplier-less by converting the continuous filter bank coefficients to finite precision coefficients in the signed power of two space. This may lead to performance degradation and calls for the use of a suitable optimisation technique. In this paper, gravitational search algorithm is proposed to be used in the design of the multiplier-less tree-structured uniform as well as non-uniform filter banks. This design method results in uniform and non-uniform filter banks which are simple, alias-free, linear phase and multiplier-less and have sharp transition width.

Reconstruction of dynamic displacement and velocity from measured accelerations using the variational statement of an inverse problem

This paper presents two types of finite impulse response (FIR) filters to reconstruct dynamic displacement induced by structural vibration from measured acceleration. The governing equation for the reconstruction is derived by taking the variation of a minimization problem, which defines an inverse problem on displacement. A regularization function for overcoming the ill-posedness of the inverse problem is included in the minimization problem. The governing equation of the inverse problem becomes the same type of differential equation as that of a beam on an elastic foundation. The conventional FIR (CFIR) filter directly approximates the transfer function of the governing equation, while the FEM-based FIR (FFIR) filter is formulated by the discretization of the minimization problem with the finite element method. For the finite element discretization, the Hermitian shape function is utilized. The proposed FFIR filter is capable of reconstructing displacement and velocity simultaneously. The fundamental characteristics of the proposed filters are investigated in the frequency domain using the transfer and accuracy functions. It is shown that the proposed FIR filters suppress low frequency noise components in measured accelerations effectively, and reconstruct physically meaningful displacement accurately. The validity of the proposed filters is demonstrated through a numerical simulation study, a field experiment and an evaluation of flutter derivatives using measurements taken from a wind tunnel test.

Equalization of nonlinear transmission impairments by maximum-likelihood-sequence estimation in digital coherent receivers

We describe a successful introduction of maximum-likelihood-sequence estimation (MLSE) into digital coherent receivers together with finite-impulse response (FIR) filters in order to equalize both linear and nonlinear fiber impairments. The MLSE equalizer based on the Viterbi algorithm is implemented in the offline digital signal processing (DSP) core. We transmit 20-Gbit/s quadrature phase-shift keying (QPSK) signals through a 200-km-long standard single-mode fiber. The bit-error rate performance shows that the MLSE equalizer outperforms the conventional adaptive FIR filter, especially when nonlinear impairments are predominant.

Calculation of narrowband lowpass filters with finite impulse response

This study provides a review of digital filters known under the name “interpolated finite impulse response filters” (IFIR filters) that make it possible to create narrowband lowpass filters (LPF) with substantially reduced computational load and, consequently, a simpler design as compared with the conventional finite impulse response filters (FIR filters).

Efficient FPGA implementation of sharp FIR filters using the FRM technique

A high-performance field programmable gate array (FPGA) implementation of full pipelined computation structure is proposed for sharp finite-impulse -response (FIR) filters using the frequency response masking (FRM) technique. The FRM-based FIR (FFIR) filter consists of a novel symmetrical systolic array of a interpolated FIR(IFIR) filter in cascade to a pair of nonsymmetrical systolic arrays of masking FIR filters mainly. These filters are designed based on inner-product computation involving MAC operation which can be realized by the DSP block in the latest FPGA device efficiently. The realization results on a Xilinx Virtex-5 chip show that the proposed FPGA implementation can obtain higher throughput but consumes less resource compared to the equivalent conventional sharp FIR (CSFIR) filter that developed by the Core Generator software tool.

FIR Filter of DS-CDMA UWB Modem Transmitter

This letter presents low-complexity digital pulse shaping filter structures of a direct sequence code division multiple access (DS-CDMA) ultra wide-band (UWB) modem transmitter with a ternary spreading code. The proposed finite impulse response (FIR) filter structures using a look-up table (LUT) have the effect of saving the amount of memory by about 50% to 80% in comparison to the conventional FIR filter structures, and consequently are suitable for a high-speed parallel data process.

Low power and high-speed implementation of fir filters for software defined radio receivers

The most computationally intensive part of the wideband receiver of a software defined radio (SDR) is the intermediate frequency (IF) processing block. Digital filtering is the main task in IF processing. The computational complexity of finite impulse response (FIR) filters used in the IF processing block is dominated by the number of adders (subtracters) employed in the multipliers. This paper presents a method to implement FIR filters for SDR receivers using minimum number of adders. We use an arithmetic scheme, known as pseudo floating-point (PFP) representation to encode the filter coefficients. By employing a span reduction technique, we show that the filter coefficients can be coded using considerably fewer bits than conventional 24-bit and 16-bit fixed-point filters. Simulation results show that the magnitude responses of the filters coded in PFP meet the attenuation requirements of wireless communication standard specifications. The proposed method offers average reductions of 40% in the number of adders and 80% in the number of full adders needed for the coefficient multipliers over conventional FIR filter implementation methods

A Low-Complexity Adaptive Echo Canceller for xDSL Applications

A finite impulse response (FIR)-based adaptive filter structure is proposed for echo cancellation in xDSL applications. The proposed algorithm consists of an FIR filter, a cascaded interpolated FIR filter, and a tap-weight overlapping and nulling scheme. This filter requires low computational complexity and inherits the stable characteristics of the conventional FIR filter. Simulations show that the proposed echo canceller can effectively cancel the echo up to 73.4 dB [for a single-pair high-speed digital subscriber line (SHDSL) system]. About 55% complexity reduction can be achieved compared with a conventional FIR filter.