Conventional Dynamic Random Access Memory Research Articles

Capacitorless Two‐Transistor Dynamic Random‐Access Memory Cells Comprising Amorphous Indium–Tin–Gallium–Zinc Oxide Thin‐Film Transistors for the Multiply–Accumulate Operation

AbstractCapacitorless two‐transistor (2T0C) dynamic random‐access memory (DRAM) cells comprising oxide thin‐film transistors (TFTs) show potential as low‐power and high‐density DRAM cells; however, the multiply–accumulate (MAC) operation using these cells is not yet realized. In this study, 2T0C DRAM cells comprising amorphous indium–tin–gallium–zinc oxide TFTs are fabricated for MAC operations. In a 2T0C DRAM cell, one transistor acts as a write transistor and the other as a read transistor, whose gate capacitance corresponds to the data storage capacitance. The cells have a long retention time of 1000 s, which is 104 times longer than that of conventional DRAM cells, owing to the extremely low leakage current of the TFTs (1.11 × 10−18 A µm−1). These cells satisfy the original condition for synaptic devices, in which a proportional relationship exists between the input and output. The MAC operation is performed using two cells. This study demonstrates the usefulness of oxide TFTs in artificial neural networks.

Mitigating WL-to-WL Disturbance in Dynamic Random-Access Memory (DRAM) through Adopted Spherical Shallow Trench Isolation with Silicon Nitride Layer in the Buried Channel Array Transistor (BCAT)

The Pass Gate Effect (PGE), often referred to as adjacent cell interference, presents a significant challenge in dynamic random-access memory (DRAM). In this study, we investigate the impact of PGE and propose innovative solutions to address this issue in DRAM technology, employing 10 nm node technology with buried channel array transistors. To evaluate the efficacy of our proposals, we utilized SILVACO for simulating various DRAM configurations. Our approach centers on two key structural optimizations: the introduction of a spherical Shallow Trench Isolation (STI) and the incorporation of a silicon nitride (Si3N4) layer within the spherical STI structure. These optimizations were meticulously designed to mitigate the PGE by considering several factors that are highly influential in its manifestation. To validate our approach, we conducted comprehensive simulations, comparing the PGE factors of typical DRAM structures with those of our proposed configurations. The results of our analysis strongly support the effectiveness of our proposed structural enhancements in alleviating the PGE when contrasted with conventional DRAM structures. Remarkably, our optimizations achieved a remarkable 82.4% reduction in the PGE, marking a significant breakthrough in the field of DRAM technology. By addressing the PGE challenge and substantially reducing its impact, our research contributes to the advancement of DRAM technology, offering practical solutions to enhance data integrity and reliability in the era of 10 nm node DRAM.

Oxide and 2D TMD semiconductors for 3D DRAM cell transistors.

As the downscaling of conventional dynamic random-access memory (DRAM) has reached its limits, 3D DRAM has been proposed as a next-generation DRAM cell architecture. However, incorporating silicon into 3D DRAM technology faces various challenges in securing cost-effective high cell transistor performance. Therefore, many researchers are exploring the application of next-generation semiconductor materials, such as transition oxide semiconductors (OSs) and metal dichalcogenides (TMDs), to address these challenges and to realize 3D DRAM. This study provides an overview of the proposed structures for 3D DRAM, compares the characteristics of OSs and TMDs, and discusses the feasibility of employing the OSs and TMDs as the channel material for 3D DRAM. Furthermore, we review recent progress in 3D DRAM using the OSs, discussing their potential to overcome challenges in silicon-based approaches.

A unified hybrid memory system for scalable deep learning and big data applications

Emerging non-volatile memory (NVM) technologies are of dynamic random access memory (DRAM)-like, high capacity, and low cost, at the expense of slower bandwidth and higher read/write latency compared to DRAM. Typically, NVM finds its primary application in serving as an extension of conventional DRAM to create hybrid memory systems tailored to non-uniform memory access (NUMA) architectures. This strategic integration offers the potential for high performance, enhanced capacity efficiency, and a favorable balance of cost considerations. Traditional NUMA memory management policies distribute data uniformly across both DRAM and NVM, overlooking the inherent performance gap between these heterogeneous memory systems. This challenge becomes particularly pronounced when provisioning resources for deep learning and big data applications in hybrid memory systems. To tackle the performance issues in the hybrid memory systems, we propose and develop a unified memory system, UniRedl, which automatically optimizes data migration between DRAM and NVM based on data access patterns and computation graphs of applications. To improve application performance, we provide a new memory allocation strategy named HiLowAlloc. We further design two data migration strategies in UniRedl, Idle Migration and Dynamic Migration, for management of hybrid memory systems. Specifically, Idle Migration aims to manage data placed in DRAM, while Dynamic Migration manages data saved in NVM. The experimental results demonstrate that on average UniRedl improves application performance by 33.2%, 20.6%, 19.0%, and 17.5% compared to the traditional NUMA, NUMA with anb, BMPM, and OIM, respectively. It also achieves 52.0%, 34.3%, 30.6%, 22.1% on average improvement in data locality against the state-of-the-art solutions.

Circuit-Level Memory Technologies and Applications based on 2D Materials.

Memory technologies and applications implemented fully or partially using emerging 2D materials have attracted increasing interest in the research community in recent years. Their unique characteristics provide new possibilities for highly integrated circuits with superior performances and low power consumption, as well as special functionalities. Here, an overview of progress in 2D-material-based memory technologies and applications on the circuit level is presented. In the material growth and fabrication aspects, the advantages and disadvantages of various methods for producing large-scale 2D memory devices are discussed. Reports on 2D-material-based integrated memory circuits, from conventional dynamic random-access memory, static random-access memory, and flash memory arrays, to emerging memristive crossbar structures, all the way to 3D monolithic stacking architecture, are systematically reviewed. Comparisons between experimental implementations and theoretical estimations for different integration architectures are given in terms of the critical parameters in 2D memory devices. Attempts to use 2D memory arrays for in-memory computing applications, mostly on logic-in-memory and neuromorphic computing, are summarized here. Finally, challenges that impede the large-scale applications of 2D-material-based memory are reviewed, and perspectives on possible approaches toward a more reliable system-level fabrication are also given, hopefully shedding some light on future research.

Inverting logic-in-memory cells comprising silicon nanowire feedback field-effect transistors

In this paper, we propose inverting logic-in-memory (LIM) cells comprising silicon nanowire feedback field-effect transistors with steep switching and holding characteristics. The timing diagrams of the proposed inverting LIM cells under dynamic and static conditions are investigated via mixed-mode technology computer-aided design simulation to verify the performance. The inverting LIM cells have an operating speed of the order of nanoseconds, an ultra-high voltage gain, and a longer retention time than that of conventional dynamic random access memory. The disturbance characteristics of half-selected cells within an inverting LIM array confirm the appropriate functioning of the random access memory array.

Design of Dynamic Random Access Memory Based on One Transistor One Diode Memory Cell

This paper presents the design analysis of Dynamic Random Access Memory (DRAM) with one transistor one diode (1T1D). The proposed structure consists of one transistor and one voltage controlled diode capacitor. The word and bit lines are connected with two voltage sources for the write operation. The source and drain of the NMOS is tied together to form the diode structure. The off-state leakage current is the main cause for the power dissipation of DRAM. Thus the improvement of power efficiency to the overall system is a critical task. The conventional DRAM cell contains one capacitor and one transistor. But the absence of capacitor in the proposed work is advantageous by means of compatibility, scalability, fabrication complexity, and cost. Tanner EDA working platform of 7 nm technology is used for the implementation of 1T1D DRAM cell in proposed work. This work achieve the power dissipation, read and write access time in the range of 2.647 mW, 0.04 μs and 0.021 μs respectively. Also, the parameter comparison is performed by changing the technologies from 10 nm to 20 nm for 1T1D DRAM cell design.

Polymorphic Memory: A Hybrid Approach for Utilizing On-Chip Memory in Manycore Systems

The key challenges of manycore systems are the large amount of memory and high bandwidth required to run many applications. Three-dimesnional integrated on-chip memory is a promising candidate for addressing these challenges. The advent of on-chip memory has provided new opportunities to rethink traditional memory hierarchies and their management. In this study, we propose a polymorphic memory as a hybrid approach when using on-chip memory. In contrast to previous studies, we use the on-chip memory as both a main memory (called M1 memory) and a Dynamic Random Access Memory (DRAM) cache (called M2 cache). The main memory consists of M1 memory and a conventional DRAM memory called M2 memory. To achieve high performance when running many applications on this memory architecture, we propose management techniques for the main memory with M1 and M2 memories and for polymorphic memory with dynamic memory allocations for many applications in a manycore system. The first technique is to move frequently accessed pages to M1 memory via hardware monitoring in a memory controller. The second is M1 memory partitioning to mitigate contention problems among many processes. Finally, we propose a method to use M2 cache between a conventional last-level cache and M2 memory, and we determine the best cache size for improving the performance with polymorphic memory. The proposed schemes are evaluated with the SPEC CPU2006 benchmark, and the experimental results show that the proposed approaches can improve the performance under various workloads of the benchmark. The performance evaluation confirms that the average performance improvement of polymorphic memory is 21.7%, with 0.026 standard deviation for the normalized results, compared to the previous method of using on-chip memory as a last-level cache.

Charge-Plasma-Based Doping-Less Vertical Thyristor for Highly Integrated Volatile Memory-Cell

Conventional dynamic random-access memory (DRAM) has been facing a severe challenge to scale down to 10 nm size. Since the cell capacitor should be able to store sufficient charges of 25~30 fF/cell, high aspect ratio of cell capacitor is inevitable, resulting in capacitors leaning into each other. To overcome this issue coming from capacitor, the two-terminal vertical thyristor-based capacitorless memory was proposed as a candidate to replace current DRAM, which consists of n++-emitter/p+-base/n+-base/p++-emitter vertical structure using conventional Si technology. The two-terminal vertical thyristor-based capacitorless memory cell having n++-emitter/p+-base/n+-base/p++-emitter structure utilizes latch-up and -down features showing bi-stable current-voltage (I-V) characteristics, so that data 0 (D0) and data 1 (D1) states can be distinguished. Nevertheless, in two-terminal vertical thyristor-based capacitorless memory, in-situ doped epitaxial growth process of silicon layers is essential. As is well known, the major disadvantage of epitaxial growth process is low throughput ratio. Besides, it is difficult to form step junctions since the dopants diffuse out from their original position during the serial epi-processes due to the high process temperature. Diffusion of dopants near the junctions is unavoidable in conventional doped thyristor memory cell fabricated with epitaxial growth, as shown in SIMS profile of Fig. 1(a). By applying the concept of charge plasma, the novel doping-less vertical thyristor as volatile memory is proposed, as shown in Fig. 1(b). In contrast with conventional doped thyristor memory cells, doping-less thyristor memory cells have step junction, as shown in carrier concentration profile of Fig. 1(c). Consequently, the vertical energy band diagram for doping-less thyristor memory cells differ from that of doped thyristor memory cells, as shown in Fig. 1(d). In addition, the conventional thyristor memory cells have been suffered from off-state leakage current because of the misfit dislocations at the highly doped junctions. On the other hand, the doping-less thyristor memory cells are misfit dislocation-free as their junctions are formed by the charge plasma, not the dopants. Moreover, the coulomb scattering can be dramatically reduced in doping-less thyristor memory cells owing to the absence of dopant and space charge, leading to the higher carrier mobility. As a result, the doping-less thyristor memory cells have lower off-state leakage current and higher on-state current, as shown in the I-V curves of Fig. 1(e) and (f). In this work, the effect of gap oxide thickness, which decides the intrinsic layer thickness, on latch-up voltage was investigated as well. In addition, the impact of p- and n-base metal work-function on the latch-up voltage of doping-less thyristor memory cell was investigated. Finally, the optimized metal work-function and gap oxide thickness for the memory cell were discussed. Acknowledgment* This research was supported by Brain Korea 21 PLUS Program in 2020, the MOTIE (Ministry of Trade, Industry & Energy 10069063) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1

Effect of Schottky Contact Emitter on Electrical Characteristics in 2-Terminal Vertical Thyristor Based Capacitorless Memory

Conventional dynamic random access memory (DRAM) has been facing a severe challenge to scale down to 10 nm size. Since the cell capacitor should be able to store sufficient charges of 25~30 fF/cell, high aspect ratio of cell capacitor is inevitable, resulting in capacitors leaning into each other. To overcome this issue coming from capacitor, the vertical thyristor-based two-terminal capacitorless memory was proposed as a promising candidate to replace current DRAM, which consists of n++-emitter/p+-base/n+-base/p++-emitter vertical structure using conventional Si technology. The two-terminal vertical thyristor based capacitorless memory cell having n++-emitter/p+-base/n+-base/p++-emitter structure could be implemented as cross-point memory array cells, as shown in Fig. 1. It utilizes latch-up features showing bi-stable current-voltage (I-V) characteristics, so that data 0 (D0) and data 1 (D1) states can be distinguished. Nevertheless, in two-terminal vertical thyristor based capacitorless memory, the latch-up and latch-down voltages decrease as the operation temperature increases, resulting in narrow memory window, as shown in Fig. 2. This is attributed to the fact that the carrier diffusion barrier decreases and carrier concentrations accumulated in base region required to generate latch-up decrease with increasing operation temperature. In our study, therefore, we propose two-terminal vertical thyristor based capacitorless memory with metal emitter replacing n++-emitter in order to reduce the temperature dependency of latch-up and latch-down voltages. The thermal conductivity of metal emitter is generally higher than that of silicon n++-emitter resulting in easier radiation of heat within the device. In addition, metal-emitter/p+-base/n+-base/p++-emitter structure can reduce the temperature dependency of latch-up and latch-down voltages since the metal emitter is immune to the decrease of bandgap with increasing temperature, unlike the silicon n++-emitter. We demonstrated the I-V characteristics depending on operation temperature of two-terminal vertical thyristor based capacitorless memory cell. Furthermore, we calculated the change of the bandgap of silicon and the magnitude of schottky barrier between metal emitter and p+-base junction in order to verify the effect of metal emitter on temperature dependency of latch-up and latch-down voltages. In addition, the heat flow and the dependency of the I-V characteristics on the metal emitter were investigated by TCAD simulation. Finally, we present the effect of schottky contact emitter on electrical characteristics in two-terminal vertical thyristor based capacitorless memory. Acknowledgment * This research was supported by Brain Korea 21 PLUS Program in 2019, the MOTIE (Ministry of Trade, Industry & Energy 10069063) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1

Twin Drain Quantum Well/Quantum Dot Channel Spatial Wave-Function Switched (SWS) FETs for Multi-Valued Logic and Compact DRAMs

This paper aims to design and simulate a compact dynamic random access memory (DRAM) cell using two-channel spatial wavefunction switched (SWS) field-effect transistor (FET) and two capacitors. One unit of a SWSFET based DRAM cell stores 2-bits, which reduces the overall cell area by 50% as compared to a conventional 1-bit DRAM cell. SWSFETs have two or more vertically stacked quantum well channels as the transport layer between source and drain. In a two quantum channel n-SWSFET, as the gate voltage is raised above threshold, electrons appear in the lower quantum well W2 and this inversion channel connects Source S2 to drain D2. As the gate voltage is further increased, electrons transfer to upper quantum well W1 and now source S1 and drain D1 are connected electrically. Spatial location of electrons allows us to encode as 4 logic states: no electrons 00, electrons in W2 01, electrons is both wells 10 and electrons in well W1. This property of the SWSFET has been shown to implement multi-valued logic circuits. A SWSFET may have 2-4 sources and drains independently operated or connected together depending upon the logic circuit implementation.

A 1T Dynamic Random Access Memory Cell Based on Gated Thyristor with Surrounding Gate Structure for High Scalability.

In this study, we investigate a one-transistor (1T) dynamic random access memory (DRAM) cell based on a gated-thyristor device utilizing voltage-driven bistability to enable high-speed operations. The structural feature of the surrounding gate using a sidewall provides high scalability with regard to constructing an array architecture of the proposed devices. In addition, the operation mechanism, I-V characteristics, DRAM operations, and bias dependence are analyzed using a commercial device simulator. Unlike conventional 1T DRAM cells utilizing the floating body effect, excess carriers which are required to be stored to make two different states are not generated but injected from the n+ cathode region, giving the device high-speed operation capabilities. The findings here indicate that the proposed DRAM cell offers distinct advantages in terms of scalability and high-speed operations.

Suppression of the Floating-Body Effect of Vertical-Cell DRAM With the Buried Body Engineering Method

Recently, new dynamic random-access memory (DRAM) structures have been used to sharply reduce chip size. One of these is vertical-cell DRAM that has the advantage of reducing the chip area by 33% compared with the conventional cell DRAM. However, since the bitline is made in Si trenches, it can cause a floating-body effect, which increases the OFF current. Here, we suggest the buried body engineering method as a simple way to deal with these disadvantages without changing the materials. This method significantly improved the electrical performance in comparison with the conventional buried contact. Especially, the OFF current, which is the most important factor influencing the refresh time, was dramatically reduced by a factor of 63. The reason for this dramatic decrease in the OFF current is that the holes accumulated in the body are removed immediately, and they do not generate a parasitic bipolar junction transistor (BJT) action. We also calculated the hole density using simulations and obtained the junction depth that suppresses the floating-body effect. Above all, we provide advanced insight into the mechanism of the parasitic BJT action due to the floating-body effect that occurs at the bottom contact region of vertical-cell DRAM.

Effect of Misfit Dislocations in Junctions and Base Thickness on Latch-up Characteristics in Two-Terminal Vertical Thyristor-Based Capacitorless Memory

Conventional dynamic random access memory (DRAM) has been facing a severe challenge to scale down to 10 nm size. The cell capacitor should be able to store sufficient charges of 25~30 fF/cell. In order to meet this requirement, high aspect ratio of cell capacitor is inevitable, resulting in capacitors leaning into each other. To overcome this issue coming from capacitor, the vertical thyristor-based two-terminal capacitorless memory was proposed as a promising candidate to replace current DRAM, which consists of p++-anode / n+-base / p+-base / n++-cathode vertical structure using conventional Si technology. The two-terminal vertical thyristor-based capacitorless memory cell having p++-anode / n+-base / p+-base / n++-cathode vertical structure is easy to construct cross-point memory array cells, as shown in Figure 1. Furthermore, Two-terminal vertical thyristor-based capacitorless memory array cells can be operated without selector since sneak current is suppressed by latch-down process. In our study, three types of two-terminal vertical thyristor-based capacitorless memory cells consist of top-p++-anode / n+-base / p+-base / bottom-n++-cathode with 80-nm-thick base region (PNPN80), top-p++-anode / n+-base / p+-base / bottom-n++-cathode with 160-nm-thick base region (PNPN160), and top-n++-cathode / p+-base / n+-base / bottom-p++-anode with 160-nm-thick base region (NPNP160) were fabricated, individually. The dopant concentration profile of each device was analyzed by secondary ion mass spectroscopy (SIMS), as shown in Figure 2. By correlating HR TEM images with SIMS analyses, misfit dislocations were observed at the depth where dopant pile-up was found, as shown in Figure 3. Figure 4 (a), (b) and (c) show I-V measurements of PNPN80, PNPN160 and NPNP160, respectively. The difference of latch-up voltages between Figure 4 (b) and (c) can be explained by carrier life-time difference. NPNP160 had less misfit dislocations compared to PNPN160, resulting in longer excess carrier life-time, since dislocations act as recombination centers. Thus, NPNP160 needed smaller anode voltage to induce sufficient excess carriers in base regions, which had smaller latch-up voltage than PNPN160. In addition, the difference of latch-up voltages between Figure 4 (a) and (b) resulting from base thickness difference can be explained by electric field. The electric field of PNPN160 is weaker than that of PNPN80 in base regions when equivalent anode voltage is applied. Therefore, PNPN160 needed larger anode voltage to lower the injection barrier of excess carriers. Besides, the effect of misfit dislocations and base dopant concentration on memory margin and off-state leakage current will be discussed. Finally, the memory cell pulse operations will be exhibited as well. Acknowledgment * This research was supported by Brain Korea 21 PLUS Program in 2018, the MOTIE (Ministry of Trade, Industry & Energy 10069063) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1

Editors' Choice—Vertically Integrated Nanowire-Based Zero-Capacitor Dynamic Random Access Memory

This paper demonstrates a breakthrough for DRAM scaling: A vertically integrated gate-all-around (GAA) silicon nanowire (SiNW) channel-based dynamic random access memory (DRAM) without a cell capacitor for data storage, i.e., a zero-capacitor DRAM unlike the conventional DRAM. Vertical integration of the SiNW was attained by a one-route all-dry etching process (ORADEP), resulting in stiction-free stability and simplicity in the fabrication process. High performance that is suitable for high packing density integration is presented with vertically integrated multiple channels, which reveals a potential for an ultimate scaling of DRAM toward the end of the roadmap.

High performance DRAM architecture with split row buffer

In dynamic random access memory (DRAM)-based main memory, access latency is a key performance metric. Commonly, the access latency is improved by employing row buffers that store the most recently accessed row data. However, if a new request tries to access a different row address from that in the row buffer, which is a row buffer conflict, the access latency is significantly increased. In a heterogeneous multi-core system, row buffer conflicts occur frequently because various types of processors with different access patterns share the main memory. A novel DRAM architecture that hides the latency penalty due to row buffer conflicts is proposed. The key idea is that read or write commands serviced during activate and precharge operations for different rows in the same bank are carried out by splitting the row buffer into two buffers. Experimental results show that the proposed DRAM architecture achieves up to 16% higher system performance for memory-intensive applications compared with a conventional DRAM architecture.

Vertically Integrated ZRAM toward Extremely Scaled Memory

Conventional dynamic random access memory (DRAM), which is composed of 1 transistor (1T) and 1 capacitor (1C), has been used as main memory. With the advent of 18 nm DRAM, however, manufacturing of DRAM has been confronted with a few technical challenges for continuous scaling. In particular, the fabrication of a cell capacitor is one of the most insurmountable obstacles for extreme scaling. Under this circumstance, reconsidering a zero capacitor-DRAM (zRAM) that consists of solely 1T is a timely approach. Compared to the conventional DRAM, the main advantages of the zRAM are the cell size reduction and nondestructive reading. Moreover, one of the greatest advantages of the zRAM is that there is no need to make a sense amplifier (S/A) for identifying a data state. This can allow versatile core and periphery circuit architecture. In this regard, the notable increment of data sensing margin (ION /IOFF ) due to the vertically integrated multi-stacked channels, which do not increase a layout area, is very attractive for future DRAM technology. As mentioned above, memory device has considerably been miniaturized for improving productivity as well as performance and lowering fabrication cost. But, suppression of the short-channel effects (SCEs) stemmed from continuous miniaturization has been a crucial concern. Therefore a three-dimensional (3-D) structured transistor has been developed beyond a conventional two-dimensional (2-D) transistor. Among various 3-D structures, a gate-all-around (GAA)-based silicon nanowire (SiNW), which is ranked at the end of the roadmap, showed the strongest gate controllability and thereby effectively suppressed the SCEs. On the contrary, the extreme scaling of the SiNW (e.g., diameter (dNW ) of the SiNW) inevitably sacrifices ION because of increased parasitic resistance and reduced density of 2-D electron gas, even though it is attractive to minimize IOFF . Thus there is no choice but to compromise the controllability of IOFF and the drivability of ION . In this regard, vertically integrated multi-stacked channels can recover the sacrificed ION , which was caused by extremely scaled dNW for the reduction of IOFF . Up to date, there were a few reports to describe the vertical stacking of the SiNWs to provide high performance with good scalability and to suppress the SCEs. As the transition to the next phase, hybrid integration to combine zRAM and the vertically integrated multi-stacked GAA SiNW channels can lead to driving the extremely scaled DRAM for high performance and enlarged memory window even without the S/A. In this work, vertically integrated-zRAM (VI-zRAM) comprised of the GAA SiNW channels, which were implemented to a bulk silicon substrate, is demonstrated for the first time. The vertical stacking of the SiNW, which is the most critical procedure in the entire fabrication, is achieved by employing the one-route all-dry etching process (ORADEP). Unlike previous works, the ORADEP produced the vertically integrated multi-stacked SiNWs without any stiction failure thus it harnessed high controllability and reproducibility with process simplicity, i.e., just one-route etching. Representative images of the VI-zRAM with the GAA SiNW channels that stacked up to five-story, were clearly shown with the aid of high-resolution transmission electron microscopy (TEM) and energy-dispersive X-ray spectroscopy (EDS). In the TEM image, the clear separation of each SiNW fully surrounded by the poly-Si gate proves the complete GAA structure. Undamaged crystallinity of the fabricated SiNW was approved by the fast Fourier transform (FFT) image. Hence it supports that there are no process related defects originated from optimized ORADEP. Compared with the single SiNW channel-based zRAM, ION is threefold increased at the three-story channels and fivefold enhanced at the five-story channels without significant degradation of other device parameters such as IOFF and subthreshold slope. This increase of ION by the number of SiNW without both the sacrifice of other performances and the extra increment of the cell size, allows us to project the ultimate DRAM at the endpoint of the roadmap. In addition, the VI-zRAM showed reliable switching endurance with negligible change of memory characteristics. Thus it is capable of identifying the data state without the S/A. In terms of the chip size reduction, no use of the S/A can increasingly be favored for continuous DRAM scaling. It reveals that additional versatile circuit architecture to replace presumable S/A can be allowed. Throughout the demonstration of the fabricated VI-zRAM by the ORADEP process, it will drive ultimate scaled DRAM technology toward the roadmap end. Figure 1

Vertically Integrated ZRAM toward Extremely Scaled Memory

This paper discusses the demonstration of a vertically integrated gate-all-around (GAA) silicon nanowire (SiNW) channel-based dynamic random access memory (DRAM) without a cell-capacitor as a breakthrough for conventional DRAM scaling. Owing to the one-route all-dry etching process (ORADEP) with stiction-free stability and process simplicity, vertical integration of multiple silicon nanowire was achieved with high uniformity and high reproducibility. Finally, high performance suitable for further scaling was presented in zero-capacitor DRAM (ZRAM) operable with up to five-story SiNW channels without sacrificing scalability.

Energy efficient task allocation for hybrid main memory architecture

Compared with the conventional dynamic random access memory (DRAM), emerging non-volatile memory technologies provide better density and energy efficiency. However, current NVM devices typically suffer from high write power, long write latency and low write endurance. In this paper, we study the task allocation problem for the hybrid main memory architecture with both DRAM and PRAM, in order to leverage system performance and the energy consumption of the memory subsystem via assigning different memory devices for each individual task. For an embedded system with a static set of periodical tasks, we design an integer linear programming (ILP) based offline adaptive space allocation (offline-ASA) algorithm to obtain the optimal task allocation. Furthermore, we propose an online adaptive space allocation (online-ASA) algorithm for dynamic task set where arrivals of tasks are not known in advance. Experimental results show that our proposed schemes achieve 27.01% energy saving on average, with additional performance cost of 13.6%.

Low-Power MCU With Embedded ReRAM Buffers as Sensor Hub for IoT Applications

This paper proposes embedding 256 Kb resistive random-access memory (ReRAM) in a microcontroller unit as a data buffer for communicating with a stand-alone flash memory. In this study, the chip was manufactured using a combination of the TSMC 0.18 $ \mu{\rm m}$ process and the Industrial Technology Research Institute ReRAM back-end-of-line process. The ReRAM was equipped with a novel sense amplifier that had three magnification times for the reference cell current for increasing the read yield by 32%. Furthermore, the ReRAM controller included built-in self-test, built-in self-repair, a shortened Bose–Chaudhuri–Hocquenghem (99, 64, 5) error-correlating code, and asymmetric coding can yield ReRAM up to approximately 100%. When compared with the conventional dynamic random-access memory (DRAM) buffer, the proposed architecture reduces the system execution time by 25% and the power consumption by 15% at 25 MHz. Simulations also showed that the ReRAM buffering runs at least 51% faster when compared with the use of other nonvolatile memories such as ferroelectric RAM, phase change RAM, and conduct-bridge RAM. Although ReRAM buffering is just competitive in speed and power consumption of spin-transfer torque magnetorresistive RAM buffering, ReRAM has clear advantages in area, cost, and reliability.