Conventional DRAM Research Articles

First demonstration of 2T0C-FeDRAM: a-ITZO FET and double gate a-ITZO/a-IGZO FeFET with a record-long multibit retention time of >4-bit and >2000 s.

Conventional DRAM, consisting of one transistor and one capacitor (1T1C), requires periodic data refresh processes due to its limited retention time and data-destructive read operation. Here, we propose and demonstrate a novel 3D-DRAM memory scheme available with a single transistor and a single ferroelectric field-effect transistor (FeFET) DRAM (2T0C-FeDRAM), which offers extended retention time and non-destructive read operation. This architecture uses a back-end-of-line (BEOL)-compatible amorphous oxide semiconductor (AOS) that is suitable for increasing DRAM cell density. Notably, the device structures of a double gate a-ITZO/a-IGZO FeFET, used for data storage and reading, are engineered to achieve an enlarged memory window (MW) of 1.5 V and a prolonged retention time of 104 s. This is accomplished by a double gate and an a-ITZO/a-IGZO heterostructure channel to enable efficient polarization control in hafnium-zirconium oxide (HZO) layers. We present successful program/erase operations of the double gate a-ITZO/a-IGZO FeFET through incremental step pulse programming (ISPP), demonstrating multi-level states with remarkable retention characteristics. Most importantly, we perform 2T0C-FeDRAM operations by electrically connecting the double gate a-ITZO/a-IGZO FeFET and the a-ITZO FET. Leveraging the impressive performance of the double gate a-ITZO/a-IGZO FeFET technology, we have effectively showcased an exceptionally record-long retention time exceeding 2000 s and 4-bit multi-level states, positioning it as a robust contender among emerging memory solutions in the era of artificial intelligence.

Design and analysis of gate all around stacked nanosheet-DRAM for future technology node

This paper reports a stacked Dynamic random-access transistor (DRAM) memory structure that is based on gate all-around nanosheet access transistor. A TCAD study is done to compare nanosheet DRAM and conventional saddle fin recessed channel access transistor (SRCAT) in terms of DRAM electrical characteristics and its row hammer-induced leakage. The nanosheet DRAM shows superior characteristics in terms of current driving capability, speed, and refresh than SRCAT. The nanosheet DRAM also shows significantly lower hammer-induced failure as compared to SRCAT because the original leakage path from the cell to the neighboring cell gets blocked due to the nanosheet device structure. We also investigate the effect of spacer length on nanosheet DRAM characteristics and show that extended spacer length is favorable for having better DRAM characteristics due to the floating body effect. Our study demonstrates the potential, and advantages of nanosheet DRAM architecture compared to the conventional SRCAT DRAM.

NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching

Deep neural network (DNN) implementations are typically characterized by huge datasets and concurrent computation, resulting in a demand for high memory bandwidth due to intensive data movement between processors and off-chip memory. Performing DNN inference on general-purpose cores/edge is gaining attraction to enhance user experience and reduce latency. The mismatch in the CPU and conventional DRAM speed leads to under-utilization of the compute capabilities, causing increased inference time. 3D DRAM is a promising solution to effectively fulfill the bandwidth requirement of high-throughput DNNs. However, due to high power density in stacked architectures, 3D DRAMs need dynamic thermal management (DTM), resulting in performance overhead due to memory-induced CPU throttling. We study the thermal impact of DNN applications running on a 3D DRAM system, and make a case for a memory temperature-aware customized prefetch mechanism to reduce DTM overheads and significantly improve performance. In our proposed NeuroCool DTM policy, we intelligently place either DRAM ranks or tiers in low power state, using the DNN layer characteristics and access rate. We establish the generalization of our approach through training and test datasets comprising diverse data points from widely used DNN applications. Experimental results on popular DNNs show that NeuroCool results in a average performance gain of 44% (as high as 52%) and memory energy improvement of 43% (as high as 69%) over general-purpose DTM policies.

Rethinking DRAM's Page Mode With STT-MRAM

STT-MRAM is a promising candidate for drop-in replacement for DRAM-based main memory because of its higher energy efficiency and similar latency to DRAM. However, simply replacing DRAM with STT-MRAM without optimizations severely limits STT-MRAM from exploiting its full potential. STT-MRAM employs costly sense amplifiers that demand an order of magnitude more area and power than DRAM. To manage the high cost, STT-MRAM shares one sense amplifier across multiple bit-lines, exploiting the non-destructive nature of its read operation. This sense amplifier sharing reduces the size of row buffers; as a result, it incurs higher activation energy and lower performance. Other issues arise if STT-MRAM is required to be compatible with DRAM interfaces and policies. To address these challenges in a cost-effective manner, we propose SMART that, unlike DRAM and conventional STT-MRAM, waits to do bit-line sensing until after receiving a column access command instead of a row activation command. This results in several benefits: larger pages, fewer sense amplifiers, lower activation power, higher bank-level parallelism, shorter latency, fewer address pins, and more efficient repairing of defective columns than conventional STT-MRAM. Our evaluation shows that SMART consumes lower energy while providing higher performance than conventional STT-MRAM and DRAM. Additionally, SMART consumes less area compared to conventional STT-MRAM.

Adaptive Regression Prefetching Algorithm by Using Big Data Application Characteristics

This paper presents an innovative prefetching algorithm for a hybrid main memory structure, which consists of DRAM and phase-change memory. To enhance the efficiency of hybrid memory hardware in serving big data technologies, the proposed design employs an application-adaptive algorithm based on big data execution characteristics. Specifically optimized for graph-processing applications, which exhibit complex and irregular memory access patterns, a dual prefetching scheme is proposed. This scheme comprises a fast-response model with low-cost algorithms for regular memory access patterns and an intelligent model based on an adaptive Gaussian-kernel-based machine-learning prefetch engine. The intelligent model can acquire knowledge from real-time data samples, capturing distinct memory access patterns via an adaptive Gaussian-kernel-based regression algorithm. These methods allow the model to self-adjust its hyperparameters at runtime, facilitating the implementation of locally weighted regression (LWR) for the Gaussian process of irregular access patterns. In addition, we introduced an efficient hybrid main memory architecture that integrates two different kinds of memory technologies, including DRAM and PCM, providing cost and energy efficiency over a DRAM-only memory structure. Based on the simulation-based experimental results, our proposed model achieved performance enhancement of 57% compared to the conventional DRAM model and of approximately 12% compared to existing prefetcher-based models.

1T DRAM with Raised SiGe Quantum Well for Sensing Margin Improvement

In this paper, a novel one-transistor dynamic random-access memory (1T DRAM) with a raised SiGe quantum well (QW) under one gate in the double-gate (DG) structure is proposed. The proposed structure can improve the poor performance of the retention time and sensing margin which is the problem of the conventional 1T DRAM. In write operation, the performance is improved through the band to band tunneling (BTBT) between body and drain and through valence band offset between SiGe and Si. Also by utilizing the physical barrier of oxide, read “1” retention time can be increased. The fabrication process is also proposed.

Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories

Main memory system design and corresponding technology requirements have become increasingly challenging for data-dominated high-performance applications. To address the leakage and scalability issues of the conventional DRAM-based memory, new memory technologies with ultra-low leakage and potential for high scalability have been explored extensively over the last decade. However, none of them are mature enough to serve as a drop-in replacement for DRAM. In this paper, we propose a hybrid main memory system solution for utilizing new memory technologies with specific features, based on the target application characteristics and system configurations. To this end, we examine two new memories, 1S-1VCMA and IGZO-based DRAM, along with conventional DRAM in the context of hybrid main memory solutions for high-capacity and low-power Pareto-optimizations, respectively. To better evaluate the power and performance, we consider the page-fault modeling in our evaluations. The results of the simulation show that different combinations of memory technologies in the hybrid memory system, different memory capacities, and different storage systems could provide a promising solution in the system regarding the characteristics of running applications and the requirements of the system.

A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder

DRAM latency has remained almost constant over decades and has become a performance bottleneck of computing systems. In this study, we propose a low-cost DRAM architecture enabling dynamic reconfiguring of row decoder to provide reduced latency with high flexibility and reliability. We apply minimum changes to row decoders and allow dynamic reconfiguration to switch array blocks between two modes: 1) normal mode, where the DRAM array behaves in the same manner as the conventional DRAM does and 2) low latency mode, where two DRAM cells in the neighbor array blocks are coupled to operate as a logical cell and reduce latency reliably according to the differential principle. On the basis of an industrial open bitline (BL) cell array, we only change the word-line decoding scheme but keep the cell array and sense amplifiers (SAs) untouched to avoid modifications to the DRAM process for cost and reliability considerations. Our circuit simulation shows that the low-latency mode can reduce row-to-column delay and row access strobe time by 25.7% and 23.2%, respectively. We evaluate the reduced-latency LPDDR4 DRAM on various workloads. Compared with the JEDEC standard DRAM, our proposal provides a maximum system performance improvement of 8.5%. We believe that our proposal is a reliable and cost-friendly solution to DRAM latency reduction.

A Novel Capacitorless 1T DRAM with Embedded Oxide Layer.

A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively used to improve the retention time by reducing the recombination rate of stored holes and sensing electrons. Based on TCAD simulations, the new structure is predicted to not only have the characteristics of fast access, random read and integration of 4F2 cell, but also to realize good retention and deep scaling. At the same time, the new structure has the potential of scaling compared with the conventional capacitorless 1T DRAM.

Design and analysis of dopingless 1T DRAM using work function engineered tunnel field effect transistors

In this paper, a dopingless DRAM based on work function engineered Tunnel field effect transistor is proposed. Gate metal workfunction engineering is done to enhance ON/OFF current ratio of drain current, thereby improving the sense margin and retention time. Drain electrode is made up of dual metal, so as to suppress ambipolar current. The analysis of dual material gate dual drain electrode DRAM (DMG DDE DRAM) and triple material gate dual drain electrode DRAM (TMG DDE DRAM) is done in terms of retention time and sense margin. The performance parameters with different device dimensions and bias conditions are analyzed. It is observed that the proposed DRAMs work well even when the dimensions are scaled down. In addition, the proposed DRAMs have comparable performance with the conventional DRAMs and provide better performance when compared with other dopingless DRAM. Retention times of 430 ms and 370 ms, sense margins of 130 nA and 101 nA are achieved with TMG DDE DRAM and DMG DDE DRAM respectively.

An Approximate DRAM Design with an Adjustable Refresh Scheme for Low-power Deep Neural Networks

A DRAM device requires periodic refresh operations to preserve data integrity, which incurs significant power consumption. Slowing down the refresh rate can reduce the power consumption; however, it may cause a loss of data stored in a DRAM cell, which affects the correctness of computation. This paper proposes a new memory architecture for deep learning applications, which reduces the refresh power consumption while maintaining accuracy. Utilizing the error-tolerant property of deep learning applications, the proposed memory architecture avoids the accuracy drop caused by data loss by flexibly controlling the refresh operation for different bits, depending on their criticality. For data storage in deep learning applications, the approximate DRAM architecture reorganizes the data so that these data are mapped to different DRAM devices according to their bit significance. Critical bits are stored in more frequently refreshed devices while non-critical bits are stored in less frequently refreshed devices. Compared to the conventional DRAM, the proposed approximate DRAM requires only a separation of the chip select signal for each device in a DRAM rank and a minor change in the memory controller. Simulation results show that the refresh power consumption is reduced by 66.5 % with a negligible accuracy drop on state-of-the-art deep neural networks.

Sustainable disturbance crosstalk mitigation in deeply scaled phase-change memory

While Phase Change Memory (PCM) is gaining popularity in next generation systems compared to conventional DRAM and Flash, write disturbance due to crosstalk remains a significant challenge to PCM performance and reliability. To address this concern we propose a multi-tiered compression (MTC) technique combined with novel encoding that can decrease the probability of write disturbance. MTC compresses a high proportion (>94%) of cachelines by a small predictable amount (e.g., 40- or 56-bits of a 512-bit block) while maintaining data similarity vital for optimizing PCM writes. By detecting data patterns prone to crosstalk, we use encoding, correction pointers, and a hybrid approach to reduce the instances of write disturbance. We use MTC reclaimed bits to store the encoding. Thus, our approach requires only five additional auxiliary bits per 512-bit cacheline, minimizing the embodied energy (fabrication) overhead to mitigate write disturbance. Additionally, through a multi-objective optimization, dramatic endurance improvements are possible while maintaining nearly all write disturbance improvement.Our technique improves performance, endurance and write energy by 47%, 42% and 36% versus the state-of-the-art with nominal (circa 1%) increases to embodied energy. When considering the full life-cycle impact, the additional area of our MTC with encoding approach is mitigated by the use-phase benefits within 60 days for a high performance system and in less than four years of use for a desktop system. In nearly all studied scenarios, the improved lifetime provided by our MTC and encoding approach easily recoups the required additional upfront manufacturing energy.

Investigation on junctionless floating body DRAMs including Trap Assisted Tunneling

Junctionless Transistors (JL) and One-Transistor (1T) DRAMs are concepts that come out in order to improve the scalability of logic and volatile memories, respectively. In some recent papers, Floating Body (FB) DRAMs (a class of 1T-DRAM) and JL transistors have been joined in order to propose a solution to overcome the scaling limit of the conventional 1T-1C DRAM cells. In this paper they are discussed in detail the physics of operation and the performances of FB-DRAM cells based on JL transistors including the effect of Trap-Assisted-Tunneling (TAT), neglected in most of previous works. As expected, TAT severely limits the retention time due to the large doping, in particular during HOLD operation. The discussion is supported by 2D device simulation on a double gate junctionless transistor including the effect of statistical variability induced by random dopant fluctuations, and the technology (bandgap, lifetime) scaling. It is found that the cell, at least at the nanoscale, can work only by independent gate operation, having maximum performance when the bottom gate works at the limit of the BBT bias region during READ, and that at a gate length as large as 100 nm and fin width of 10 nm the cell can sustain the high doping induced variability to a retention time in the order of 1 ms, while the use of materials with higher bandgap (~1.3 eV) than Silicon can improve the retention time to the order of 10 ms. However several concerns remain on their actual use related to the necessary bias level and to the impact of the actual technologies on the lifetime, which strongly affects TAT degradation.

Access pattern-based high-performance main memory system for graph processing on single machines

With the increasing complexity of graph structures, the current real-world large-scale graphs are being represented by a considerable amount of vertex and edge data. Furthermore, the analysis of a large number of computing nodes has become a very complicated job that requires a large amount of hardware resources. Moreover, in large-scale graph processing, the vertex and edge data show random and sequential memory access patterns at the same time, and this is a major bottleneck in graph processing. In this paper, we present a high-capacity main memory system with an intelligent pattern-aware prefetching engine to overcome the scalability problem and the memory inefficiency of single-machine graph processing. The proposed intelligent pattern-aware prefetching engine is designed to predict and handle sequential or regular patterns and random-access patterns simultaneously. Experimental results demonstrated that the proposed model exhibited performance improvements of 60% over conventional DRAM models, approximately 40% over the existing prefetch models, and about 12.5% over the latest prefetch models.

NoM: Network-on-Memory for Inter-Bank Data Transfer in Highly-Banked Memories

Data copy is a widely-used memory operation in many programs and operating system services. In conventional computers, data copy is often carried out by two separate read and write transactions that pass data back and forth between the DRAM chip and the processor chip. Some prior mechanisms propose to avoid this unnecessary data movement by using the shared internal bus in the DRAM chip to directly copy data within the DRAM chip (e.g., between two DRAM banks). While these methods exhibit superior performance compared to conventional techniques, data copy across different DRAM banks is still greatly slower than data copy within the same DRAM bank. Hence, these techniques have limited benefit for the emerging 3D-stacked memories (e.g., HMC and HBM) that contain hundreds of DRAM banks across multiple memory controllers. In this paper, we present Network-on-Memory (NoM), a lightweight inter-bank data communication scheme that enables direct data copy across both memory banks of a 3D-stacked memory. NoM adopts a TDM-based circuit-switching design, where circuit setup is done by the memory controller. Compared to state-of-the-art approaches, NoM enables both fast data copy between multiple DRAM banks and concurrent data transfer operations. Our evaluation shows that NoM improves the performance of data-intensive workloads by 3.8X and 75%, on average, compared to the baseline conventional 3D-stacked DRAM architecture and state-of-the-art techniques, respectively.

В ожидании нативных архитектур СУБД на основе энергонезависимой основной памяти

Many experts in the field of data management believe that the emergence of non-volatile byte-addressable main memory (NVM) available for practical use will lead to the development of a new type of ultra-high-speed database management systems (DBMS) with single-level data storage (native in-NVM DBMS). However, the number of researchers who are actively engaged in research of architectures of native in-NVM DBMS has not increased in recent years. The most active researchers are PhD students that are not afraid of the risks, which, of course, exist in this new area. The second section of the article discusses the state of the art in NVM hardware. The analysis shows that NVM in the DIMM form factor has already become a reality, and that in the near future we can expect the appearance on the market NVM-DIMMs with the speed of conventional DRAM and endurance close to that of hard drives. The third section is devoted to the review of related works, among which the works of young researchers are the most advanced. In the fourth section, we state and justify that the work performed so far in the field of in-NVM DBMS, did not lead to the emergence of a native architecture. This is hampered by the set of limiting factors analyzed by us. In this regard, in the fifth section, we present a sketch of the native architecture of an in-NVM DBMS, the choice of which is influenced only by the goals of simplicity and efficiency. In conclusion, we summarize the article and argues the need for additional research into many aspects of the native architecture of an in-NVM DBMS.

DR Refresh: Releasing DRAM Potential by Enabling Read Accesses Under Refresh

Emerging data analytic workloads such as graph processing, neural network and edge data preprocesing desire efficient memory read operations. Unfortunately, due to the necessity of dynamic refresh, modern DRAM systems have to stall access during refresh cycles. As DRAM device density continues to grow, refresh operations can be a crucial throughput bottleneck. To fully unleash memory access performance, we revisit conventional refresh mechanism and DRAM architecture. We propose DR refresh, a specific refresh mechanism that enable read and refresh operations to be done simultaneously. We devise DR DRAM, a specific memory hardware system that can efficiently deploy DR refresh. Unlike traditional refresh, DR explores device refresh that only refreshes a designated device at a time. Meanwhile, DR increases read efficiency by recovering the inaccessible data that resides on a device under refreshing. We also propose Hybrid Refresh Main Memory (HRMM) which can designate refresh schemes (DR or traditional refresh) in a specific memory space. We expect that our design can benefit many real-life tasks such as SPEC CPU2006, CNN, LLT and PageRank.

Analysis of operation characteristics of junctionless poly-Si 1T-DRAM in accumulation mode

Capacitorless DRAM (1T-DRAM) is considered to be a promising candidate to replace conventional 1T-1C DRAM which is facing a scaling limit. 1T-DRAM with a poly-Si body has attracted much attention specifically for its simple SOI fabrication and stackable memory which allow for ultrahigh density. A single crystal silicon-based junctionless (JL) transistor is unsuitable for a 1T-DRAM cell because the transistor’s body is too thin to have a storage region and its junction barrier is too low to store holes. In contrast, a JL transistor with a thin poly-Si body can be used as a 1T-DRAM cell because it uses a grain boundary as its charge storage region instead of a floating body. We carried out intensive simulations of JL transistors with poly-Si body and confirmed the possibility of using a JL structure as a poly-Si 1T-DRAM cell. In addition, we analyzed the memory mechanism and characteristics of this structure.

A Gated Diode DRAM Cell for Improved Power and Speed

In this paper performance analysis of Gated diode based Dynamic Random Access Memory (GD-DRAM) cell is compare with capacitor based DRAM cell in terms of average power dissipation, propagation delay, read access time and write access time at 250nm technology. The GD-DRAM is also referred as capacitorless DRAM. This gated diode stored data in DRAM which is an alternative solution to capacitor. This gated diode DRAM shows cutback in leakage and access time as compared to capacitor based DRAM. A gated diode is formed by shorting two terminal of MOS transistor i.e. source and drain. When the voltage Vgs is higher than knee voltage Vth; then data get stored on it. Nowadays dynamic random access memory is highly attracting market as compared static RAM because of its high package density, low cost and small area. In this paper this gated diode also resolves the issue of fabrication of capacitor in conventional DRAM cell. The major problem associated with DRAM is power dissipation. The above cells were designed and simulated in Tanner EDA tool and their results were analyzed at 250μm technology. Here we investigated that gated diode based DRAM has superior performance in terms of read time, write time and average power dissipation.

Thermal-aware processing-in-memory instruction offloading

With the advent of die stacking technology and big data applications, Processing-in-memory (PIM) is regaining attention as a promising technology for improving performance and energy efficiency. Although various PIM techniques have been proposed in recent studies for effectively offloading computation from the host, the thermal impacts of PIM offloading have not been fully explored. This paper investigates the thermal constraints of PIM and proposes techniques to enable thermal awareness for efficient PIM offloading. To understand the thermal effects of 3D-stacked designs, we measure the temperature of a real Hybrid Memory Cube (HMC) prototype and observe that compared to conventional DRAM, HMC reaches a significantly higher operating temperature, which causes thermal shutdowns with a passive cooling solution. Even with a commodity-server cooling solution, when in-memory processing is highly utilized, HMC fails to maintain the temperature of the memory dies within the normal operating range. In this paper, we propose a collection of software- and hardware-based techniques to enable thermal-aware PIM offloading by controlling the intensity of PIM offloading at runtime. Our evaluation results show that the proposed techniques achieve up to 1.4 × and 1.37× speedups compared to non-offloading and naïve offloading scenarios.