Conventional Current Mode Logic Research Articles

A Hybrid Transmitter With Voltage-Mode SST Preemphasis and Current-Mode Transmitter Equalization Capable of Operating at 77 K in DUNE

The Deep Underground Neutrino Experiment (DUNE) requires that the front-end transmitters operate at cryogenic temperature and drive 25–35 m long twin-axial (twinax) cables. To compensate the frequency-dependent channel loss over the long cables and alleviate the de-emphasizing of the low-frequency signal magnitude, a hybrid of a current-mode (CM) transmitter equalization (TXEQ) and a voltage-mode (VM) preemphasis is proposed. The TXEQ employs a finite-impulse response (FIR) filter to boost the high-frequency components while de-emphasizing the low-frequency signal magnitude, thereby flattening the overall channel frequency response and reducing the intersymbol interference (ISI). The VM preemphasis is proposed to further mitigate ISI by boosting the high-frequency portion without degrading the signal magnitude, allowing for high signal swing. The main driver utilizes VM source-series-terminated (SST) output stages, which offers higher signal swing and better power efficiency than the conventional CM logic (CML) drivers. To ensure the lifetime and reliability at cryogenic temperature, the transmitter is implemented in a 65-nm CMOS process operating at 1.1 V of supply voltage and employing transistors with larger than minimum lengths. Silicon measurement results at 77 K have validated the proposed approaches.

A Novel CML Latch-Based Wave-Pipelined Asynchronous SerDes Transceiver for Low-Power Application

In the present technology development billions of transistors are fabricated on a single chip, which improves the performance of circuits in terms of high data transmission speed and power consumption. This requirement of data transmission speed is achieved with the help of high-speed transceivers. In this paper, we present a high-speed asynchronous wave-pipelined serializer and deserializer (SerDes) transceiver implemented using current-mode logic (CML). This asynchronous transceiver circuit does not require a clock and therefore it saves large amount of power which is consumed in the phase locked loop (PLL) and frequency synthesizer circuits. Further, the proposed design is built using CML which saves more power. CML circuit operates at relatively higher speed as compared to CMOS circuits which helps the circuit to operate at higher data rate. Compared to conventional CML latch, a novel CML latch is proposed in our design to increase the speed. The circuit is implemented in standard CMOS 65-nm technology. The total power consumed by the serializer and deserializer is 9.32[Formula: see text]mW, which is very less as compared to published related works. The proposed asynchronous SerDes transceiver operates at 18.1-Gbps data transmission rate with low power dissipation.

An improved current mode logic latch for high‐speed applications

SummaryIn this paper, an improved current mode logic (CML) latch design is proposed for high‐speed on‐chip applications. Transceivers use various methods in fast data transmission in wireless/wire‐line application. For an asynchronous transceiver, the improved CML latch is designed using additional NMOS transistors in conventional CML latch which helps to boost the output voltage swing. The proposed low‐power CML latch‐based frequency divider is compatible for higher operating frequency (16 GHz). Next, the delay model is also developed based on small signal equivalent circuit for the analysis of the proposed latch. The output voltage behavior of the proposed latch is analyzed using 180‐nm standard CMOS technology.

A Current-mode Logic Driver with Two-tap Pre-emphasis using Reconfigurable Capacitive Peaking for -12.3 dB Insertion Loss

This paper proposes a 10-Gb/s output driver based on Current-Mode Logic (CML) driver with 2-tap including pre-emphasis and de-emphasis method by using reconfigurable capacitive peaking. The proposed is implemented in 55-nm CMOS process with 1.2 V supply. The proposed output driver can compensate for insertion loss -12.3 dB just with 2-tap and controlling the number of capacitor that is able to change pre-emphasis gain. Additionally, the de-emphasis gain is able to be changed by using 2-tap current source. Thus, the proposed achieves about 3.8 times higher gain than the conventional CML driver and evenly reduces power consumption up to 56.32% compared the conventional CML driver with the same of number of taps.

A power-efficient switchable CML driver at 10 Gbps

High static power limits the application of conventional current-mode logic(CML). This paper presents a power-efficient switchable CML driver, which achieves a significant current saving by 75% compared with conventional ones. Implemented in the 130 nm CMOS technology process, the proposed CML driver just occupies an area about 0.003 mm2 and provides a robust differential signal of 1600 mV for 10 Gbps optical line terminal (OLT) with a total current of 10 mA. The peak-to-peak jitter is about 4 ps (0.04TUI) and the offset voltage is 347.2 mV @ 1600 mVPP.

Analysis of Nonlinearities in Injection-Locked Frequency Dividers

The locking range of injection-locked frequency dividers is investigated and it is shown that the presence of nonlinearities, such as those exhibited in a current mode logic (CML) D flip-flop (DFF)-based divider, can result in a wider frequency locking range. A new approach to evaluate such nonlinearities is described. A new divider topology benefiting from the nonlinearity is presented that exhibits both higher operating frequencies and similar locking range compared to the conventional CML DFF-based topology. The chip was fabricated through a TSMC 90-nm CMOS process.

A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain

A process-variation resilient current mode logic (CML) is presented. The proposed CML employs time-reference-based adaptive biasing chain with replica load to address performance degradation over the process variations. It adjusts variable load resistor to simultaneously regulate time constant, voltage swing, level shifting, and DC gain. The prototype demonstrates the process-variation resiliency of the proposed solution by showing performance degradation over the process corners. Over 20% of polygate resistance variation, the proposed CML suppresses the degradation of speed and rms jitter less than 4.3% and 0.15 ps while conventional CML results in 13% and 3.8-ps degradation, respectively.

Current adjustable clock distribution network scheme for GDDR5

Presented is a current adjustable clock distribution network for GDDR5. In general, GDDR5 uses a current mode logic (CML) buffer as the global driver of the clock distribution. The wide-frequency range conventional CML buffer is designed to the fastest frequency. However, the CML buffer consumes constant current at all frequencies. For this reason, the conventional buffer dissipates current more than necessary at low frequencies. A proposed current adjustable clock distribution network scheme adjusts the amount of the current consumption of the global driver according to the clock frequency. The proposed scheme is implemented in 65 nm CMOS technology, reduces power consumption by 17.7% in the wide frequency range from an average 10.26 mW of the conventional scheme to 8.44 mW.

A 14-GHz AC-Coupled Clock Distribution Scheme With Phase Averaging Technique Using Single LC-VCO and Distributed Phase Interpolators

In this paper, we report the world's first ac-coupled clock distribution circuit for low-power and high-frequency clock distribution. By employing the proposed ac-coupled LC-based voltage-controlled oscillator (LC-VCO) and phase interpolators, the use of conventional current-mode-logic (CML) buffers with large power requirements can be prevented, and power consumption for clock distribution can be reduced. With the aim of verifying the effectiveness of the proposed circuit, test chips were designed and fabricated in 0.18- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex></formula> m mixed-signal CMOS technology. The measured results indicated a 14.007 GHz clock distribution to four points whose pitches are 450 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex> </formula> m, with 6.9 mW of power. The phase noise was measured to be <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex></formula> 79.06 dBc/Hz at a 100 kHz offset, <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex> </formula> 101.66 dBc/Hz at a 1 MHz offset, and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$-$</tex></formula> 107.25 dBc/Hz at a 10 MHz offset, with a clock frequency of 12.96 GHz. Furthermore, a phase averaging technique for reducing phase deviation was proposed and theoretically investigated.

Low-Blind-Period Differential Sampler for High-Speed Serial Link Receivers

This brief presents techniques to reduce the blind period of a sampler in high-speed serial link receivers. The impact of the blind period on receiver performance is first investigated. A conventional current-mode logic (CML) master/slave latch-based sampler is reviewed and simulated, followed by the theoretical analysis of the root causes of the sampler blind period. Finally, a proposed sampler is presented with the transistor-level simulation results in a 32-nm silicon-on-insulator process. Operating at 10 Gb/s, the proposed sampler, consuming approximately 25% less current than the conventional CML sampler, exhibits a blind period of approximately 2 ps for the eye height of 40 mV, whereas the conventional CML sampler exhibits a blind period of 33 ps under the same condition.

Design of ultrahigh-speed low-voltage CMOS CML buffers and latches

A comprehensive study of ultrahigh-speed current-mode logic (CML) buffers along with the design of novel regenerative CML latches will be illustrated. First, a new design procedure to systematically design a chain of tapered CML buffers is proposed. Next, two new high-speed regenerative latch circuits capable of operating at ultrahigh-speed data rates will be introduced. Experimental results show a higher performance for the new latch architectures compared to the conventional CML latch circuit at ultrahigh-frequencies. It is also shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.