A 14-GHz AC-Coupled Clock Distribution Scheme With Phase Averaging Technique Using Single LC-VCO and Distributed Phase Interpolators

Abstract

In this paper, we report the world's first ac-coupled clock distribution circuit for low-power and high-frequency clock distribution. By employing the proposed ac-coupled LC-based voltage-controlled oscillator (LC-VCO) and phase interpolators, the use of conventional current-mode-logic (CML) buffers with large power requirements can be prevented, and power consumption for clock distribution can be reduced. With the aim of verifying the effectiveness of the proposed circuit, test chips were designed and fabricated in 0.18- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex></formula> m mixed-signal CMOS technology. The measured results indicated a 14.007 GHz clock distribution to four points whose pitches are 450 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex> </formula> m, with 6.9 mW of power. The phase noise was measured to be <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex></formula> 79.06 dBc/Hz at a 100 kHz offset, <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex> </formula> 101.66 dBc/Hz at a 1 MHz offset, and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$-$</tex></formula> 107.25 dBc/Hz at a 10 MHz offset, with a clock frequency of 12.96 GHz. Furthermore, a phase averaging technique for reducing phase deviation was proposed and theoretically investigated.