Conventional Complementary Metal Oxide Semiconductor Research Articles

Tunable magnetic synapse for reliable neuromorphic computing

Artificial neural networks (ANNs), inspired by the structure and function of the human brain, have achieved remarkable success in various fields. However, ANNs implemented using conventional complementary metal oxide semiconductor technology face significant limitations. This has prompted exploration of nonvolatile memory technologies as potential solutions to overcome these limitations by integrating storage and computation within a single device. These emerging technologies can retain resistance values without power, allowing them to serve as analog weights in ANNs, mimicking the behavior of biological synapses. While promising, these nonvolatile devices often exhibit inherent nonlinear relationships between resistance and applied voltage, complicating training processes and potentially impacting learning accuracy. This article proposes a magnetic synapse device based on the spin–orbit torque effect with geometrically controlled linear and nonlinear response characteristics. The device consists of a magnetic multilayer stack patterned into a designed shape, where the width variation along the current flow direction allows for controllable magnetic domain wall propagation. Through finite element method simulations and experimental studies, we demonstrate that by engineering the device geometry, a linear relationship between the applied current and the resulting Hall resistance can be achieved, mimicking the desired linear weight-input behavior in artificial neural networks. Additionally, this study explores the influence of current pulse width on the response curves, revealing a deviation from linearity at longer pulse durations. The geometric tunability of the magnetic synapse device offers a promising approach for realizing reliable and energy-efficient neuromorphic computing architectures.

Hybrid Quantum-Dot Cellular Automata Nanocomputing Circuits

Quantum-dot cellular automata (QCA) is an emerging transistor-less field-coupled nanocomputing (FCN) approach to ultra-scale ‘nanochip’ integration. In QCA, to represent digital circuitry, electrostatic repulsion between electrons and the mechanism of electron tunnelling in quantum dots are used. QCA technology can surpass conventional complementary metal oxide semiconductor (CMOS) technology in terms of clock speed, reduced occupied chip area, and energy efficiency. To develop QCA circuits, irreversible majority gates are typically used as the primary components. Recently, some studies have introduced reversible design techniques, using reversible majority gates as the main building block, to develop ultra-energy-efficient QCA circuits. However, this approach resulted in time delays, an increase in the number of QCA cells used, and an increase in the chip area occupied. This work introduces a novel hybrid design strategy employing irreversible, reversible, and partially reversible QCA gates to establish an optimal balance between power consumption, delay time, and occupied area. This hybrid technique allows the designer to have more control over the circuit characteristics to meet different system needs. A combination of reversible, irreversible, and innovative partially reversible majority gates is used in the proposed hybrid design method. We evaluated the hybrid design method by examining the half-adder circuit as a case study. We developed four hybrid QCA half-adder circuits, each of which simultaneously incorporates various types of majority gates. The QCADesigner-E 2.2 simulation tool was used to simulate the performance and energy efficiency of the half-adders. This tool provides numerical results for the circuit input/output response and heat dissipation at the physical level within a microscopic quantum mechanical model.

Enhancement noise margin and delay time performance of novel punch-through nMOS for single-carrier CMOS

In this paper, we propose the use of punch-through nMOS (PTnMOS) as an alternative to pMOS in complementary metal oxide semiconductor (CMOS) circuits. According to the TCAD simulation results, PTnMOS exhibit sub-threshold characteristics similar to those of pMOS and can be formed by simply changing the doping concentration of the source and drain. Without the need for sizing, which solves the area occupation problem caused by the need to increase the width of pMOS due to insufficient hole mobility. In addition, we compose a PTnMOS and nMOS without sizing to form a single-carrier CMOS in which only electrons are transmitted, and We extract its performance for comparison with conventional CMOS (Wp/Wn = 1). The results indicate that single-carrier CMOS has symmetric noise margin and 29% faster delay time compared to conventional CMOS (Wp/Wn = 1). If III–V or II–VI group materials could be applied to single-carrier CMOS, not only could costs be reduced and wafer area occupancy minimized, but also significant improvements in the performance and bandwidth application of microwave circuits could be achieved.

Experimental demonstration of an on-chip p-bit core based on stochastic magnetic tunnel junctions and 2D MoS2 transistors

Probabilistic computing is a computing scheme that offers a more efficient approach than conventional complementary metal-oxide–semiconductor (CMOS)-based logic in a variety of applications ranging from optimization to Bayesian inference, and invertible Boolean logic. The probabilistic bit (or p-bit, the base unit of probabilistic computing) is a naturally fluctuating entity that requires tunable stochasticity; by coupling low-barrier stochastic magnetic tunnel junctions (MTJs) with a transistor circuit, a compact implementation is achieved. In this work, by combining stochastic MTJs with 2D-MoS2 field-effect transistors (FETs), we demonstrate an on-chip realization of a p-bit building block displaying voltage-controllable stochasticity. Supported by circuit simulations, we analyze the three transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how the characteristics of each component influence the overall p-bit output. While the current approach has not reached the level of maturity required to compete with CMOS-compatible MTJ technology, the design rules presented in this work are valuable for future experimental implementations of scaled on-chip p-bit networks with reduced footprint.

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

Fundamental to digital signal processing applications such as the Arithmetic Logic Unit (ALU), logic gates serve as the foundational components. This paper presents NOR and NAND gates engineered for operation within the ultra-low voltage (LV) and low power domains (LP). Utilizing the floating gate MOSFET (FGMOS) approach, this study adopts a strategy to enhance performance, focusing on reducing design complexity and minimizing power consumption.The proposed FGMOS-NAND/NOR gate design is investigated for important device parameters such as power (pwr), delay (tp), power delay product (PDP), and energy delay product (EDP). At 0.7 V supply, the overall power consumption of the FGMOS NOR and NAND gates is 0.442 nW and 0.323 nW, respectively. Further, carbon nanotube field effect transistor (CNTFET) technology is used to implement NOR and NAND gates in this research work. A rigorous comparative analysis was conducted in this research study to assess the performance of non-conventional technologies, specifically field-effect transistors with floating gate (FGMOS) and carbon nanotube field-effect transistors (CNFET), in comparison to the conventional complementary metal-oxide-semiconductor (CMOS) technology. Notably, our investigation revealed that when carbon nanotube field-effect transistor (CNTFET) technology is synergistically employed in conjunction with FGMOS technology, the overall circuit performance is significantly enhanced. Furthermore, in order to estimate the robustness and reliability of the proposed designs, comprehensive analysis pertaining to delay and power-delay product (PDP) variability were meticulously carried out within the scope of this research article.

Oxide Semiconductor Heterojunction Transistor with Negative Differential Transconductance for Multivalued Logic Circuits.

Multivalued logic (MVL) technology is a promising solution for improving data density and reducing power consumption in comparison to complementary metal-oxide-semiconductor (CMOS) technology. Currently, heterojunction transistors (TRs) with negative differential transconductance (NDT) characteristics, which play an important role in the function of MVL circuits, adopt organic or 2D semiconductors as active layers, but it is still difficult to apply conventional CMOS processes. Herein, we demonstrate an oxide semiconductor (OS) heterojunction TR with NDT characteristics composed of p-type copper(I) oxide (Cu2O) and n-type indium gallium zinc oxide (IGZO) using the conventional CMOS manufacturing processes. The electrical characteristics of the fabricated device exhibit a high Ion/Ioff ratio (∼3 × 103), wide NDT ranges (∼29 V), and high peak-to-valley current ratios (PVCR ≈ 25). The electrical properties of 15 devices were measured, confirming uniform performance in the PVCR, NDT range, and Ion/Ioff ratio. We analyze the device operation by varying the source/drain (S/D) position and changing the device geometry and the thickness of the Cu2O layer. Additionally, we demonstrate heterojunction ambipolar TR to elucidate the transport mechanism of NDT devices at a high gate voltage (VGS). To confirm the feasibility of the MVL circuit, we present a ternary inverter with three clearly expressed logic states that have a long intermediate state and greater margin of error induced by wide NDT regions and high PVCR.

Memristor-Inspired Digital Logic Circuits and Comparison With 90-/180-nm CMOS Technologies

Compact low-power devices with ultrafast processing speed are the fundamental building blocks for the development of the state-of-the-art logic systems and memristor prominently fulfills these demands and plays a major role in digital circuit design. In this work, design, implementation, and performance evaluation of memristor-based logic gates, such as NOT, AND, NAND, OR, NOR, XOR, and XNOR, and combinational logic circuits, such as adder, subtractor, and 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 1 mux, are presented via SPECTRE in Cadence Virtuoso. Herein, we propose an optimized design of memristor-based logic gates and combinational logic circuits and draw a comparative analysis with the conventional 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The utilized memristor model is thoroughly validated with the experimental results of a high-density Y <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> O <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{3}}$</tex-math> </inline-formula> -based memristive crossbar array (MCA), which shows a significantly low values of coefficient of variabilities in device-to-device (D2D) and cycle-to-cycle (C2C) operation. The area, power, and delay calculated from these combinational circuits are found to be reduced by more than 71.4%, 40%, and 54%, respectively, as compared to the conventional 180-nm CMOS technology. The impact of multiple CMOS technology nodes (90 and 180 nm) on the power consumption at the chip-level logic circuit implementation has also been investigated. The adopted memristor-based design significantly improves the performance of various logic designs, which makes it area and power efficient and enables a major breakthrough in designing various low-power, low-cost, ultrafast, and compact circuits.

Broadband-Spectral-Responsivity of black silicon photodetector with high gain and sub-bandgap sensitivity by titanium hyperdoping

Silicon, as one of the most essential semiconducting materials, is widely applied in various photodetection applications due to its high portability, convenient preparation, and compatibility with conventional complementary metal–oxide–semiconductor technology. Nowadays, black silicon, prepared by enforcing ultrafast laser micro-structuring and hyperdoping techniques, has received considerable attention for developing next-generation silicon photonics and silicon optoelectronics devices. In this work, high-comprehensive-property black silicon photodetectors with broadband spectral responsivity and high gain were achieved by femtosecond laser irradiation and titanium hyperdoping. The proposed device can respond to the incident light from 400 nm to at least 1550 nm, demonstrating a high responsivity of 40.59 A/W for 950 nm under the application of −5 V bias, and the corresponding detectivity can reach 3.61 × 1012 cm·Hz1/2W−1. Moreover, the fabricated photodetector exhibits a stable sub-bandgap photocurrent at 1550 nm, with an average responsivity of 3.42 mA/W by applying a −5 V bias. These improvements were achieved by the hyperdoping of titanium in silicon, which shows deep impurity levels, low electroactivity, and increased effective carrier lifetimes, as well as the formation of shallow n-i heterojunction and trapping centers induced by the femtosecond laser irradiation. Our work provides significant insights into the applications of black silicon in various optical-related fields, including weak and infrared photon detection, silicon photonic chips, remote sensing, and large-scale optoelectronic integration.

Hierarchies in Visual Pathway: Functions and Inspired Artificial Vision.

The development of artificial intelligence has posed a challenge to machine vision based on conventional complementary metal-oxide semiconductor (CMOS) circuits owing to its high latency and inefficient power consumption originating from the data shuffling between memory and computation units. Gaining more insights into the function of every part of the visual pathway for visual perception can bring the capabilities of machine vision in terms of robustness and generality. Hardware acceleration of more energy-efficient and biorealistic artificial vision highly necessitates neuromorphic devices and circuits that are able to mimic the function of each part of the visual pathway. In this paper, wereview the structure and function of the entire class of visual neurons from the retina to the primate visual cortex within reach (Chapter 2) are reviewed. Based on the extraction of biological principles, the recent hardware-implemented visual neurons located in different parts of the visual pathway are discussed in detail in Chapters 3 and 4. Furthermore, valuable applications of inspired artificial vision in different scenarios (Chapter 5) are provided. The functional description of the visual pathway and its inspired neuromorphic devices/circuits are expected to provide valuable insights for the design of next-generation artificial visual perception systems.

Direct Visualization of Charge Migration in Bilayer Tantalum Oxide Films by Multimodal Imaging

AbstractInspired by biological neuromorphic computing, artificial neural networks based on crossbar arrays of bilayer tantalum oxide memristors have shown to be promising alternatives to conventional complementary metal‐oxide‐semiconductor (CMOS) architectures. In order to understand the driving mechanism in these oxide systems, tantalum oxide films are resistively switched by conductive atomic force microscopy (C‐AFM), and subsequently imaged by kelvin probe force microscopy (KPFM) and spatially resolved time‐of‐flight secondary ion mass spectrometry (ToF‐SIMS). These workflows enable induction and analysis of the resistive switching mechanism as well as control over the resistively switched region of the film. In this work it is shown that the resistive switching mechanism is driven by both current and electric field effects. Reversible oxygen motion is enabled by applying low (&lt;1 V) electric fields, while high electric fields generate irreversible breakdown of the material (&gt;1 V). Fully understanding oxygen motion and electrical effects in bilayer oxide memristor systems is a fundamental step toward the adoption of memristors as a neuromorphic computing technology.

A thermally aware performance analysis of quantum cellular automata logic gates

&lt;span lang="EN-US"&gt;The high-performance digital circuits can be constructed at high operating frequency, reduced power dissipation, portability, and large density. Using conventional complementary-metal-oxide-semiconductor (CMOS) design process, it is quite difficult to achieve ultra-high-speed circuits due to scaling problems. Recently quantum dot cellular automata (QCA) are prosed to develop logic circuits at atomic level. In this paper, we analyzed the performance of QCA circuits under different temperature effects and observed that polarization of the cells is highly sensitive to temperature. In case of the 3-input majority gate the cell polarization drops to 50% with an increase in the temperature of 18 K and for 5 input majority gate the cell polarization drops more quickly than the 3-input majority. Further, the performance of majority gates also compared in terms of area and power dissipation. It has been noticed that the proposed logic gates can also be used for developing simple and complex and memory circuits.&lt;/span&gt;

Parallel perception of visual motion using light-tunable memory matrix.

Parallel perception of visual motion is of crucial significance to the development of an intelligent machine vision system. However, implementing in-sensor parallel visual motion perception using conventional complementary metal-oxide semiconductor technology is challenging, because the temporal and spatial information embedded in motion cannot be simultaneously encoded and perceived at the sensory level. Here, we demonstrate the parallel perception of diverse motion modes at the sensor level by exploiting light-tunable memory matrix in a van der Waals (vdW) heterostructure array. The optoelectronic characteristics of gate-tunable photoconductivity and light-tunable memory matrix enable devices in the array to realize simultaneous encoding and processing of incoming spatiotemporal light pattern. Furthermore, we implement a visual motion perceptron with the array capable of deciphering multiple motion parameters in parallel, including direction, velocity, acceleration, and angular velocity. Our work opens up a promising venue for the realization of an intelligent machine vision system based on in-sensor motion perception.

A dual-mode image sensor using an all-inorganic perovskite nanowire array for standard and neuromorphic imaging

The high-density, vertically aligned retinal neuron array provides effective vision, a feature we aim to replicate with electronic devices. However, the conventional complementary metal-oxide-semiconductor (CMOS) image sensor, based on separate designs for sensing, memory, and processing units, limits its integration density. Moreover, redundant signal communication significantly increases energy consumption. Current neuromorphic devices integrating sensing and signal processing show promise in various computer vision applications, but there is still a need for frame-based imaging with good compatibility. In this study, we developed a dual-mode image sensor based on a high-density all-inorganic perovskite nanowire array. The device can switch between frame-based standard imaging mode and neuromorphic imaging mode by applying different biases. This unique bias-dependent photo response is based on a well-designed energy band diagram. The biomimetic alignment of nanowires ensures the potential for high-resolution imaging. To further demonstrate the imaging ability, we conducted pattern reconstruction in both modes with a 10 × 10 crossbar device. This study introduces a novel image sensor with high compatibility and efficiency, suitable for various applications including computer vision, surveillance, and robotics.

A proposal for leaky integrate-and-fire neurons by domain walls in antiferromagnetic insulators

Brain-inspired neuromorphic computing is a promising path towards next generation analogue computers that are fundamentally different compared to the conventional von Neumann architecture. One model for neuromorphic computing that can mimic the human brain behavior are spiking neural networks (SNNs), of which one of the most successful is the leaky integrate-and-fire (LIF) model. Since conventional complementary metal-oxide-semiconductor (CMOS) devices are not meant for modelling neural networks and are energy inefficient in network applications, recently the focus shifted towards spintronic-based neural networks. In this work, using the advantage of antiferromagnetic insulators, we propose a non-volatile magnonic neuron that could be the building block of a LIF spiking neuronal network. In our proposal, an antiferromagnetic domain wall in the presence of a magnetic anisotropy gradient mimics a biological neuron with leaky, integrating, and firing properties. This single neuron is controlled by polarized antiferromagnetic magnons, activated by either a magnetic field pulse or a spin transfer torque mechanism, and has properties similar to biological neurons, namely latency, refraction, bursting and inhibition. We argue that this proposed single neuron, based on antiferromagnetic domain walls, is faster and has more functionalities compared to previously proposed neurons based on ferromagnetic systems.

Electrical Characteristics of CMOS-Compatible SiOx-Based Resistive-Switching Devices.

The electrical characteristics and resistive switching properties of memristive devices have been studied in a wide temperature range. The insulator and electrode materials of these devices (silicon oxide and titanium nitride, respectively) are fully compatible with conventional complementary metal-oxide-semiconductor (CMOS) fabrication processes. Silicon oxide is also obtained through the low-temperature chemical vapor deposition method. It is revealed that the as-fabricated devices do not require electroforming but their resistance state cannot be stored before thermal treatment. After the thermal treatment, the devices exhibit bipolar-type resistive switching with synaptic behavior. The conduction mechanisms in the device stack are associated with the effect of traps in the insulator, which form filaments in the places where the electric field is concentrated. The filaments shortcut the capacitance of the stack to different degrees in the high-resistance state (HRS) and in the low-resistance state (LRS). As a result, the electron transport possesses an activation nature with relatively low values of activation energy in an HRS. On the contrary, Ohm's law and tunneling are observed in an LRS. CMOS-compatible materials and low-temperature fabrication techniques enable the easy integration of the studied resistive-switching devices with traditional analog-digital circuits to implement new-generation hardware neuromorphic systems.

Sensitive and Broadband Wavelength Sensor Based on Two Graphene/Si/Graphene Heterojunctions

AbstractHigh‐precision spectral detection and broadband wavelength sensors have attracted considerable interest for important application in color image sensing. Due to the absorption limitations of silicon, conventional complementary metal–oxide–semiconductors have a relatively limited wavelength region from the ultraviolet to near‐infrared spectrum. Here, a simple‐structured device is developed by assembling two back‐to‐back monolayer graphene (MLG)/Si/MLG heterojunctions for high‐resolution wavelength sensing applications. The single MLG/Si/MLG photodetector exhibits a responsivity of 0.18 A W−1, a specific detectivity of 1.36 × 109 Jones, and an external quantum efficiency of 28.5%. Thanks to the unique device geometry, the distribution of photo‐generation rates in the two photodetectors is completely different, which brings about different photoelectric properties. It is found that the relationship between the photocurrent ratio of both photodetectors and the light wavelength can be fitted by a monotonic function, according to which the wavelength of incident light in the range from 260 to 1050 nm can be accurately estimated. A high resolution of 1 nm is demonstrated across a broadband wavelength from 260 to 1000 nm. This good resolution, along with good repeatability and stability, endow the present device with potential promise in future spectral sensing applications.

A Novel Design of Low Power & High Speed FinFET Based Binary and Ternary SRAM and 4*4 SRAM Array

The Conventional Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOSFET) design techniques have limitations in designing the Integrated Circuit (ICs), especially with memories of multiple valued logic (MVL) in nanotechnologies. FinFET technologies provide the possibilities of low logic gates and small chip areas with high speed. Memories play an essential role in all types of devices. This paper aims to optimize the power and increase the speed of the SRAM Cell and Array using different techniques in 18nm FinFET technology. The presence of a ternary input provides an additional degree of freedom for the operation of the memory cell. The SRAM cells are also implemented at a Quantum level to improve the results in terms of area, energy, and speed. Simulation and Analysis of the design is done using Cadence Virtuoso Analog Design Environment Tool and Quantum Dot Cellular Automata Designer Tool. The proposed Multi-Threshold Complementary MOS (MTCMOS) based SRAM Array design exhibits an improvement of 4.56% in power consumption and 19.29% in speed as compared to a Conventional CMOS SRAM Array. The proposed ternary implementation of the MTCMOS-based SRAM cell is found to have a 24.9% reduction in power consumption and a 39% improvement in speed as compared to the proposed conventional ternary CMOS SRAM array while SRAM cell latency is 1 clock cycle. It occupies an area of 0.04 µm2 and consists of 33 quantum cells. The average energy dissipation of this SRAM cell is found to be 40% better than the latest existing literature for the design.

A CNTFET Based Bit-Line Powered Stable SRAM Design for Low Power Applications

Higher charge mobility, gate control, and better electrostatics are the key reasons that make carbon nanotube field effect transistor (CNTFET) a better candidate to become the successor of conventional CMOS transistors. However, the increased charge mobility also enhances the leakage power. This work uses CNTFET for designing a low-power eight-transistor static random access memory (8T SRAM) cell. The leakage power of the proposed cell is reduced by 2.21×compared to conventional 6T SRAM at 0.3V with similar CNTFET parameters. The read and write power delay product of the proposed design is improved by 1.02×and 1.85×, respectively. Moreover, the read/ write/ hold static noise margin of the proposed cell is also enhanced by 1.98×/ 0.99×/ 1.01×, respectively, compared to the conventional 6T design. The proposed cell is also compared with three already proposed CNTFET based 8T SRAM designs. Cadence Virtuoso simulation tool and Stanford University 32 nm CNTFET verilog-A model file are used to achieve simulation results.

Efficient Spectral Graph Convolutional Network Deployment on Memristive Crossbars

Graph Neural Networks (GNNs) have attracted increasing research interest for their remarkable capability to model graph-structured knowledge. However, GNNs suffer from intensive data exchange and poor data locality, which will cause critical performance and energy bottlenecks under conventional complementary metal oxide semiconductor (CMOS)-based von-Neumann computing architectures (graphics processing unit (GPU), central processing unit (CPU)) for the “Memory Wall” issue. Fortunately, memristive crossbar-based computation has emerged as one of the most promising neuromorphic computing architectures, which has been widely studied as the computing platform for convolutional neural network (CNNs), recurrent neural network (RNNs), spiking neural network (SNNs), etc. This paper proposes the deployment of spectral graph convolutional networks (GCNs) on memristive crossbars. Further, based on the structure of GCNs (extremely high sparsity and unbalanced non-zero data distribution) and the neuromorphic characteristics of memristive crossbar circuit, we propose the acceleration method that consists of Sparse Laplace Matrix Reordering and Diagonal Block Matrix Multiplication. The simulated experiment on memristor crossbars achieves 90.3% overall accuracy on the supervised learning graph dataset (QM7), and compared with the original computation, the proposed acceleration computing framework (with half-size diagonal blocks) achieves a 27.3% reduction of memristor number. Additionally, on the unsupervised learning dataset (Karate club), our method shows no loss of accuracy with half-size diagonal block mapping and reaches a 32.2% reduction of memristor number.

Ferroelectric Ternary Content Addressable Memories for Energy-Efficient Associative Search

A fast and efficient search function across the database has been a core component for a number of data-intensive tasks in machine learning, IoT applications, and inference. However, the conventional digital machines implementing the search functionality with repetitive arithmetic operations suffer from the energy efficiency and performance degradation due to the significant data transfer between the storage and processing units in the Von Neumann architecture. Ternary content addressable memories (TCAMs) are an essential hardware form of computing-in-memory (CiM) designs that aim to overcome the data transfer bottlenecks by implementing the parallel associative search function within the memory blocks. While most state-of-the-art TCAM designs focus on improving the information density by harnessing compact nonvolatile memories (NVMs), little efforts have been spent on optimizing the energy efficiency of the NVM-based TCAM. In this article, by exploiting the ferroelectric FET (FeFET) as a representative NVM, we propose an NOR-type 2FeFET-1T and an NAND-type 2FeFET-2T TCAM designs that enable highly energy-efficient associative search by reducing the associated precharge overheads. We then propose a hybrid ferroelectric NAND-NOR (HFNN) TCAM design to further improve the energy efficiency. An HFNN-based segmented architecture is proposed to reduce the search delay and energy by search operation pipeline. Evaluation results suggest that the proposed 2FeFET-1T, 2FeFET-2T and HFNN TCAM design consume <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.03\times $ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8.08\times $ </tex-math></inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$226.92\times $ </tex-math></inline-formula> less search energy than the conventional 16T complementary metal oxide semiconductor (CMOS) TCAM, respectively. Application benchmarking shows that our proposed 2FeFET-1T/2FeFET-2T/HFNN TCAM can save, on average, 45.2%/50.6%/57.5% the GPU energy consumption as compared to the conventional GPU.