Conventional ATPG Research Articles

Ring Counter Based ATPG for Low Transition Test Pattern Generation.

In test mode test patterns are applied in random fashion to the circuit under circuit. This increases switching transition between the consecutive test patterns and thereby increases dynamic power dissipation. The proposed ring counter based ATPG reduces vertical switching transitions by inserting test vectors only between the less correlative test patterns. This paper presents the RC-ATPG with an external circuit. The external circuit consists of XOR gates, full adders, and multiplexers. First the total number of transitions between the consecutive test patterns is determined. If it is more, then the external circuit generates and inserts test vectors in between the two test patterns. Test vector insertion increases the correlation between the test patterns and reduces dynamic power dissipation. The results prove that the test patterns generated by the proposed ATPG have fewer transitions than the conventional ATPG. Experimental results based on ISCAS'85 and ISCAS'89 benchmark circuits show 38.5% reduction in the average power and 50% reduction in the peak power attained during testing with a small size decoding logic.

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG

Fault equivalence is an essential concept in digital design with significance in fault diagnosis, diagnostic test generation, testability analysis and logic synthesis. In this paper, an efficient algorithm to check whether two faults are equivalent is presented. If they are not equivalent, the algorithm returns a test vector that distinguishes them. The proposed approach is complete since for every pair of faults it either proves equivalence or it returns a distinguishing vector. The advantage of the approach lies in its practicality since it uses conventional ATPG and it automatically benefits from advances in the field. Experiments on ISCAS’85 and full-scan ISCAS’89 circuits demonstrate the competitiveness of the method and measure the performance of simulation for fault equivalence.

A Novel Transition Fault ATPG That Reduces Yield Loss

In this article, we have presented a novel constrained broadside transition ATPG algorithm to avoid overtesting functionally (sequentially) untestable transition faults. In some circuits, significantly more functionally untestable transition faults were identified. At the same time, more faults could be detected without incidental detection of functionally untestable transition faults. With a test set that reduces launching of transitions that are functionally impossible, we believe our method offers a practical solution to avoid overtesting these functionally impossible transitions, thus reducing yield loss. However, the runtime for our constrained ATPG is much longer than the conventional ATPG as a result of the constraint learning and construction process. Our future work concentrates on more-efficient constraint learning algorithms to reduce the over all ATPG runtime.

Compact Test Generation Using a Frozen Clock Testing Strategy

Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach to generating compact test sequences for sequential circuits. Our approach combines a conventional ATPG algorithm, a technique based on the frozen clock testing strategy, and a dynamic compaction method based on a genetic algorithm. The frozen clock strategy temporarily suspends the sequential behavior of the circuit by stopping its clock and applying several vectors to increase the number of faults detected without changing the circuit state. Results show that test sets generated using the new approach are more compact than those generated by previous approaches for many circuits.

Abstraction techniques for validation coverage analysis and test generation

The enormous state spaces which must be searched when verifying the correctness of, or generating tests for, complex circuits precludes the use of traditional approaches. Hard-to-find abstractions are often required to simplify the circuits and make the problems tractable. This paper presents a simple and automatic method to extract the control flow of a circuit so that the resulting state space can be explored for validation coverage analysis and automatic test generation. This control flow, capturing the essential "behavior" of the circuit, is represented as a finite state machine called the ECFM (Extracted Control Flow Machine). Simulation is currently the primary means of verifying large circuits, but the definition of a coverage measure for simulation vectors is an open problem. We define functional coverage as the amount of control behavior covered by the test suite. We then combine formal verification techniques, using BDDs as the underlying representation, with traditional ATPG techniques to automatically generate additional sequences which traverse uncovered parts of the control state graph. We also demonstrate how the same abstraction techniques can complement ATPG techniques when attacking hard-to-detect faults in the control part of the design for which conventional ATPG alone proves to be inadequate or inefficient at best. Results on large designs show significant improvement over conventional algorithms.