Conventional Arithmetic Research Articles

Conventional and on-line arithmetic designs for high-speed recursive digital filters

Designs using conventional and on-line arithmetic for performing the recursive computations of Second-Order Direct-Form IIR filters are implemented in a 0.7μ HCMOS gate array technology. The new conventional (bit-parallel) design using two levels of scattered lookahead achieves a rate of 104 Msamples/second. The design eliminates carry propagate addition from the recursive loop and uses radix-4 recoding to reduce the number of partial products. The on-line design is an improved radix-4 multiply-add (MA) module. Two arrays based on the on-line MA module are developed to achieve rates of 128 Msamples/second with two levels of scattered lookahead. Performance and cost comparisons of the designs provide insights into the most appropriate designs to be used for a given word length.

Contributions of net-theory to the modelling of OR-problems from a logically based point of view

The construction and analysis of OR-problems are considered under the assumption that the problem structures depend essentially on logical constituents. The conventional approach to use binary (“0/1”) variables suffers from models which are very complicated and intransparent. The nature of logical constitutents is not “adequately” represented by complexes of binary variables. As an alternative the net-theoretic approach can be used to construct graphical problem descriptions. These descriptions base on the propositional or predicate logic and the theory of Petri nets. The resulting net models have the advantages of compactness and easy interpretation. Furthermore conventional arithmetic and logically based algorithrns can be applied to the analysis of net models (for consistency checks e.g.). The efficiency of model construction and analysis is not considered. Instead of this the preceding aspect is explored which contributions to problem modelling result from combining logic, net theory, linear arithmetic and graphical problem description. An example demonstrates these results. It concerns the design of annual balance sheets of stock corporations with regard to corporate income tax.

Bit-Level systolic architectures for high performance IIR filtering

Several novel systolic architectures for implementing densely pipelined bit parallel IIR filter sections are presented. The fundamental problem of latency in the feedback loop is overcome by employing redundant arithmetic in combination with bit-level feedback, allowing a basic first-order section to achieve a wordlength-independent latency of only two clock cycles. This is extended to produce a building block from which higher order sections can be constructed. The architecture is then refined by combining the use of both conventional and redundant arithmetic, resulting in two new structures offering substantial hardware savings over the original design. In contrast to alternative techniques, bit-level pipelinability is achieved with no net cost in hardware.

Computer Aided Analysis Software for Discrete-event Dynamic System

A discrete-event system is a system whose behaviour can be discribed by a set of time-consuming activities, performed according to a prescribed ordering. The events concerned correspond to starting or ending time of some activities. This kind of system is not linear in the conventional arithmetic, but is, however, linear in max-algebra. A new kind of linear system, also called psuedo-linear discrete-event system, has been set up. Referring to usual linear system theory, a series of results for modelling and analysis of discrete-event dynamic system (DEDS) are developed, such as state equation, stability, characteristic equation, eigenvalue, periodicity, controllability, observability, etc. The Psuedo-linear Discrete-event System Analysis Package (PDSAP) is to implement the matrix calculations in max-algebra sense, model DEDS and analize performances of the system. Some fundamental contents of max-algebra and DEDS, functions and some algorithms of PDSAP are presented in this paper.

The Use of Floating-Point and Interval Arithmetic in the Computation of Error Bounds

Three forms of interval floating-point arithmetic are defined in terms of absolute precision, relative precision, and combined absolute and relative precision. The absolute-precision form corresponds to the centered form of conventional rounded-interval arithmetic. The three forms are compared on the basis of the number of floating-point operations needed to generate error bounds for inner-product accumulation.

Modular and quasi-modular arithmetic

The conventional modular arithmetic is but a particular case of a more general class of solutions. In the case of addition the class of modular solutions is not too numerous; on the contrary, the modular solutions for multiplication are very many and the conventional modular arithmetic appears not to be among the best solutions, because of the redundancy of the code introduced by it.