Control Processor Research Articles

Optimality and Complexity Analysis of a Branch-and-Bound Method in Solving Some Instances of the Subset Sum Problem

Abstract In this paper we study the question of parallelization of a variant of Branch-and-Bound method for solving of the subset sum problem which is a special case of the Boolean knapsack problem. The following natural approach to the solution of this question is considered. At the first stage one of the processors (control processor) performs some number of algorithm steps of solving a given problem with generating some number of subproblems of the problem. In the second stage the generated subproblems are sent to other processors for solving (one subproblem per processor). Processors solve completely the received subproblems and return their solutions to the control processor which chooses the optimal solution of the initial problem from these solutions. For this approach we define formally a model of parallel computing (frontal parallelization scheme) and the notion of complexity of the frontal scheme. We study the asymptotic behavior of the complexity of the frontal scheme for two special cases of the subset sum problem.

Design of an Online Brain-Computer Interface System Based on Field Programmable Gate Array

In the article, an online brain-computer interface (BCI) demo system based on Field Programmable Gate Array (FPGA) was designed. A colour visual stimulator based on a Video Graphics Array (VGA) monitor controlled by FPGA is designed to produce transient visual stimulations. An electroencephalography (EEG) acquisition module including active electrodes and driven-right-leg circuit is used to acquire the visual evoked potential (VEP) signal; Finite impulse response (FIR) filtering combined with an averaging method allows for extraction of the weak VEP signals. The template matching method is used in target identification. The FPGA is successfully used in the BCI system to complete multiple tasks such as the VGA controller, analog to digital (AD) converter controller, VEP signal processor and electronic device controller. Experiments show that the subjects’ transient VEP can successfully activate the electronic devices by the online BCI system which has relatively high identification accuracy. All these results show that the real time BCI demo system based on FPGA is feasible and effective.

Z15 selfboot and secure boot

The IBM Z central processor (CP) and storage controller (SC) chips contain hardware and firmware to serve selfboot and secure boot needs. Selfboot initializes the CP/SC chips from hardware and firmware, which reside in each chip module. This establishes a core root of trust and also guarantees a boot time that is independent of the system configuration, which is key for large enterprise class systems consisting of multiple drawers and chips. Secure boot is built on this core root of trust and is used to authenticate the firmware loaded from system memory prior to execution of that firmware. Selfboot and secure boot also guarantee the integrity of the CP and SC chips by restricting hardware and memory accesses through debug or service interfaces during boot, runtime, and code update phases. In this article, we describe the basic hardware and firmware concepts that are implemented and enabled for the z15 CP and SC chips.

Software Defined Networking Flow Table Management of OpenFlow Switches Performance and Security Challenges: A Survey

Software defined networking (SDN) is an emerging network paradigm that decouples the control plane from the data plane. The data plane is composed of forwarding elements called switches and the control plane is composed of controllers. SDN is gaining popularity from industry and academics due to its advantages such as centralized, flexible, and programmable network management. The increasing number of traffics due to the proliferation of the Internet of Thing (IoT) devices may result in two problems: (1) increased processing load of the controller, and (2) insufficient space in the switches’ flow table to accommodate the flow entries. These problems may cause undesired network behavior and unstable network performance, especially in large-scale networks. Many solutions have been proposed to improve the management of the flow table, reducing controller processing load, and mitigating security threats and vulnerabilities on the controllers and switches. This paper provides comprehensive surveys of existing schemes to ensure SDN meets the quality of service (QoS) demands of various applications and cloud services. Finally, potential future research directions are identified and discussed such as management of flow table using machine learning.

Submodule Capacitance Monitoring Strategy for Phase-Shifted Carrier Pulsewidth-Modulation-Based Modular Multilevel Converters

Capacitance monitoring is one of the important issues for a modular multilevel converter (MMC) to obtain high reliability. Since pulsewidth modulation is usually implemented in the field-programmable gate array (FPGA), produced precise switching states in the FPGA cannot be directly accessed by the top digital signal processor (DSP) controller, which poses challenges to the existing capacitance monitoring methods based on precise switching states of the MMC. This article presents a submodule (SM) capacitance monitoring strategy for the MMC with a simple algorithm, where the fundamental frequency components of the SM capacitor voltage and current are extracted to estimate the SM capacitance based on reference, but not the precise switching states. The proposed scheme not only simplifies the implementation and calculation, but also avoids control limitations and heavy communication burden between the DSP and the FPGA. Besides, the proposed strategy effectively eliminates noise impact from sensors and increases accuracy. Simulation and experimental studies are implemented, and the results confirm the effectiveness of the proposed strategy.

An Indigenous Smart Cane System For The Visually Impaired With Sound Clap Location Ability

Guiding the visually impaired persons is always very tasking. Smart Canes previously designed for the blinds are relatively costly. Also, most of the available Smart Cane Systems used only remote control and buzzing methods for locating the cane if misplaced. However, no research work has handled how to locate the cane should the remote control itself be misplaced. This work designed an Indigenous Smart Cane System for the Visually Impaired with Sound Clap Location Ability. It is relatively less costly, easy to learn, and can be located by a natural means if misplaced. The system uses one ATMEGA328P Microcontroller which is programmed to control both input and output signals. It was designed with three low-cost 0.3m resolution HC-SR04 Ultrasonic Sensors to detect obstacles within the range of 2cm – 400cm in the front, left and right directions of the user and sends the current obstacle distance signal to the controller for processing. Receiving this signal, the controller determines which of the output devices (Piezo Speaker, Earphone and Vibrator Motor) to use and communicate the object distance to the user. In case the cane is misplaced, the user makes a sound clap which triggers the Sound Sensor to send signal to the controller for an audio feedback. This audio feedback is done by the Piezo Speaker. The system was programmed to use a very simple object – detection algorithm to help the user learn how to use the cane easily. This system has been tested and found to be relatively less costly, easy to learn and can be located with a clap sound.
 Keywords: Sound-Clap Location Ability, Visually Impaired, Indigenous Smart Cane, Sensors, Audio Feedback; Object Distance; Microcontroller.

Navigasi robot bergerak berdasarkan landmark garis menggunakan kontroler Braitenberg dan pengolahan citra

Line following and lane tracking are robotic navigation techniques that use lines as a guide. The techniques can be applied to mobile robots in the industry. This research applied the Braitenberg controller and image processing to control and obtain line information around the mobile robot. The robot was implemented using Arduino Uno as a controller. A webcam was connected to a computer that performs image processing using canny edge detection and sends the data to the robot controller via serial communication. The robot can navigate on the side of the line, and the success rate of the system is 100 % at a turn of 135 ° and 80 % at a turn of 90 °.

A Multi-Level Power Converter Interface for a Battery Energy Storage System

— This study proposes a multi-level power converter for a battery energy storage system (BESS) with bidirectional power flow. The multi-level power converter includes a DC-DC power converter, a selection switch set and a full-bridge inverter. The DC-DC power converter performs bidirectional power conversion and provides a DC voltage that is greater than the peak voltage of the utility. Integrating the selection switch set and the full-bridge inverter produces a five-level AC voltage that controls the real power flow and the reactive power flow between the battery set, the DC-DC power converter and the grid. Because partial power is directly processed using only the selection switch set and the full-bridge inverter, the DC-DC power converter is operated only when the grid voltage is greater than the voltage of the battery set. Therefore, the power conversion efficiency for the proposed BESS is improved. The proposed BESS uses only eight power electronic switches, so the power circuit is simplified. A hardware prototype with a digital signal processor controller is used to verify the performance of the proposed BESS. The experimental results are as expected.

Cryptocurrency and Privacy: Economic Analysis of Law

The dynamic technology junction of Cryptocurrency and Privacy pose several implications to the existing economic and legal regulations. The present work intends to take up an economic analysis of the laws relating to Cryptocurrency in the context of Privacy. The concept of money and development of fiat currency with role of banking industry leads one to understand the background of Cryptocurrency basis, therefore a segment on the historic perspective of money, development of fiat money and role of banking industry as an intermediary are added in the present work. The technology of Blockchain used in Cryptocurrency transaction transmits the existing monetary regulations across the globe thereby challenging the financial systems. The economics of Cryptocurrency has generated sufficient interest and the present work surveys such interest. The most comprehensive regulation on Privacy and Data protection having a global impact is the European Union’s General Data Protection Regulation (EUGDP), which took effect in May 2018. The EUGDP Regulations by giving much needed importance and protection to the individual’s data privacy and security have altered the functionality of the Data driven companies such as Facebook, Google and others. The work takes a brief note of issues such as data controller and data processor identification, territorial and cross-border data transfer issues, legitimate bases for processing personal data and individual’s privacy rights as some of necessary compliance under the EUGDP Regulations that interact with the blockchain technology used under Cryptocurrency transactions. The conclusion suggests the need for economic analysis of laws relating to Cryptocurrency and Privacy for their intrinsic economic value.

Междисциплинарная связь физики, схемотехники и программирования

В статье представлены результаты разработки электронного устройства на основе цифровых компонентов, проведенной совместно с учащимися школ и студентами. Целью данной работы являлись проектирование и разработка электронного устройства на основе 32-битных микроконтроллеров серии STM32. Для проектирования и разработки электронной части устройства была использована интегрированная среда разработки Altium Designer. С применением языка высокого уровня С++ разработана управляющая программа в отладочной среде Keil v.5. В качестве центрального управляющего процессора использован микроконтроллер серии STM32F030K6T6. Разработаны электрическая схема и печатная плата прибора. В качестве сенсорного элемента использован высокочувствительный датчик газа TGS 2610 производства фирмы «Figaro» (Япония). Для передачи SMS применен модуль SIM800A. В процессе выполнения работы учащиеся самостоятельно изготовили электрические платы с использованием метода облучения ультрафиолетовой лампой специального фоторезиста. Практически все компоненты были расставлены и распаяны школьниками самостоятельно. Совместно со студентами была разработана управляющая программа для микроконтроллера. Для изготовления корпуса устройства была задействована среда «КОМПАС». Распечатка корпуса осуществлялась на 3Dпринтере. Проведены калибровка прибора и ее тестовые испытания. По результатам предварительных тестовых испытаний устройства установлено, что датчик газа реагирует на наличие газа в течение первых 20 с от времени начала утечки. Ложных срабатываний устройства не зафиксировано. Показано значение основ физики, информатики и математики в процессе проектирования цифровых устройств и приборов.

SkinSim: A Design and Simulation Tool for Robot Skin With Closed-Loop pHRI Controllers

The importance of tactile sensing for physical human–robot interaction (pHRI) and dexterous manipulation is well known. SkinSim is a novel simulation environment for tactile robot skins in which one can study design tradeoffs involved in deploying whole-body, dense sensor arrays. In this article, scalable modeling approaches are presented for simulating pressure-sensitive robot skin patches, with simultaneous consideration of sensing element geometry and mechanical structure, signal quality, data processing, and closed-loop force controller performance. The open-source simulation architecture of SkinSim is compatible with Gazebo and robot operating system (ROS) programming environments and supports both robot skin dynamic models, as well as tactile sensing element models. An experimentally validated force dispersion model was introduced for the simulation of sensors embedded in a mechanical damping layer. Simulation examples of robot skin with different tactile resolutions are presented using parameter values extracted from an experimental testbed. Thus, simulation results were experimentally validated and the skin sensor density impact on a simple pHRI controller performance was evaluated. Performance measures include center of pressure (COP) estimation error and control signal settling time, overshoot, and steady-state errors. Results suggest that while COP errors decrease in denser sensor skins, controller performance also deteriorates. Therefore, optimal robot skin designs will have to consider application-dependent tradeoffs. Similar results were confirmed in simulation with a larger skin patch containing approximately 4000 tactels and deployed on the end-effector of a collaborative mobile manipulator. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Note to Practitioners</i> —This article was motivated by the expensive and time-consuming process of designing tactile skin for robots. When designing pressure-sensitive whole-body sensor arrays for physical human–robot interaction, there are tradeoffs related to sensor resolution, accuracy, and response time, among others. Instead of building prototypes and evaluating them experimentally, the SkinSim simulation environment allows automatic testing of skins with simultaneous consideration of sensing element geometry and mechanical structure, signal quality, data processing, and closed-loop force controller performance. The user can specify several configurations to test and thereby explore the best tradeoffs before actually prototyping any hardware.

GDPR compliance: proposed technical and organizational measures for cloud provider

PurposeThe purpose of this paper is to give a brief guidance on what a cloud provider should consider and what further actions to take to comply with General Data Protection Regulation (GDPR).Design/methodology/approachThis paper presents in detail the requirements for GDPR compliance of cloud computing environments, presents the GDPR roles (data controller and data processor) in a cloud environment and discusses the applicability of GDPR compliance requirements for each cloud architecture (Infrastructure as a Service, Platform as a Service, Software as a Service), proposes countermeasures for satisfying the aforementioned requirements and demonstrates the applicability of the aforementioned requirements and countermeasures to a PaaS environment offering services for building, testing, deploying and managing applications through cloud managed data centers. The applicability of the method has been demonstrated on in a PaaS environment that offers services for building, testing, deploying and managing applications through cloud managed data centers.FindingsThe results of the proposed GDPR compliance measures for cloud providers highlight the effort and criticality required from cloud providers to achieve compliance.Originality/value

When a ‘Like’ Is Not a ‘Like’: A New Fragmented Approach to Data Controllership

AbstractIn Fashion ID, the Court of Justice of the European Union (‘CJEU’) held that an operator of a website featuring a Facebook ‘Like’ button is a data controller under EU Directive 95/46 (‘Directive’) jointly with Facebook in respect of the collection and transmission of the personal data of website visitors to Facebook, but Facebook alone is a data controller for any subsequent data processing. While the CJEUs expansive interpretation of joint controllership aims to leave ‘no gaps’ in the protection of individuals, we question whether the proposed solution to ‘fragment’ controllership into different stages of processing helps to achieve that goal. We argue that CJEUs ‘fragmented’ approach is incompatible with the GDPR, as it does not reveal the intended purposes of data processing, and thus negates informed and specific consent. We suggest that such ‘fragmentation’ undermines the consistency, predictability and transparency of EU data protection law by obscuring the pervasiveness of data commodification in the digital economy.

Seven‐level power conversion system for solar power generation system

This study proposes a seven-level power conversion system for a solar power generation system. This seven-level power conversion system consists of a DC–DC power converter and a cascade DC–AC inverter. The cascade DC–AC inverter comprises a full-bridge inverter and a T-type inverter. The T-type inverter generates a three-level quasi-square-wave voltage and the full-bridge inverter provides a three-level high-frequency pulse voltage. The amplitude of the three-level quasi-square-wave voltage is double that of the three-level high-frequency pulse voltage, so seven levels of AC voltage are synthesized. Only the full-bridge inverter with lower DC bus voltage uses high-frequency switching so switching losses are effectively reduced. The novelty of the proposed cascade DC–AC inverter is that the output power of T-type inverter is controlled by regulating the DC bus voltage, so no real power is supplied from the full-bridge inverter and an independent power source is not required to provide power to the full-bridge inverter. The negative terminal voltage for solar cell array keeps almost constant to reduce the leakage current of proposed seven-level power conversion system. A hardware prototype with a digital signal processor controller is developed to verify the performance of seven-level power conversion system for a solar power generation system.

Approximate Memory Compression

Memory subsystems are a major energy bottleneck in computing platforms due to frequent transfers between processors and off-chip memory. We propose approximate memory compression, a technique that leverages the intrinsic resilience of emerging workloads such as machine learning and data analytics to reduce off-chip memory traffic, thereby improving energy and performance. We realize approximate memory compression by enhancing the memory controller to be aware of approximate memory regions—regions in memory that contain approximation-resilient data—and to transparently compress (decompress) the data written to (read from) these regions. To provide control over approximations, each approximate memory region is associated with an error constraint such as the maximum error that may be introduced in each data element. The quality-aware memory controller subjects memory transactions to a compression scheme that introduces approximations, thereby reducing memory traffic, while adhering to the specified error constraint for each approximate memory region. A software interface is provided to allow programmers to identify data structures (DSs) that are resilient to approximations. A runtime quality control framework automatically determines the error constraints for the identified DSs such that a given target application-level quality is maintained. We evaluate our proposal by applying it to three different main memory technologies in the context of a general-purpose computing system—DDR3 DRAM, LPDDR3 DRAM, and spin-transfer torque magnetic RAM (STT-MRAM). To demonstrate the feasibility of the proposed concepts, we also implement a hardware prototype using the Intel UniPHY-DDR3 memory controller and Nios-II processor, a Hynix DDR3 DRAM module, and a Stratix-IV field-programmable gate array (FPGA) development board. Across a wide range of machine learning benchmarks, approximate memory compression obtains significant benefits in main memory energy ( $1.18\times $ for DDR3 DRAM, $1.52\times $ for LPDDR3 DRAM, and $2.0\times $ for STT-MRAM) and a simultaneous improvement in execution time (5.2% for DDR3 DRAM, 5.4% for LPDDR3 DRAM, and 9.3% for STT-MRAM) with nearly identical application output quality.

1.2 Mfps standalone X-ray detector for Time-Resolved Experiments

We present a standalone and autonomous X-ray detector capable of operation with the speed of up to1.2 Mfps. The detector utilizes UFXC32k hybrid pixel detectors for sensing X-rays, Spartan-6 LX45 FPGA placed in commercially available sbRIO 9628 controller for data acquisition and processing including a compression with zero-suppression algorithm. A Linux-RT system working on the 400 MHz Dual-Core CPU is used for FPGA control and data streaming to the higher-level system over 1 Gbps Ethernet connection. 1.2 M frames per second is achieved in so-called burst mode of operation while in zerodead-time mode 70 kfps is possible. Due to efficient data compression in FPGA there's no need of using high-speed transceivers and Frame-Grabber cards on the data server side and the detector can stream the data infinitely over standard 1 Gbps network connection. Operation modes were tested at Advanced Photon Source Synchrotron at Argonne National Laboratory.

Study on precise detecting and controlling technology of lag angle based on image processing

A precise method of detecting and controlling of lag angle during the optical fiber winding procedure is described in this paper. The system is composed of three modules, image collection, image processing and PC controller. Images of lag angle are collected by an industrial high-speed camera. Binary treatment on lag angle images of the motive optical fiber is done by global threshold method. Image identification of lag angle of the motive optical fiber is realized by Hough transform, thus the digital values of lag angel are obtained. PC outputs controlled variables to modify the winding motion based on detecting results so as to limit the lag angel in a precise range. The research result indicates that application of image collection and identification technology to optical fiber winding can avoid winding flaw effectively such as gap and lamination thus to improve the quality and efficiency of optical fiber winding.

Study on precise detecting and controlling technology of lag angle based on image processing

A precise method of detecting and controlling of lag angle during the optical fiber winding procedure is described in this paper. The system is composed of three modules, image collection, image processing and PC controller. Images of lag angle are collected by an industrial high-speed camera. Binary treatment on lag angle images of the motive optical fiber is done by global threshold method. Image identification of lag angle of the motive optical fiber is realized by Hough transform, thus the digital values of lag angel are obtained. PC outputs controlled variables to modify the winding motion based on detecting results so as to limit the lag angel in a precise range. The research result indicates that application of image collection and identification technology to optical fiber winding can avoid winding flaw effectively such as gap and lamination thus to improve the quality and efficiency of optical fiber winding.

Indecision and delays are the parents of failure\u2014taming them algorithmically by synthesizing delay-resilient control

The possible interactions between a controller and its environment can naturally be modelled as the arena of a two-player game, and adding an appropriate winning condition permits to specify desirable behavior. The classical model here is the positional game, where both players can (fully or partially) observe the current position in the game graph, which in turn is indicative of their mutual current states. In practice, neither sensing and actuating the environment through physical devices nor data forwarding to and from the controller and signal processing in the controller are instantaneous. The resultant delays force the controller to draw decisions before being aware of the recent history of a play and to submit these decisions well before they can take effect asynchronously. It is known that existence of a winning strategy for the controller in games with such delays is decidable over finite game graphs and with respect to omega -regular objectives. The underlying reduction, however, is impractical for non-trivial delays as it incurs a blow-up of the game graph which is exponential in the magnitude of the delay. For safety objectives, we propose a more practical incremental algorithm successively synthesizing a series of controllers handling increasing delays and reducing the game-graph size in between. It is demonstrated using benchmark examples that even a simplistic explicit-state implementation of this algorithm outperforms state-of-the-art symbolic synthesis algorithms as soon as non-trivial delays have to be handled. We furthermore address the practically relevant cases of non-order-preserving delays and bounded message loss, as arising in actual networked control, thereby considerably extending the scope of regular game theory under delay.

Assessment of proposed maximum power point tracking–unity power factor algorithms for optimum operation permanent magnet synchronous generator–based wind turbine

It is very important to select proper maximum power point tracking algorithm in order to achieve best performance and low cost for wind turbine–generator combination. A permanent magnet synchronous generator steady-state unity power factor analytical model based on a current source—equivalent circuit is provided. Validation of the identified load angle effect in current source as compared with that of the commonly used voltage source permanent magnet synchronous generator is presented. Then three new maximum power point tracking–load angle control algorithms based on current source model are presented. They all apply magnitude and frequency control techniques for Digital Signal Processor control systems. The first one presents maximum power point tracking–unity power factor applying constrained load angle control algorithm. The merits of the next two developed schemes are quickly and precisely tracking the maximum power output of the wind turbine; thus, the second and third algorithms are then characterized with linear control systems. The linearity of the second scenario is between load angle and reference speed while the third one has a load angle–torque linear relationship which shows its optimality. Finally, the controlled characteristics and implementation for the optimum case are presented for both stationary and synchronous reference frames (for vector control purposes). Simulation modeling for optimum case is provided and its results match well with the proposed predictive control algorithm.