Controlled Collapse Chip Connection Research Articles

Crossbar operation of BiFeO3/Ce–CaMnO3 ferroelectric tunnel junctions: From materials to integration

Ferroelectric Tunnel Junctions (FTJs) are a candidate for the hardware realization of synapses in artificial neural networks. The fabrication process for a 784 × 100 crossbar array of 500 nm large FTJs, exhibiting effective On/Off currents ratio in the range 50–100, is presented. First, the epitaxial 4 nm-BiFeO3/Ca0.96Ce0.04MnO3//YAlO3 is combined with Ni electrodes. The oxidation of Ni during the processing affects the polarity of the FTJ and the On/Off ratio, which becomes comparable to that of CMOS-compatible HfZrO4 junctions. The latter have a wider coercive field distribution: consequently, in test crossbar arrays, BiFeO3 exhibits a smaller cross-talk than HfZrO4. Furthermore, the relatively larger threshold for ferroelectric switching in BiFeO3 allows the use application of half-programming schemes for supervised and unsupervised learning. Second, the heterostructure is combined with W and Pt electrodes. The design is optimized for the controlled collapse chip connection to neuromorphic circuits.Graphical abstract

Effect of thermal cycling on the strain and stress distribution of TSVs and solder bumps in stacked package structure

Aerospace exploration requires electronic devices to withstand the test of extreme environments, and it is of great significance to study the reliability of packaged devices at extreme temperatures. In this paper, the Anand model is used to describe the mechanical constitutive behavior of Sn-3.0Ag-0.5Cu (SAC305) solder and through-silicon via (TSV) in a 3D package structure, and the thermal cycling behavior of controlled collapse chip connection (C4) bumps and TSV arrays under thermal cycling from -100 to 120 °C is analyzed. The thermal fatigue life of C4 bumps and TSVs was evaluated according to the modified Coffin-Manson model. The results show that the maximum stress is 50.57 MPa at the contact interface between the C4 bump and the chip, which is caused by local thermal mismatch. The maximum equivalent plastic strain of the key bump is 1.6 × 10−2 and its fatigue life under extreme temperature thermal cycling conditions is about 1366 cycles. The maximum equivalent plastic strain of the TSV array is 2.8 × 10−2, located at the corner of the peripheral TSV, which is the most dangerous position in the TSV array, and its thermal fatigue life is about 1.9 × 106 cycles.

MTTF Enhancement Power-C4 Bump Placement Optimization

Constructing a reliable power delivery network (PDN) is increasingly challenging by further technology scaling. PDN suffers from long-term reliability threats such as electromigration (EM). EM results in permanent failures and directly affects chip lifetime and voltage stability. Loss of limited controlled collapse chip connection (C4) pads to EM makes delivering a stable supply voltage more critical. The C4 bumps failure mechanism depends on current density, on-chip voltage noise, and temperature. In this paper, we develop a statistical simulation framework to analyze the effect of accurate chip temperature on multiple power-bump wearout. Our result shows that using uniform temperature leads, in the pessimistic system, to mean-time-to-failure (MTTF). Meanwhile, the current C4 pad placement optimization algorithms consider the current source or voltage drop as the forces to move the pads that do not lead to maximum MTTF. We propose a new technique to improve the efficiency of optimization algorithms by exploring the temperature as a new virtual force to move the pads. Experimental results show that our algorithm improves the MTTF by 25.43% that will support more off-chip I/O channels in current and near-future technology nodes.

Microbump Processing for 3D IC Integration

In recent years, the development of microbumps has allowed even smaller sizes of ICs to utilize the flip chip technique. In addition, microbumps have enabled the implementation of three-dimensional (3D) ICs, which drastically improve the spatial efficiency of packaging. However, as the bumps size decreases and the number increases, several process challenges must be considered, for example, the height consistency of bump, the ratio of miss and deformity bump and the yield and strength of interconnection, etc. Therefore, it is increasingly important to study the interconnection technology and materials of high-density microbump interconnection. After briefly introducing the common electronic packaging techniques, including wire bonding, tape-automated bonding and flip chip, this paper reviews microbumps as an advanced bonding technology. Techniques such as Controlled Collapse Chip Connection - New Process(C4NP), printing, insert bump bonding, and self-replication process are discussed and compared. C4NP can achieve low-cost, fine pitch bumping by utilizing varied lead-free solder alloys, which overcomes the limitation of existing bumping technologies. Depending on the microbump size, engraved mask stump, and photosensitive organic mask and squeegee are the two ways for micro-bump printing. The micro-insert bump bonding process is new to stack chips vertically, which has robust bonding structure and a simpler bonding process compared to Cu pillar bonding process. The self-replication process is using the surface tension property of molten solder between the micro bridged bump to get two bumps with same volume and geometries on each faced pairs of lands. The use of two common material for the microbump, Cu, Sn, and its alloys are presented along with the differences in the process for each. As with any technology, a new breakthrough addressing an issue brings with it its own set of shortfalls. Microbumps are no different. The various techniques and materials used to realize the reduced scale bonding method are subject to a number of challenges. Most prominent among them are electromigration, thermomigration, and thermallyinduced mechanical fatigue, which are discussed in this paper.

Bumping Process Impact on the Chip Package Interaction (CPI) Reliability

Abstract Flip chip technology is widely used in advanced integrated circuit (IC) package. Chip package interaction (CPI) became critical in flip chip technology that needed to be addressed to avoid electrical or mechanical failure in products. When addressing CPI challenges, different areas have to be considered, ranging from silicon BEOL design and processing, bumping design and process, package assembly process, assembly bill of material (BOM), and substrate technology. Controlled collapse chip connection (C4) bump technology provided the inter-connection between the IC to package substrate for high-performance, leading-edge microprocessors. It is very critical for chip package interaction (CPI). With the transfer to lead free technology, bumping process plays more and more important role for chip package interaction reliability. In this paper, we focused on bumping process effect on the CPI reliability. The bumping process has been reviewed and CPI reliability issues induced by the bumping process like particles, Ti seed layer deposition, UBM undercut, Cu pad oxidation and contamination, photoresist opening damage have been discussed. Bumping process optimization and corrective actions have been taken to reduce those defects and improve CPI reliability.

(Invited) Copper Plating and Its Application in Advanced Packaging

Conventional acid electroplated copper is being widely used in semiconductor industries from back-end-of-the-line (BEOL) interconnects to advanced packaging applications such as copper pillar, redistribution layer (RDL) copper and Through Silicon Via ( TSV) because of low cost, easy manufacturing process and high throughput[1-3]. Industry trends towards higher performance semiconductor devices with increased interconnect density have created significant materials challenges for advanced electronics packaging metallization processes. Copper pillar becomes a transformative technology replacing traditional C4 (controlled collapse chip connection) bumps to meet new performance demands. Copper pillar chemistry requires innovative organic additives in order to meet challenges such as flat pillar shape, void-free intermetallic interface after reflow with solder, fast plating speed, high purity deposits and excellent uniformity. Copper plating baths may contain at least one or three of the additives: accelerator, suppressor, and leveler. Accelerator is usually used to enhance plating rate (depolarization agent) just as its name indicates, while suppressor and leveler are polarization agents that inhibit the plating locally. Although all the additives can be defined as either polarization or depolarization agents, depending on the electrochemical response, the function of each additive could be very different depending on the application. In this talk, the additive function in three different electroplating applications, Dual Damascene, TSV, and copper pillar, will be compared. Then we will introduce the development of Dow Electronic Materials’ next-generation copper pillar chemistry. Additives, current density and process impact on plating performance will be discussed. E. Reddington, M. Thorseth, Y. Qin, J. Woertink, R. Farrell, M. Scalisi, E. Banelis, P. Lopez-Montesinos, B. Sherzer, Z. Baumer, W. Tachikawa, J. dong, M. Lefebvre, J. Calvert, International Wafer Level Packaging Conference (IWLPC), 2014, San JoseT. P. Moffat, D. Wheeler, M.D. Edelstein, D. Josell, IBM J. RES. & DEV. 49, 2005, 19-36M. Thorseth, M. Scalisi, I. Lee, S. Park, Y. Lee, J. Prange, M. Imanari, M. Lefebvre, J. Calvert, 12th International Microelectronics Assembly and Packaging Society (IMAPS), 2016, Arizona

Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures

With ever-increasing on-chip current density, technology scaling is pushing the electromigration (EM)-induced robustness of silicon chips’ controlled collapse chip connection (C4) bump array to its limit. Since the density of C4 bumps is projected to be constant in the future, it is increasingly becoming challenging to guarantee EM-failure free for all power-supply bumps without increasing chip packaging cost or encroaching on bumps sites needed for I/O. In this paper, we develop a statistical simulation framework to analyze the mechanism and consequences of multiple power-bump wearout. Our analysis shows that the penalty of a moderate number of EM-induced power-bump failures is fairly small. A mild increase in on-chip supply voltage noise guardband can tolerate these bump failures and significantly increase a system mean-time-to-failure (MTTF). As a result, the targeted system MTTF can be achieved with significantly reduced power-bump count (e.g., 43% less) and a small extra noise margin (e.g., 0.5% $V_{\mathrm{ dd}}$ IR drop).

A High-Linearity 76–85-GHz 16-Element 8-Transmit/8-Receive Phased-Array Chip With High Isolation and Flip-Chip Packaging

<?Pub Dtl=""?> An SiGe transmit–receive phased-array chip has been developed for automotive radar applications at 76–84 GHz. The chip is based on an all-RF beamforming approach and contains 8-transmit channels, 8-receive channels, and a complete built-in-self-test system. Two high-linearity quadrature mixers with an input <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$P_{1\,{\rm dB}}$</tex></formula> of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${+}{\hbox{2.5}}$</tex> </formula> dBm are used and allow simultaneous sum and difference patterns in the receive mode. The chip operates in either a narrowband frequency-modulated continuous-wave (FMCW) mode or a wideband mode with <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">${&gt;} {\hbox{2}}$</tex></formula> -GHz bandwidth. A high-linearity design results in an input <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$P_{1\,{\rm dB}}$</tex></formula> of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}{\hbox{10}}$</tex> </formula> dBm (per channel), a system noise figure of 16–18 dB, and a transmit power is 4–5 dBm (per channel). The chip uses a controlled collapse chip connection (C4) bumping process and is flip-chipped on a low-cost printed-circuit board, and results in <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${&gt;} {\hbox{50}}$</tex></formula> -dB isolation between the transmit and receive chains. To our knowledge, this work represents the state-of-the-art in terms of complexity at millimeter-wave frequencies and with simultaneous transmit and receive operation for high-performance FMCW radars.

Electrochemical Flip-Chip Interconnect Technology

The flip-chip interconnect technology introduced to microelectronic packaging a high number of inputs/outputs (I/O), high interconnect density and most importantly improved electrical and thermal performance1. Fabrication of PbSn solder Controlled Collapse Chip Connections (C4) by evaporation through a metal mask was pioneered by IBM2, 3 in the 60’s as a high reliability packaging method. However, evaporation, besides requiring a large capital investment, is typically less than 5% efficient. More than 95 % of the evaporated material ends up on the evaporator wall and on the metal mask, which need to be cleaned, and the Pb-containing waste has to be disposed of by an expensive, regulated procedure. Both the Under-Bump-Metallurgy and the 97/3 Pb/Sn solder solder were evaporated through a molybdenum metal mask. However, as the wafer size progressively increased and the solder dimensions decreased, the thermal mismatch between the mask (4.8 ppm/oC) and the Si wafer (2.6ppm/oC) limited the extendibility of the evaporation process.3 The electrochemical fabrication of flip-chip solder technology is an extremely selective and efficient process which is extendible to larger wafer sizes, to finer dimensions and to higher C4 density.3, 4 Our focus was the development of a manufacturable technology that was based on additive and subtractive thin film processing.4 A typical process flow for the fabrication of the flip-chip interconnection is as follows. On the passivated chip, that has vias to the Cu pads, a blanket barrier layer of TiW or Cr is deposited by sputtering. A blanket CrCu layer about is sputtered over the barrier layer. A blanket Cu seed layer is sputtered on top of the CrCu layer. The role of the CrCu is to provide improved adhesion of the solder intermetallic (typically Cu3Sn or Cu6Sn5) with the underlying barrier layer. The C4 pattern is defined on the wafer with an appropriate photoresist of thickness at least as great as the thickness of the plated solder. The solder is electroplated through the resist mask, as an alloy or as sequencial thin films. The resist is removed. The Cu and CrCu are removed by selective electroetching or chemical etching. The TiW or Cr is removed by chemical etching. The solder is treated and reflowed in an appropriate atmosphere. The wafer is diced into chips, that are joined to a carrier employing a suitable flux. Modeling, experimental matrices, process control and equipment were developed to enable great manufactur-ability and scalability of the flip-chip process. 4, 5 In order to meet the requirements of the European Union Restriction of Hazardous Substances (RoHS), lead-free solder alloy technologies have been developed.6, 7 The lead-free solders and plating processes have begun to made their way into adjacent spaces for interconnecting solar cells.8 REFERENCES 1. N.G. Koopman, T.C. Reiley, P.A. Totta, “Chip to Package Interconnections,” R. Tummala and E. J. Rymaszewski, Editors, Microelectronics Packaging Handbook, Van Nostrand Reinhold, NY, p.361(1989).2. R. A. Totta and R. P. Sopher, IBM J. Research Dev., 16, 226 (1969).3. P.A. Totta, “History of Flip Chip and Area Array Technology,” Editors K.J. Puttlitz, P.A. Totta, Area Array Interconnection Handbook, Kluwer Academic Publications, The Netherlands, p.1-36 (2001).4. M. Datta, R. V. Shenoy, C. Jahnes, P. C. Andricacos, J. Horkans, J. O. Dukovic, L. T. Romankiw, J. Roeder, H. Deligianni, H. Nye, B. Agarwala, H. M. Tong, P. Totta, J. Electrochem. Soc., 142(11), J. Electrochem. Soc., 142(11), 3778- 3785 (1995).5. US 5,516,412, “Vertical Paddle Cell,” P.C. Andricacos, K.G. Berridge, J.O. Dukovic, M. Flotta, L.T. Romankiw, K.-H. Wong, F. Spera, O. Schick, May 14, 1996.6. US 6,224,690 B1, “Flip-Chip Interconnections using Lead-free Solders,” P.C. Andricacos, M. Datta, H. Deligianni, W.J. Horkans, S. K. Kang, K.T. Kwietniak, G.S. Mathad, S. Purushothaman, L. Shi, H.-M. Tong, May 1, 2001.7. S.K. Kang, D.-Y. Shi, P. Gruber, D.W. Henderson, K.J. Puttlitz, IBM J. Research and Develop., 49(4/5), 606-620 (2005).8. P.C. Hsiao and A. Lennon, J. Electrochem. Soc., 160(10), D446-452 (2013).

Parallel C4 Packaging of MEMS Using Self-Alignment: Simulation and Experiments

Packaging is one of the major cost drivers for microelectromechanical systems (MEMS). Currently wire bonding is the dominant method for electrically connecting MEMS chips to the substrate. Using self-alignment, a method for packaging multiple MEMS at the same time has been developed. The presented process achieves high throughput and precise alignment at low cost. The controlled collapse chip connection (C4) process has been adapted to the specific requirements of MEMS. The combination of coarse robotics and liquid solder self-alignment guarantees precise positioning and alignment of the individual MEMS chips to the respective substrates. The new method has been implemented in a case study. In the study, force sensors were packaged. Precise angular alignment of the sensors is critical for making accurate measurements. Results of the case study are presented. The alignment motion is analyzed, compared with results in the literature, and simulated. These simulations, in combination with our experiments, indicate that the motion is dominated by solder-specific effects such as oxide removal, wetting, and flux solvent evaporation.

Sensorless Closed-Loop and Selective Heating for SiP MEMS Flip Chip

System-in-package (SiP) devices are increasingly becoming popular. When they are packaged using controlled collapse chip connection or derived processes, precise substrate heating at the land location is necessary. Currently, this is commonly achieved by heating the chip-handling probe. This approach restrains free motion of the chip and inhibits self-alignment of the chip to the substrate. Alternatively, the system is heated in a furnace. We present a method that heats the substrate locally at the desired spot while precisely controlling the temperature. This is achieved by embedding a Joule heater into the substrate. Additional sensors are not required because the change of the resistance of the heating, which reflects the change in temperature, is closely monitored. Because the temperature is determined inside the substrate, it provides accurate feedback of the solder's temperature. The method has been implemented and tested in an SiP microelectromechanical systems assembly process. It has proven to be a viable alternative to current methods, and features fast, localized, and tightly controlled heating and does not restrict the chip's free motion, thereby allowing chip self-alignment. Since the heating is integrated into the substrate, it also does not interfere with other components and requires no housing to protect the operators against optical radiation. Our method can be implemented at virtually no variable cost and with very low equipment costs.

Study of Warpage and Mechanical Stress of 2.5D Package Interposers during Chip and Interposer Mount Process

As data transmission rate increases, flip chip plastic ball grid array (FCPBGA) utilizing a interposer for multiple chips is gaining popularity because of high electrical performance, ease of chip design, ease of thermal management with thermal lid, etc. The authors assessed package design configuration and key design elements for two chips application assuming 1600 signal I/Os for logic and 800 signal I/Os for memory. Then, we studied warpage behavior of the interposer, and mechanical stress of solder interconnections and low-k dielectric layer under controlled collapse chip connection (C4) pad. We set three different mount process assumptions for chip to interposer and interposer to base organic substrate. The mount process assumptions are (1) two pass reflow of chip to interposer first, then interposer to base organic substrate, (2) reversed sequence of two pass reflow which is interposer to base organic substrate first, then chip to interposer, (3) one pass reflow of chip, interposer and base organic substrate all together. We also set three different interposer material assumptions of Si, glass and organic in this study. We analyzed warpage behavior and mechanical stress using finite element method (FEM) modeling technique with a set of combinations of coefficient of thermal expansion (CTE) and elastic modulus of the interposers. The study also includes an analysis for conventional multi-chip-module (MCM) FCPBGA as a reference. We show the analysis results of interposer warpage, first principal stress at low-k dielectric layer under C4 pad and von Mises stress at solder interconnections of chip joining and interposer joining.

Assessment of XRF Technique as a Method to Measure Percent Ag in SnAg Solders for Flip Chip Applications

Pb-free SnAg solder has become the industry standard for fabricating flip chip interconnects utilizing C4 (controlled collapse chip connection) technology. One area of interest for manufacturability of Pb-free solders is the ability to control and measure the %Ag composition and its variation from wafer to wafer, chip to chip, and C4 to C4. There are various ways to measure solder composition. These are divided into two categories which are invasive and non-invasive referring to whether solder must be removed from the wafer in order to conduct the measurement. There are a variety of invasive methods including Atomic Absorption (AA), Differential Scanning Calorimetry (DSC), Inductively Coupled Plasma (ICP) and Electron Probe Micro-Analyzer (EPMA) used with cross sections. Non-invasive methods are limited, making the development of the non-invasive X-Ray Fluorescence (XRF) method an important technique to determine both the thickness and composition of C4s on wafers without modifying the wafer. There are many factors which can affect the accuracy of the XRF measurements. These include bump geometry, composition, UBM (under bump metallurgy) stack, bump spatial density, underlying chip wiring, tool vibration and tool parameters, such as collimator size, power levels, scan time, etc. This paper will address the implementation issues in utilizing XRF for Pb-free solder SnAg systems. The paper will describe:(1) Experimental bumping variables,(2) XRF configuration, calibration, optimized measuring methodology and the importance of having known standards with the same dimensions of the bumps being measured(3) Measuring accuracy and correlation with ICP and DSC,(4) Ag distribution study in the die and wafer level

Residual Stress Properties of Nickel and Copper Deposits Used for C4 Interconnects

Semiconductor packaging technology requires understanding how the fundamental materials properties of different structures interact to impact the final reliability of the system, how to measure those properties and how to control them. We investigated the impact of residual stress of electrodeposited Ni (sulfamate) and Cu (sulfate and MSA) deposits that are used for C4 (controlled collapse chip connection) interconnects using X-ray lattice distortion method, sin2ψ and wafer bow measurement as a function of thermal excursions up to 400 C. The impact of this stress on the final reliability of a flip chip package was studied in order to determine useful guidelines to limit post-plate process temperatures, to conduct anneals when possible, to establish best known methods to monitor plated materials stresses and to develop methods to maintain and condition chemical plating baths to control those deposits. Finally, dynamic SIMS was utilized to aid in the interpretation of those data.

Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies

3-D integrated circuits promise high bandwidth, low latency, low device power, and a small form factor. Increased device density and asymmetrical packaging, however, renders the design of 3-D power delivery a challenge. We investigate in this paper various methods to improve 3-D power delivery. We analyze the impact of through-silicon via (TSV) size and spacing, of controlled collapse chip connection (C4) spacing, and of dedicated power delivery TSVs. In addition to considering typical cylindrical or square metal-filled TSVs (core TSVs), we also investigate using coaxial TSVs for power delivery resulting in reduced routing blockages and added coupling capacitance. Our 3-D evaluation system is composed of a quad-core chip multiprocessor, a memory die, and an accelerator engine, and it is evaluated using representative SPEC benchmark traces. This is the first detailed architectural-level analysis for 3-D power delivery. Our findings provide clear guidelines for 3-D power delivery design. More importantly, we show that it is possible to achieve 2-D-like, or even better, power quality by increasing C4 granularity and by selecting suitable TSV size and spacing.

Micro Structure Observation and Reliability Behavior of Peripheral Flip Chip Interconnections with Solder-Capped Cu Pillar Bumps

PoP (Package on Package) structures have been used widely in digital consumer electronics products such as digital still cameras and mobile phones. However, the final stack height from the top to the bottom package for these structures is higher than that of the current stacked die packages. To reduce the height of the package, a flip chip technology is used. Since the logic chips of mobile applications use a pad pitch of less than 80 μm or less, an ultra-fine-pitch flip chip interconnection technique is required. The C4 (Controlled Collapse Chip Connection) flip chip technology is widely used in area array flip chip packages. The C4 was named after the four initial characters which are C of Controlled Collapse Chip Connection. The collapse of the molten solder is controlled by the individual opening of solder resist on each pad on the substrate so that the chip can be connected onto the substrate. However, C4 is not suitable in the ultra-fine-pitch flip chips because the such a individual opening which is suitable for the ultra-fine-pitch cannot be made on the substraete. Instead of the C4 flip chip technology, the new interconnection technique was developed using the solder capped Cu pillar bumps. It is very easy to control the space between the die and the substrate by adjusting the Cu pillar height even when a large slit window opening exists on a group of pads on the substrate. Since the collapse control of the solder bumps is not necessary, we call the process C2 (Chip Connection). The C2 was named after the two initial characters which are C of Chip Connection. The solder capped Cu pillar bumps are connected to Cu substrate pads, which are a surface treated with OSP (Organic Solder Preservative), by reflow with no-clean processes. This technology creates the SMT (Surface Mount Technology)/flip chip hybrid assembly for SoP (System on Package) use. We have produced 50 μm pitch interconnections and observed the micro structure and tested their reliability. Some voids in the solder joint were observed after the reflow process. The results of warpage measurements and FEM (Finite Element Method) analyses suggest that these voids are the shrinkage voids caused by the wide temperature range of the solder liquid phase and the substrate warpage. Since they are not the stress induced voids, they didn't affect the reliability test. The increase in interconnection resistance during the reliability test was compared between the C2 interconnection and Au stud-solder interconnection. Since the resistance increase of the C2 interconnection is much smaller than that for the Au stud-solder interconnection, it is clear that the C2 flip chip technology provides robust solder connections at low cost. Also the C2 structure with a low-k device was evaluated and no failures were observed at 1,500 cycles in the TC (Thermal Cycle) test. In addition to the fine-pitch interconnections, a die thickness of 70 μm is required to reduce the final stack height. The reliability performance of the C2 flip chip with the die thicknesses 20 μm, 70 μm and 150 μm was also discussed using a PEG (Post-Encapsulation Grinding) method in which the die is ground to less than 70 μm after joining and underfilling. Finally the electromigration tests were performed on the 80 μm pitch C2 interconnection. The tests showed that the solder capped Cu pillar structure has high endurance against electromigration and no failure data was recorded up to 1,000 hrs with several electromigration conditions regardless the direction of electron flow.

3D chip stacking with C4 technology

Three-dimensional (3D) integration technology promises to continue enhancing integrated-circuit system performance with high bandwidth, low latency, low power, and a small form factor for a variety of applications. In this work, conventional C4 (controlled-collapse chip connection) technology is studied for robust interconnection between stacked thin chips. Various solder hierarchies to enable 3D chip stacking and packaging are investigated. Examples are presented to compare stacking schemes with sequential and parallel reflow. Chips as thin as 90 µm are stacked using conventional chip-placement and reflow processes, and the associated process challenges are investigated and discussed. Warpage of the thin chips is measured on various substrates. Rework of the chip stack has also been demonstrated through a temporary chip attachment operation, and the scalability of reworkable C4 is investigated.

Large-Scale Correlations in the Orientation of Grains in Lead-Free Solder Joints

A large number of lead-free Sn-Ag-Cu controlled collapse chip connection (C4) solder joints (∼100 μm in diameter) in flip-chip microelectronic packages were studied by electron backscatter diffraction (EBSD) in order to describe the statistical distribution of grain size and coincident site lattice boundaries associated with 60 deg twins in the Sn phase, as a function of silver content. It is shown that lower silver content results in smaller grains, and a lower propensity for grains to exhibit twinning symmetries. Indirect measurements of the creep properties of these joints were also obtained as a function of silver content, showing that, in the strain rate and temperature conditions that are the most relevant to the microelectronic industry, solder joints with low silver content are more susceptible to creep deformation.

Sea-of-Leads MEMS I/O Interconnects for Low-k IC Packaging

Technology feasibility of MEMS-type chip I/O interconnects (namely Sea-of-Leads or SoL) is demonstrated. Acting like a spring, a MEMS lead can provide high mechanical compliance to compensate for mismatch of coefficient of thermal expansion (CTE) between a Si chip and a composite substrate. The compliant interconnects can provide low-stress connection between a chip and a PWB substrate, and, therefore, are promising to enable wafer-level packaging of IC chips with mechanically weak low-k interlayer dielectrics (ILD). The compliant interconnection also eliminates the need for an expensive underfilling process, which is one of the key challenges for scaling of conventional controlled collapse chip connection (C4) solder bumps in organic flip-chip packages. For the first time, SoL MEMS interconnects were investigated through the whole procedure of process integration, assembly, as well as reliability assessment. Without underfill, the SoL MEMS interconnects survived more than 500 thermal cycles indicating a promising improvement over a regular C4 solder joint. Failure analysis suggests that the MEMS leads do not fracture while failure occurs close to solder-Cu pad interface due to a nonreliable joining. Full reliability potential of the SoL MEMS interconnects may be demonstrated upon optimization of PWB metallurgy, soldermask design and lead compliance.

Predicting the Liquid Formation for the Solder Joints in Flip Chip Technology

An accurate and efficient analytical geometric method is presented for predicting the geometric parameters of the controlled collapse chip connection type solder joint using direct chip attach technology after a reflow process. By this method, the meridian of the solder joint is first discretized as a series of sufficiently fine fragmental arcs. After calculating the internal pressure inside the molten eutectic solder from the forces balance, the meridional and circumferential radii of curvature of each arc are then obtained from the Laplace-Young equation. As a result, the coordinates of each node of the arc and the solder joint geometry can be determined in turn. The factors that affect the final shape of the molten eutectic solder joints, including the solder volumes, external loading, pad size, surface tension of molten eutectic solder, and interfacial surface tension between the molten eutectic solder and the solid high-lead bump are considered herein. The results computed by the analytical geometric method are also compared with those obtained using the Surface Evolver program, the extended Heinrich’s model, and the experimental results. The results of the various approaches are mutually consistent.