An important variable affecting the production throughput in the wafer fabrication photolithography area is the work-in-process (WIP) level of control wafers. Previous research work has focused on control wafers downgrading problem, and little work has been done for WIP level of control wafers. The objective of this paper is to develop methods for estimating the WIP level of control wafers for each grade, while maintaining the same level of production throughput. Two factors are considered, the re-entrant of control wafers within the same grade and the downgrading of control wafers among different grades. Under pulling control production environment, a multi-loop algorithm is developed for estimating the WIP control wafers for each grade. We conduct some simulation experiments based on a real-world factory production environment to demonstrate the effectiveness of the proposed algorithm. The results show that the algorithm is an efficient tool for estimating the cycle time and WIP level for each grade of control wafers.
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