Control Flow Checking Technique Research Articles

A software control flow checking technique in multi-core processors

Multi-core processors can benefit performance, power consumption and level of parallelism, which is the primary reason why they are employed in safety-critical embedded systems. Nowadays the use of safety-critical multi-core embedded systems in different industries is growing significantly. In these systems, an error may result in a severe failure which can lead to disaster. In order to prevent such failure, the fault tolerance of the systems should be improved. Some of the important errors, which can cause failures, are the control flow errors changing the execution flow of a multi-core program and eventually leading to core failure. To detect them, different control flow checking techniques have been proposed, almost all of which have so far aimed to detect errors in single-core processors. In this paper, a software control flow checking technique in multi-core processors, called SCFC-MC, has been proposed wherein, in addition to executing the program, each thread monitors the execution flow of another thread, thereby eliminating every single point of failure. Experimental results show that applying SCFC-MC to a quad-core processor [Intel(R) Core(TM) i7-4710HQ] results in the detection of about 95% of control flow errors with less than 20% performance overhead.

A software control flow checking technique in multi-core processors

A software control flow checking technique in multi-core processors

Control Flow Checking or Not? (for Soft Errors)

Huge leaps in performance and power improvements of computing systems are driven by rapid technology scaling, but technology scaling has also rendered computing systems susceptible to soft errors. Among the soft error protection techniques, Control Flow Checking (CFC) based techniques have gained a reputation of being lightweight yet effective. The main idea behind CFCs is to check if the program is executing the instructions in the right order. In order to validate the protection claims of existing CFCs, we develop a systematic and quantitative method to evaluate the protection achieved by CFCs using the metric of vulnerability. Our quantitative analysis indicates that existing CFC techniques are not only ineffective in providing protection from soft faults, but incur additional performance and power overheads. Our results show that software-only CFC protection schemes increase system vulnerability by 18%--21% with 17%--38% performance overhead and hybrid CFC protection increases vulnerability by 5%. Although the vulnerability remains almost the same for hardware-only CFC protection, they incur overheads of design cost, area, and power due to the hardware modifications required for their implementations.

Bipartite graph-based control flow checking for COTS-based small satellites

Single event upset (SEU) effect, caused by highly energized particles in aerospace, threatens the reliability and security of small satellites composed of commercial-off-the-shelves (COTS). SEU-induced control flow errors (CFEs) may cause unpredictable behavior or crashes of COTS-based small satellites. This paper proposes a generic software-based control flow checking technique (CFC) and bipartite graph-based control flow checking (BGCFC). To simplify the types of illegal branches, it transforms the conventional control flow graph into the equivalent bipartite graph. It checks the legality of control flow at runtime by comparing a global signature with the expected value and introduces consecutive IDs and bitmaps to reduce the time and memory overhead. Theoretical analysis shows that BGCFC can detect all types of inter-node CFEs with constant time and memory overhead. Practical tests verify the result of theoretical analysis. Compared with previous techniques, BGCFC achieves the highest error detection rate, lower time and memory overhead; the composite result in evaluation factor shows that BGCFC is the most effective one among all these techniques. The results in both theory and practice verify the applicability of BGCFC for COTS-based small satellites.

An efficient control-flow checking technique for the detection of soft-errors in embedded software

In this paper, we propose a new technique to improve the efficiency of control-flow checking for detecting soft-errors in embedded software. The novelties of the proposed technique are as follows: (1) the frequency of used variables and the frequency of the execution of basic blocks are used as two parameters for selecting important variables and basic blocks, (2) kernel blocks (i.e., a subset of the program’s flowgraph vertices) are used for the selection of important basic blocks, and (3) using the proposed method, developers can make a trade-off between the detection latency and the performance overheads. The experimental evaluations using several benchmarks showed that the execution time in the hardened code is less than the relationship signatures for control flow checking (RSCFC) method, while the memory overhead and code size remains nearly the same. The execution time of the hardened code also remains nearly the same as the original code.

Error Detection Enhancement in PowerPC Architecture-based Embedded Processors

This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. To enhance the error detection coverage, three other mechanisms, i.e., Machine Check Exception, System Trap Instructions and Work Load Timer are combined with the Branch Trace Exception mechanism. The proposed technique is experimentally evaluated on a 32-bit PowerPC microcontroller using software implemented fault injection (SWIFI) and Power Supply Disturbances fault injection (PSD). A total of 6,000 faults were injected in microcontroller to measure the error detection coverage of the proposed control flow checking technique. The experimental results show that this technique detects about 95.2% of transient errors in software implemented fault injection method and 96.4% of transient errors in power supply disturbances fault injection method.

CFCET: A hardware-based control flow checking technique in COTS processors using execution tracing

This paper presents a behavioral-based error detection technique called control flow checking by execution tracing (CFCET) to increase concurrent error detection capabilities of commercial off-the-shelf (COTS) processors. This technique traces the program jumps graph (PJG) at run-time and compares it with the reference jumps graph to detect possible violations caused by transient faults. The reference graph is driven by a preprocessor from the source program. The idea behind the CFCET is based on using an external watchdog processor (WDP) and also the internal execution tracing feature available in COTS processors to monitor the addresses of taken branches in a program, externally. This is done without any modification of application programs, thus, the program overhead is zero. This technique is analytically evaluated based on three different fault models. The results show that the error detection coverage varies between 79.74% and 96.43% depending on the different workload programs. The errors are detected with about zero latency. The external hardware overhead is about 3% using the Altera flex 10K30 FPGA and the execution time overhead is between 33.26% and 140.81% for different workload programs. The overheads have been measured experimentally by executing the workloads on a Pentium system.