Continuous Valued Number System Research Articles

An Analog CVNS-Based Sigmoid Neuron for Precise Neurochips

In this paper, the design and implementation of an analog sigmoid neuron is presented. The activation function of the proposed neuron is implemented based on the piecewise linear approximation in the analog domain. The proposed neuron provides the required accuracy that cannot be achieved in general by analog neural network implementations. General digital outputs of a sigmoid neuron are replaced with fewer analog digits of the continuous valued number system (CVNS), while at the same time maximum approximation error is kept the same as the digital architectures. The proposed CVNS neuron resulted in an optimal ASIC implementation and is suitable for neurochips with on-chip learning. The VLSI implementation of the neuron is carried out using current-mode circuits. The implementation results compare favorably with previously developed structures in terms of area, delay, and power consumption. The proposed neuron structure occupies 28% less area compared with the state-of-the-art methods and it has two times lower power $\times $ delay.

Mixed-signal VLSI neural network based on Continuous Valued Number System

Mixed-signal neural networks have higher energy efficiency and lower area consumption when compared with their equivalent digital implementations. However, the signal processing precision in mixed-signal implementations is limited. A mixed-signal arithmetic method called Continuous Valued Number Systems (CVNS) is employed for development and implementation of different functions required in a neuronal network. Analog digits of this number system enable the higher accuracy of analog operations, and can efficiently relate with digital and binary values. In this paper, design and implementation of a 2-2-1 mixed-signal CVNS network structure is presented, to confirm the developed arithmetic method. In the proposed structure, weights are stored in the digital registers while the arithmetic is based on the CVNS. The CVNS features have been exploited to address the limited signal processing precision issue, which requires resolutions higher than 12-bit for online training of the network. As a result, the proposed structure satisfies this requirement of neural networks, while yielding an optimized network configuration. The proposed network is designed, fabricated, and tested in 0.18μm technology.

CVNS Synapse Multiplier for Robust Neurochips With On-Chip Learning

Designing low noise-to-signal-ratio (NSR) structures is one of the main concerns when implementing hardware-based neural networks. In this paper, a new continuous valued number system (CVNS) multiplication algorithm for low-resolution environment is proposed with accurate results. Using the proposed CVNS multiplication algorithm, VLSI implementation of a high-resolution mixed-signal CVNS synapse multiplier for neurochips with on-chip learning is realized. The proposed CVNS multiplication algorithm provides structures with lower NSR. Therefore, the proposed CVNS multiplication algorithm can be exploited to design robust CVNS Adaline for neurochips with on-chip learning.

Area-efficient robust Madaline based on continuous valued number system

Achieving a low Noise-to-Signal Ratio (NSR) is one of the major concerns when implementing hardware-based neural networks. Continuous Valued Number System (CVNS) features have been exploited to improve the NSR. The efficiency of the network model in terms of area, power consumption, and NSR is measured using the product of the total number of neurons in the network multiplied by the network NSR, which indicates the number of neurons required for a specific NSR. The network proposed in this paper stores the weights in digital registers while the processing is done in the analog domain using CVNS arithmetic. The mathematical analysis and comparison between the proposed network and the previous structures prove that the proposed architecture improves upon in terms of both the NSR and the product of neuron multiplied by NSR.

A Prototype CVNS Distributed Neural Network Using Synapse-Neuron Modules

Continuous valued number system (CVNS) has the fulfilment of being used for building resistive-type distributed neural networks (DNNs). CVNS DNNs benefit form scalability and higher noise immunity compared to the conventional DNNs. In this paper, CVNS is used to design synapse-neuron modules to cope with the environment resolution. These modules can be employed as building blocks of distributed neural networks. A 4-3-2 network is designed and trained to justify the functionality of the proposed structure. This prototype is simulated and laid out in 0.18 μm CMOS technology.

ERROR RECOVERY IN CONTINUOUS VALUED NUMBER SYSTEM

Continuous valued number system is a novel number system which can be employed for developing analog signal processing units. It is a continuous number system which is represented by a set of continuous digits. One of the main features of this system is that digits share information, and have a digit-level redundancy. This redundancy is used to protect the digits against environment imperfections when implemented by analog circuits. In this paper, integrity of this number system in representing real values is explored. The study is required to show the effect of implementation imperfections which is an indicative of its feasibility. Effects of possible errors and error threshold for implementing this system are studied in this paper. An error recovery method is proposed, which enhances this number system representation. An efficient error recovery method extends the application of this number system in high density memory and storage devices for hardware implementations of neural networks.

CVNS-Based Storage and Refreshing Scheme for a Multi-Valued Dynamic Memory

Multi-valued dynamic memories are appropriate for applications such as implementation of neural networks, where massive number of synaptic weights have to be stored on a chip. In this paper, a novel storage and refreshing configuration to store up to 4 bits (16 levels) per cell on a dynamic memory is proposed. This configuration is based on the Continuous Valued Number System (CVNS). Error correction method according to the CVNS properties is used in order to increase the noise margin of memory cells. Furthermore, by decreasing the leakage current, the refresh cycle time is increased. The circuits are designed, simulated, and finally laid out using 90-nm CMOS technology.

Resistive-Type CVNS Distributed Neural Networks With Improved Noise-to-Signal Ratio

Resistive-type distributed neural networks (DNNs) provide a self-scaling structure for the neuron, which can spontaneously adapt itself to different numbers of inputs. In lumped neural networks, the neuron should be changed whenever the number of inputs changes due to the applications; redesigning the neuron is not practical, particularly for hardware implementations. In this brief, a group of feedforward DNNs based on a continuous valued number system is proposed, which outperforms not only the lumped neural networks but also the conventional DNNs because of the reduced sensitivity to noise.

16-level CVNS memory with fast ADC

A novel 16-level current-mode DRAM based on the continuous valued number system (CVNS) representation is introduced. The refreshing circuitry of this DRAM is designed using analogue to digital converter (ADC) and digital to analogue converter modules. Each ADC generates two bits of the output simultaneously which decreases the delay time of the ADC module. Error correction codes are used to increase the noise margin by a factor of two. The proposed memory can be used in hardware implementation of CVNS based systems.

Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing

In this paper, design of a mixed-signal 64-bit adder based on the continuous valued number system (CVNS) is presented. The 64-bit adder is generated by cascading four 16-bit radix-2 CVNS adders. Truncated summation of the CVNS digits reduced the number of required interconnections in the system, which in turn reduced design complexity and hardware costs. This adder can perform one 64-bit, two 32-bit, four 16-bit, or eight 8-bit additions on demand for media signal processing applications. The compact and low-power and low-noise design of the adder is suitable for this type of application. The 64-bit adder designed in TSMC CMOS 0.18-mum technology, has a worst case delay of 1.5 ns, energy dissipation of about 14 pJ with the core area of 13 250mum2.

Robust low-sensitivity Adaline neuron based on Continuous Valued Number System

In this article Continuous Valued Number System is studied as an alternative method for implementing Analog Neural Networks. Continuous Valued Number System is analog in nature and employs digit level analog modular arithmetic. The information redundancy among the digits allows efficient operations using analog circuitry with arbitrary accuracy. The general operations in this number system are more precise than regular analog operations, thus enabling us to implement large size analog neural networks with more precision. In this article, function evaluation properties of the Continuous Valued Number System are introduced. These key properties are used for developing analog Adaline with a nonlinear activation function. Stochastic modeling of a network of such elements is carried out which indicates that the proposed network has low sensitivity to implementation errors.