Abstract
Achieving a low Noise-to-Signal Ratio (NSR) is one of the major concerns when implementing hardware-based neural networks. Continuous Valued Number System (CVNS) features have been exploited to improve the NSR. The efficiency of the network model in terms of area, power consumption, and NSR is measured using the product of the total number of neurons in the network multiplied by the network NSR, which indicates the number of neurons required for a specific NSR. The network proposed in this paper stores the weights in digital registers while the processing is done in the analog domain using CVNS arithmetic. The mathematical analysis and comparison between the proposed network and the previous structures prove that the proposed architecture improves upon in terms of both the NSR and the product of neuron multiplied by NSR.
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