Continuous-time Loop Filter Research Articles

Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition

The recent developments in biosignal acquisition devices for continuous supervision of cardiovascular signs of high-risk patients require a high-precision and low-power Analog Front End (AFE) circuit. The proposed design adopts Continuous-Time (CT) Sigma-Delta Modulator (ΣΔM) architecture to achieve high resolution and SIgnal-to-Noise And Distortion ratio (SINAD) requirements. The proposed modulator is a second-order CT-ΣΔM with Cascade of Integrators Feed-Forward (CIFF) architecture that consists of a CT loop filter, a single-bit quantizer, and a Digital-to-Analog Converter (DAC). The use of single-bit quantization in the design reduces circuit complexity and power consumption. To use the designed ΣΔM for measuring ECG signals, a bandwidth (Bw) of 150 Hz is considered with a sampling frequency (fs) of 153.6kHz to achieve an oversampling ratio of 512. The design is simulated in a standard Cadence Virtuoso EDA tool at 180nm CMOS technology, operating at 1.8V supply voltage at the block level. The simulation results for the designed modulator show that SINAD is 104.5dB, the Effective Number Of Bits (ENOB) is 17.06bits, with power consumption of 24µW, and achieves Schreier’s Figure-Of-Merit (FOM) equal to 172.45dB.

A novel two-channel continuous-time time-interleaved 3rd-order sigma-delta modulator with integrator-sharing topology

This paper presents a 3rd-order two-path continuous-time time-interleaved (CTTI) delta-sigma modulator which is implemented in standard 90 nm CMOS technology. The architecture uses a novel method to resolve the delayless feedback path issue arising from the sharing of integrators between paths. By exploiting the concept of the time-interleaving techniques and through the use time domain equations, a conventional single path 3rd-order discrete-time (DT) ΔΣ modulator is converted into a corresponding two-path discrete-time time-interleaved (DTTI) counterpart. The equivalent CTTI version derived from the DTTI ΔΣ modulator by determining the DT loop filters and converting them to the equivalent continuous-time loop filters through the use of the Impulse Invariant Transformation. Sharing the integrators between two paths of the reported modulator makes it robust to path mismatch effects compared to the typical time-interleaved modulators which have individual integrators in all paths. The modulator achieves a dynamic range of 12 bits with an OverSampling Ratio of 16 over a bandwidth of 10 MHz and dissipates only 28 mW of power from a 1.8-V supply. The clock frequency of the modulator is 320 MHz but integrators, quantizers and DACs operate at 160 MHz.

Current mode sigma-delta modulator designed with the help of transistor’s size optimization tool

Abstract The paper presents a second order current mode sigma-delta modulator designed with the help of a new elaborated tool to optimize the transistor sizes. The circuit is composed of two continuous time loop filters, a current comparator and a one bit DAC with a current output. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 250 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 53.6 dB while dissipating 93 μW, which corresponds to an efficiency of 59.7 fJ/conv. The fully current mode structure makes the circuit suitable to be applied in a current mode signal processing like biosensors or image pixels arrays.

Analytical Expressions for the Distortion of Asynchronous Sigma–Delta Modulators

This brief investigates the commonly used asynchronous sigma-delta modulator, which consists of a Schmitt trigger and a continuous-time loop filter. A detailed analysis is presented to accurately predict the distortion of such modulators. The extracted expressions are compared with simulation results, and they illustrate an excellent match. The results are also compared with a previous work by Roza, and they show a drastic improvement in accuracy.

A 1-V 13-mW Single-Path Frequency-Translating $\Delta \Sigma $ Modulator With 55-dB SNDR and 4-MHz Bandwidth at 225 MHz

This paper presents a frequency-translating bandpass ΔΣ modulator that uses single-path mixing within the ΔΣ feedback loop to downconvert a 4-MHz signal band from IF1 = 225 MHz at the input to IF2 = 25 MHz at the output. The proposed ΔΣ modulator is designed with a sixth-order continuous-time loop filter and a 3-bit quantizer. The quantizer operates at a sampling frequency of 100 MHz, which is lower than IF1 and, therefore, reduces both the power consumption and the sensitivity to timing errors relative to a conventional bandpass ΔΣ modulator. Furthermore, the loop filter implements noise shaping primarily at IF 2, which reduces the sensitivity to coefficient variations. The prototype chip was fabricated in 65-nm CMOS with an active area of 0.55 mm2. It achieves an SNDR of 55 dB over a 4-MHz signal bandwidth, and consumes 13 mW from a 1-V power supply.

A Bufferless Interface for Single-Ended ECM Sensors

This paper presents a bufferless interface that can be directly connected to a single-ended capacitive sensor such as an electret condenser microphone. A high-input impedance interface is developed using only a continuous-time loop filter, whereas conventional interface circuits are composed of a buffer, a preamplifier, an antialiasing filter, and a high-order switched-capacitor loop filter. Equipped with an active <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gm</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> integrator, this interface chip is designed to implement all the required functions, i.e., high-input impedance buffering, preamplification, antialiasing filtering, and analog-to-digital conversion. The inherent antialiasing filtering function also provides a significant advantage in terms of silicon areas and power consumption. The complete interface channel achieves a 75-dB dynamic range and a 60.3-dB signal-to-noise-plus-distortion ratio over a 25-kHz signal band, which satisfies the requirements for electret microphones. The power consumption of the interface channel is 600 μW, and the chip dissipates a total of 860 μW from the 3.3-V supply.

A hybrid CT/DT double-sampled SMASH Σ∆ modulator for broadband applications in 90 nm CMOS technology

In this paper, a hybrid continuous-time (CT)/discrete-time (DT) multi-stage noise shaping (MASH) sigma---delta (ΣΔ) modulator architecture for broadband applications is presented. The double-sampling technique is employed in the DT second-stage modulator in order to reduce the power consumption of the overall modulator. Flat and unity signal transfer functions are used in the first- and second-stage modulators, respectively, to relax the output swing of the analog building blocks without influencing the inherent anti-aliasing behavior of the first-stage CT modulator. The proposed structure is insensitive to the amplifier limited dc gain of CT stage and avoids the need of compensation for finite gain-bandwidth induced error in CT loop filter. As a design example, the proposed MASH 2-2 modulator is designed in a 90 nm CMOS technology with 1 V power supply. Circuit level simulation results with HSPICE achieve the maximum SNDR of 74.8 dB and dynamic range of 76.5 dB in 12.5 MHz bandwidth with 17 mW power consumption while operating at 200 MHz sampling rate.

A Discrete-Time Model for the Design of Type-II PLLs With Passive Sampled Loop Filters

Type-II charge-pump (CP) phase-locked loop (PLLs) are used extensively in electronic systems for frequency synthesis. Recently, a passive sampled loop filter (SLF) has been shown to offer major benefits over the conventional continuous-time loop filter traditionally used in such PLLs. These benefits include greatly enhanced reference spur suppression, elimination of CP pulse-position modulation nonlinearity, and, in the case of phase noise cancelling fractional-N PLLs, improved phase noise cancellation. The main disadvantage of the SLF to date has been the lack of a linear time-invariant (LTI) model with which to perform the system-level design of SLF-based PLLs. Without such a model, designers are forced to rely on trial and error iteration supported by lengthy transient simulations. This paper presents an accurate LTI model of SLF-based type-II PLLs that eliminates this disadvantage.

LOW-VOLTAGE DOUBLE-SAMPLED HYBRID CT/DT ΣΔ MODULATOR FOR WIDEBAND APPLICATIONS

A hybrid continuous-time (CT)/discrete-time (DT) multi-stage noise-shaping (MASH) ΣΔ modulator architecture is presented. The double-sampling technique is employed in the DT second stage modulator. A flat and a unity signal transfer functions (STFs) are used in the first and second stage modulators, respectively, to make the modulator robust to nonlinearities of the analog circuitry and well suited for low-voltage applications without influencing the inherent anti-aliasing behavior of the first stage CT modulator. Unlike the conventional MASH architecture, this structure is insensitive to the amplifier limited DC gain of CT stage and avoids the need of compensation for finite gain-bandwidth induced error in CT loop filter. Behavioral simulations confirm the effectiveness of the proposed scheme over existing cascaded topologies.

Sensitivity of single-bit continuous-time analogue-to-digital converters to out-of-band blockers

The sensitivity of single-bit continuous-time (CT) ΔΣ analogue-to-digital converters to out-of-band (OOB) blockers received in companion with desired signals is investigated. In essence, the residual interferer signal appearing at the output of the CT loop filter can flip the single-bit quantiser decision near the zero crossings of the loop filter output signal. An intuitive analysis of this effect on the performance of single-bit ΔΣ modulators in the presence of OOB interferers is provided. System level simulations for a single-bit fifth-order CT ΔΣ modulator at an oversampling ratio of 40 have been carried out. A reduction in the achievable signal-to-noise-plus-distortion ratio, that can be as large as 10 dB when applying a 0 dBFS OOB blocker tone along with a weak −75 dBFS desired tone, has been observed. The simulation results show good agreement with the adopted theoretical discussion.

A 56 mW Continuous-Time Quadrature Cascaded $\Sigma\Delta$ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band

A quadrature cascaded modulator with continuous-time loop filters is presented for a digital multi-stream FM radio receiver. The ADC achieves a dynamic range of 77 dB and 20 MHz bandwidth centered on an intermediate frequency of 10.5 MHz and is sampling at 340 MHz. The cascaded modulator comprises programmable analog second-order quadrature filters and a digital quadrature noise cancellation filter. The 0.5 chip in 90 nm CMOS consumes 56 mW from a 1.2 V supply.

A 70-MHz Continuous-Time CMOS Band-Pass ΣΔ Modulator for GSM Receivers

A 70-MHz continuous-time CMOS band-pass ΣΔ modulator for GSM receivers is presented. Impulse-invariant-transformation is used to transform a discrete-time loop-filter transfer function into continuous-time. The continuous-time loop-filter is implemented using a transconductor-capacitor (Gm-C) filter. A latched-type comparator and a true-single-phase-clock (TSPC) D flip-flop are used as the quantizer of the ΣΔ modulator. Implemented in a MOSIS HP 0.5-μm CMOS technology, the chip area is 857 μm × 420 μm, and the total power consumption is 39 mW. At a supply voltage of 2.5 V, the maximum SNDR is measured to be 42 dB, which corresponds to a resolution of 7 bits.

A 0.2-mW CMOS ΣΔ modulator for speech coding with 80 dB dynamic range

A CMOS /spl Sigma//spl Delta/ modulator for speech coding with continuous-time loopfilter is presented. Compared to switched-capacitor implementations, the relaxed bandwidth requirements of the active elements of the loopfilter reduce the power consumption. Furthermore, the need for an antialiasing filter at the modulator input is eliminated. A fourth-order, 64/spl times/ oversampling /spl Sigma//spl Delta/ modulator for application in portable telephones was designed and shows 80 dB dynamic range over the 300-3400 Hz voice bandwidth. Its input is directly connected to the microphone (maximum 40 mV/sub RMS/). Total harmonic distortion (THD) is below -70 dB at 95 /spl mu/A current consumption from a 2.2 V supply voltage. The active die area of the modulator is 0.5 mm/sup 2/ in a standard 0.5-/spl mu/m CMOS process.