Abstract
This paper presents a 3rd-order two-path continuous-time time-interleaved (CTTI) delta-sigma modulator which is implemented in standard 90 nm CMOS technology. The architecture uses a novel method to resolve the delayless feedback path issue arising from the sharing of integrators between paths. By exploiting the concept of the time-interleaving techniques and through the use time domain equations, a conventional single path 3rd-order discrete-time (DT) ΔΣ modulator is converted into a corresponding two-path discrete-time time-interleaved (DTTI) counterpart. The equivalent CTTI version derived from the DTTI ΔΣ modulator by determining the DT loop filters and converting them to the equivalent continuous-time loop filters through the use of the Impulse Invariant Transformation. Sharing the integrators between two paths of the reported modulator makes it robust to path mismatch effects compared to the typical time-interleaved modulators which have individual integrators in all paths. The modulator achieves a dynamic range of 12 bits with an OverSampling Ratio of 16 over a bandwidth of 10 MHz and dissipates only 28 mW of power from a 1.8-V supply. The clock frequency of the modulator is 320 MHz but integrators, quantizers and DACs operate at 160 MHz.
Highlights
The rapid growth of the portable communication device markets such as audio systems and consumer electronics has been led to an increasing demand for low power high resolution ADC designs over the last decade [1]
It consists of an Anti-Aliasing Filter (AAF), a sampler and an Noise Transfer Function (NTF) of its DT equivalent
Removing the input demultiplexer has no effect on the NTF of the discrete-time time-interleaved (DTTI) DR modulator but it causes some notches in its Signal Transfer Functions (STF) at the following frequencies 0:5Fclk; 1:5Fclk; 2:5Fclk; 3:5Fclk; . . . which is shown in Fig. 10 where Fclk is the clock frequency of the DTTI DR modulator [9]
Summary
The rapid growth of the portable communication device markets such as audio systems and consumer electronics has been led to an increasing demand for low power high resolution ADC designs over the last decade [1]. The DR modulator can achieve a very high resolution analog-todigital conversion for relatively low-bandwidth signals through the use of the oversampling and the noise shaping technique. The signal bandwidth the DR modulators can deal with is narrow and is restricted by the OSR and technology deployed. To increase the signal bandwidth the modulator can process, a variety of methods are used: the first one is to increase the order of the modulator, but at a price, where the stability problem requires to be dealt with very carefully [2]. The fourth method that is one of the more practical ways is to deploy a CT loop filter coupled with the time-interleaving technique [3]. Analog Integrated Circuits and Signal Processing (2018) 95:375–385 transformation are reviewed. 5, circuit design and simulations are reviewed.
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