This special issue of the Analog Integrated Circuits and Signal Processing presents seven papers in the area of ‘‘Advanced Design Techniques for Wireless Communications’’. New design methodologies, EDA tools and radio transceivers architectures and topologies for emerging wireless technologies are presented. The papers presented in this issue were selected based both on the overall quality of the paper and on the timeliness of the topic. The selected papers reflect continuing trends toward higher levels of analog and digital circuit techniques covering a wide variety of subjects within the Analog Integrated Circuits and Signal Processing fields, ranging from RF/analog and mixed-signal circuits and systems to design methodologies and tools for telecommunications applications. In the first paper, C-Y Wu, W-C Wang, F. R Shahroury, Z-D Huang and H-J Zhan present current-mode design techniques for CMOS RF circuits, which have been developed and employed to implement a 24-GHz CMOS receiver front-end. A receiver front-end, which comprises a current-mode LNA and a current-mode downconversion mixer, has been fabricated in 0.13-lm CMOS technology. The measurement results demonstrate the feasibility of the current-mode techniques for CMOS RF circuits, showing a conversion gain of 11.3 dB, a noise figure of 14.2 dB, the input-referred 1-dB compression point of –13.5 dBm and the input-referred third-order intercept point of -1 dBm. T-Y Lo, C-S Kao and C-C Hung present in their paper a CMOS 3rd order Butterworth low-pass Gm-C filter for multi-mode wireless applications. A transconductor based on flipped-voltage follower circuit and an active resistor working in the strong inversion to achieve the transconductance tuning is designed for multi-mode implementations. The theoretical analysis and a complete set of measurement results demonstrate that the proposed filter is suitable for IEEE 802.11a/b/g/n Wireless LANs. The filter can operate with a cutoff frequency of 10 to 20 MHz, and has a maximum power consumption of 13 mW from a 1.8-V supply voltage. The third paper, by L-F Tanguay and M. Sawan, presents the architectural choices and design of a fully integrated integer-N frequency synthesizer operating in the 902–928 MHz ISM band. This ultra-low power frequency synthesizer is integrated in a transceiver for implantable wireless sensing microsystems, targeting in vivo monitoring of biological parameters. The phase-locked loop-based synthesizer includes a 1.830 GHz LC voltage controlled oscillator using a 10 nH on chip inductor. Varactors are implemented using P? in N-well diodes for their linearity and high quality factor. Several innovative design techniques have been employed to reduce the power consumption of the proposed synthesizer to 580 lW under 1 V, which is almost an order of magnitude lower compared to the recent synthesizer designs having a similar architecture. Yi Ke, S. Radiom, J. Craninkx, G. Vandenbosch and G. Gielen present a systematic design methodology for high-order multi-bit Continuous-Time Sigma-Delta modulators. The proposed strategy provides a straightforward method for determining the coefficients of the modulator, starting with the design of the modulator in z-domain and then converting it into the s-domain. The method is illustrated for a 4th-order 4-bit modulator with an OSR of 8 and a 20 MHz signal bandwidth. The simulation results show A. Rusu (&) M. Ismail ECS, ICT, Royal Institute of Technology (KTH), Stockholm, Sweden e-mail: arusu@kth.se