Continuous-time Sigma-delta ADC Research Articles

A 65-dB SNDR Continuous-Time Delta-Sigma ADC Integrated by IZO Thin-Film Transistors

A 65-dB SNDR Continuous-Time Delta-Sigma ADC Integrated by IZO Thin-Film Transistors

Complete design approach of a 3rd order continuous-time sigma-delta ADC with FIR feedback and low-noise low-distortion op-amp achieving 101.8 dB SNDR and −110dB THD

This paper presents a step-by-step design approach of a 3rd order continuous-time sigma-delta modulator with a 4-tap FIR feedback DAC achieving 107 dB DR (A-weighted), −110 dB THD and an SNDR of 101.8 dB. The THD is achieved through a fully differential feed-forward compensated op-amp that maintains high linearity with the aid of a class AB output stage and an optimum bias current through a CMFB loop. The modulator consumes 322.5uW of power while taking an area of 0.2925 mm2.

Withdrawal: P. A. Harsha Vardhini and M. Makkena (2022), Design and Comparative Analysis of On‐Chip Sigma Delta ADC for Signal Processing Applications. Advanced Control for Applications: Engineering and Industrial Systems. Accepted Author Manuscript e82. https://doi.org/10.1002/adc2.82

Advent in VLSI technology made digital signal processing to take over analog signal processing. Analog to digital converter plays a vital role in modern digital processing applications. Sigma delta analog to digital converter architecture being digital dominant architecture is much suitable for signal processing applications. This paper presents the design of a low pass continuous time sigma delta analog to digital converter on-chip architecture suitable for signal processing applications with a very few passive components connected externally to FPGA. Schematic level architecture of high-speed comparator working at a differential swing which is not allowed by standard differential pads is designed. By applying various differential swings at the input to LVPECL, the performance and power is analyzed. High performance comparator schematic is designed for On-chip Continuous-time Sigma-delta ADC architecture. Simulations are carried out to verify the maximum input frequency for given RC values. Xilinx provided Spartan 6 I/O pad and package SPICE models are used. Power analysis is carried out with LVPECL logic family based differential buffers along with external RC circuit. The analog and digital sections simulations along with mixed signal simulations at different stages are performed. Power and performance analysis are carried out using H-Spice and Questasim simulations.

A 78-MHz BW Continuous-Time Sigma-Delta ADC with Programmable VCO Quantizer

This article presents a high speed third-order continuous-time (CT) sigma-delta analog-to-digital converter (SDADC) based on voltage-controlled oscillator (VCO), featuring a digital programmable quantizer structure. To improve the overall performance, not only oversampling technique but also noise-shaping enhancing technique is used to suppress in-band noise. Due to the intrinsic first-order noise-shaping of the VCO quantizer, the proposed third-order SDADC can realize forth-order noise-shaping ideally. As a bright advantage, the proposed programmable VCO quantizer is digital-friendly, which can simplify the design process and improve anti-interference capability of the circuit. A 4-bit programmable VCO quantizer clocked at 2.5 GHz, which is proposed in a 40 nm complementary metal-oxide semiconductor (CMOS) technology, consists of an analog VCO circuit and a digital programmable quantizer, achieving 50.7 dB signal-to-noise ratio (SNR) and 26.9 dB signal-to-noise-and-distortion ration (SNDR) for a 19 MHz − 3.5 dBFS input signal in 78 MHz bandwidth (BW). The digital quantizer, which is programmed in the Verilog hardware description language (HDL), consists of two-stage D-flip-flop (DFF) based registers, XOR gates and an adder. The presented SDADC adopts the cascade of integrators with feed-forward summation (CIFF) structure with a third-order loop filter, operating at 2.5 GHz and showing behavioral simulation performance of 92.9 dB SNR over 78 MHz bandwidth.

Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback

We present the design principles and circuit details of a single-bit continuous-time delta-sigma ADC that achieves 13.3-bit resolution over a 20-MHz signal bandwidth. The modulator, which operates at a sampling rate of 2.56 GHz in a 65-nm CMOS process, uses a 2 $\times $ time-interleaved ADC to address the problem of comparator metastability. A 4 $\times $ time-interleaved virtual-ground-switched resistive FIR feedback DAC is used for low distortion and power-efficient operation. Interleaving artifacts caused by DAC-element mismatch are addressed by mixed-signal calibration, which is enabled by the DAC architecture. The decimator is implemented using poly-phase techniques. A prototype modulator, which operates with a 1.1-V supply, achieves 82.1-dB peak SNDR and THD of 98.6 dBc while consuming 11.3 mW. The resulting Schreier FoM is 174.1 dB. The decimator dissipates 13.5 mW.

34.3 fJ/conv.-step 8-MHz Bandwidth Fourth-Order Pseudo-Differential Ring-Amplifier-Based Continuous-Time Delta–Sigma ADC in 65 nm

This letter presents two pseudo-differential ring amplifiers (RAs) suitable for a continuous-time (CT) operation as an alternative to traditional amplifiers. The designs retain the advantages of RAs, scale with process technology, and do not require a periodic reset. The RAs are designed to operate in an integrator configuration and use different methods to achieve stability in continuous time. A prototype was fabricated in a 65-nm CMOS containing two versions of a CT delta–sigma ADC using the two RAs presented. The ADCs consist of a fourth-order loop filter with optimized zeros, a single-bit quantizer that operates at a sampling frequency of 320 MHz, and a digital-to-analog converter. The best design proposed achieves a measured peak signal-to-noise and distortion ratio of 50.6 dB for an 8-MHz bandwidth, a dynamic range of 53.2 dB, and consumes 152 ${\mu }\text{W}$ at a supply of 1.1 V. The obtained figure of merit is 34.3 fJ/conv.-step which outperforms state-of-the-art delta–sigma ADCs in that specification range and is 77% superior to its traditional operational transconductance amplifier-based ADC counterpart.

A continuous-time delta-sigma ADC for portable ultrasound scanners

A fully differential fourth-order 1-bit continuous-time delta-sigma ADC designed in a 65 nm process for portable ultrasound scanners is presented in this paper. The circuit design, implementation and measurements on the fabricated die are shown. The loop filter consists of RC-integrators, programmable capacitor arrays, resistors and voltage feedback DACs. The quantizer contains a pulse generator, a high-speed clocked comparator and a pull-down clocked latch to ensure constant delay in the feedback loop. Using this implementation, a small and low-power solution required for portable ultrasound scanner applications is achieved. The converter has a supply voltage of 1.2 V, a bandwidth of 10 MHz and an oversampling ratio of 16 leading to an operating frequency of 320 MHz. The design occupies a die area of $$0.0175\hbox { mm}^2$$ . Simulations with extracted parasitics show a SNR of 45.2 dB and a current consumption of $$489 \,\upmu \hbox {A}$$ . However, by adding a model of the measurement setup used, the performance degrades to 42.1 dB. The measured SNR and current consumption are 41.6 dB and $$495\,\upmu \hbox {A}$$ , which closely fit with the expected simulations. Several dies have been measured, and an estimation of the die spread distribution is given.

A continuous-time delta-sigma ADC with integrated digital background calibration

This work presents a digital calibration technique in continuous-time (CT) delta-sigma ($$\Delta \Sigma$$ΔΣ) analog to digital converter. The converter is clocked at 144 MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT $$\Delta \Sigma$$ΔΣ converter with digital background calibration circuit has been designed, simulated and implemented in 65 nm CMOS process. The maximum simulated signal-to-noise and distortion ratio is 67.1 dB within 9 MHz bandwidth.

Continuous-Time Delta-Sigma ADCs With Improved Interferer Rejection

This paper reviews and analyzes the state of the art of Delta-Sigma modulators for receiver applications. Receiver ADCs require not only steadily increased bandwidth, low power and area consumption, but especially face strong interferer signals. These are outside the band of interest, but they most often determine the overall receiver dynamic range and linearity requirements. In order to avoid or at least relax explicit filtering in front of the ADC, Delta-Sigma architectures have been presented with improved robustness to interferers by filtering. This paper intends to review the motivation, to give a tutorial of the state of the art, as well as to introduce a deeper analysis for DSM with interferer robustness. For this, an introduction to the requirements of Delta-Sigma modulators in receivers is given, and a method is introduced which allows to analyze and to scale the internal states meeting the requirements of the interferer scenarios. The paper additionally analyzes state-of-the-art techniques of modulators with improved interferer rejection in order to outline more clearly their possibilities and drawbacks.

Noise-Shaping Cyclic ADC Architecture

This paper presents an ADC architecture comprising a pipelined cyclic ADC and continuous-time delta-sigma ADC; it provides high resolution at medium speed, with small power requirements. It is also reconfigurable for different combinations of speed, precision, and power consumption. The cyclic ADC produces a residue after the final cycle, and the following delta-sigma ADC converts it to a digital value (the residue is then noise-shaped). The ADC output combines the digital outputs of the cyclic ADC and the delta-sigma ADC so as to achieve high resolution. The delta-sigma ADC can be implemented simply with continuous-time analog circuitry. We describe the overall ADC architecture and operation, show simulation results, as well as features such as its potential for reconfiguration and one of ADC architecture candidates with good tradeoff for high resolution, medium speed and small power.

Fast Lock-in Time Phase Locked Loop Frequency Synthesizer for Continuous-Time Sigma-Delta ADC

A phase locked loop circuit that uses Phase Frequency Detector with NOR gates and divide-by-64 with pseudo-NMOS divide-by-2 frequency divider is proposed, designed and simulated in TSMC 0.18um 1P6M CMOS process technology to come up with minimum chip area and achieve fast lock-in time. This PLL design is specifically intended for Continuous-Time Sigma-Delta ADC operating at 640MHz frequency which is an important component of ICs used in electronics and communication devices whose clock rates and timing relationships are vital. This work has a lock-time of around 2.5us which is a fast lock-in value for the lock-in time of ADC clock generator. The desired output frequency which is 640 MHz is achieved on all corners ranging from 608 MHz to 672 MHz which is within 640MHz ±5% tolerance. In terms of the charge pump current, the proposed design used 77uA which is within the typical values of charge pump current ranging from 10uA to 100u. The PLL displays minimum total chip core area which is 8.3393 nm 2 and 0.2049 um 2 for off-chip and on-chip filter, respectively. 

Analog design-for-testability technique for first-order sigma delta ADC

In this paper, a design for testability of 10 bits continuous time sigma delta ADC is presented. This new full test technique provides: simple way, 2 external lines and high testability for the circuit’s performances. This test is used for different sub-circuits evaluation and characterization to determine the contribution of each part in the total ADC error thus the ADC design can be improved. Using standard CMOS 0.24μm technology this technique is implemented, the obtained results confirm that the presented technique ensures a high ADC testability, and the suitability for use with integrated circuit (IC) post development design is demonstrated.

2011 IEEE Journal of Solid-State Circuits Best Paper Award Given to Bolatkale, Breems, Rutten, and Makinwa for ?A 4-GHz Continuous-Time Delta-Sigma ADC with 70-dB DR and -74 dBFS THD in 125-MHz BW? [People

The article 4-GHz Continuous-Time Δ-ΣADC with 70-dB DR and -74 dBFS THD in 125-MHz BW by Muhammed Bolatkale, Lucien J. Breems, Robert Rutten, and Kofi A.A. Makinwa, published in IEEE Journal of Solid-State Circuits (JSSC), vol. 46, no. 12, pp. 2857-2868, Dec. 2011, was declared best of all in JSSC 2011. The authors' novel approach modifies loop filter architecture to deal with the parasitics and excess delay of the large comparator array in the 4-GHz multibit quantizer. Their five-times improvement in bandwidth compared to state-of-theart CMOS delta-sigma modulators enlarges the application domain of these ADCs, enabling them to compete with high speed architectures like pipeline ADCs. A detailed review of the article is provided.

Continuous time sigma delta ADC design and non-idealities analysis

A wide bandwidth continuous time sigma delta ADC is implemented in 130 nm CMOS. A detailed non-idealities analysis (excess loop delay, clock jitter, finite gain and GBW, comparator offset and DAC mismatch) is performed developed in Matlab/Simulink. This design is targeted for wide bandwidth applications such as video or wireless base-stations. Athird-order continuous time sigma delta modulator comprises a third-order RC operational-amplifier-based loop filter and 3-bit internal quantizer operated at 512 MHz clock frequency. The sigma delta ADC achieves 60 dB SNR and 59.3 dB SNDR over a 16-MHz signal band at an OSR of 16. The power consumption of the CT sigma delta modulator is 22 mW from the 1.2-V supply.

An adaptive high-voltage protection and common-mode adjustment circuit for passive–active continuous-time sigma–delta ADCs

A digitally-programmable circuit is proposed to provide high-voltage protection at start-up, overload, and supply loss conditions in continuous-time passive---active sigma delta ADCs implemented in low-voltage nanometer CMOS technologies. The circuit optimizes the common-mode level at the input stage of the ADC enabling it to interface with input levels beyond its own supply voltage with no impact on device reliability or distortion levels, and minimum impact on area and noise performance, which provides maximum flexibility in the ADC usage. The proposed circuit along with the full ADC is implemented in a typical 65 nm CMOS technology.

A 1.2-MHz 10-bit Continuous-Time Sigma–Delta ADC Using a Time Encoding Quantizer

This paper shows the operating principle and experimental results of a new continuous-time sigma-delta modulator architecture. The proposed modulator does not require a multibit quantizer nor a mismatch-shaping digital-to-analog converter to produce a multibit noise-shaped output. Instead, its quantizer encodes the loop filter output in a binary signal using a time encoding technique similar to pulsewidth modulation. This binary signal is used to generate both the analog feedback loop signal and the digital output. A proof-of-concept chip in 0.35-mum CMOS achieves 10 bits of resolution within a signal bandwidth of 1.2 MHz using a first-order modulator.

A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply

Pick the right timing for low-power conversion

The authors have built a high-speed implementation using a 130nm process to offer a low-power alternative to the pipeline converter with resolutions up to 14 bit. A common way to compare the performance of ADCs in absolute terms is the energy figure-of-merit (FOM). The Xignal ADC provides a 76dB SNR at an input frequency of 6MHz for a power consumption of only 60mW for the ADC core. That leads to an FOM of 0.79pJ/conversion. The authors used a third-order continuous-time sigma-delta modulator, designed around a 4bit quantizer stage so that it could achieve considerable dynamic range at an over-sampling rate of 16. The differential input signal path has a bandwidth of 30MHz. The internal sample clock operates at 640MHz. The base technology today allows for increased sample rates to 80Msample/s (at Mbit) with an over-sampling clock rate of approximately 1.3GHz. The continuous-time sigma-delta ADC approach shows tremendous promise. Initial results are encouraging and it is believed that the architecture has a clear advantage with its ability to scale with CMOS process developments and yield further increases in efficiency and speed. This is a major benefit, as pipeline design will become ever more challenging within the restrictive confines of the CMOS process roadmap with its sub-bandgap threshold requirements.

A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution

A wide-bandwidth continuous-time sigma-delta ADC is implemented in a 0.13-/spl mu/m CMOS. The circuit is targeted for wide-bandwidth applications such as video or wireless base-stations. The active blocks are composed of regular threshold voltage devices only. The fourth-order architecture uses an OpAmp-RC-based loop filter and a 4-bit internal quantizer operated at 300-MHz clock frequency. The converter achieves a dynamic range of 11 bits over a bandwidth of 15 MHz. The power dissipation is 70 mW from a 1.5-V supply.