Context Switching Time Research Articles

A new median-average round Robin scheduling algorithm: An optimal approach for reducing turnaround and waiting time

A variety of algorithms handles processes on the CPU. The round-robin algorithm is an efficient CPU scheduling mechanism for a time-sharing operating system. The system processes the methods based on the time slice; however, determining the time slice has proven highly challenging for the researchers. As a result, a variety of dynamic time quantum scheduling techniques are presented by various academics to address this challenge. This study aims to determine how to best schedule resources to maximize efficiency. It is important to note that this scheduling mechanism rotates between the processes after the static quantum time is complete. However, the quantum decision affects how effectively and efficiently the procedures may be scheduled. Additionally, the quantum decision has an impact on the scheduling of processes. The average waiting time, turnaround time, and context switch times of the Round Robin scheduling algorithm are high enough to influence the system's performance. To get over the round-drawbacks, robin's the authors in this study suggest using the improved algorithm Median-Average Round Robin (MARR). Using the median and average of the burst time of each process, the author proposes a dynamic time quantum for the system. The authors compared the proposed model with four other scheduling algorithms. The results vividly depict that the proposed algorithms successfully give effective results with reduced average turnaround time and waiting time. In the future, cost and RAM utilization will be considered to enhance the algorithm.

An Overview of the nMPRA and nHSE Microarchitectures for Real-Time Applications.

In the context of real-time control systems, it has become possible to obtain temporal resolutions of microseconds due to the development of embedded systems and the Internet of Things (IoT), the optimization of the use of processor hardware, and the improvement of architectures and real-time operating systems (RTOSs). All of these factors, together with current technological developments, have led to efficient central processing unit (CPU) time usage, guaranteeing both the predictability of thread execution and the satisfaction of the timing constraints required by real-time systems (RTSs). This is mainly due to time sharing in embedded RTSs and the pseudo-parallel execution of tasks in single-processor and multi-processor systems. The non-deterministic behavior triggered by asynchronous external interrupts and events in general is due to the fact that, for most commercial RTOSs, the execution of the same instruction ends in a variable number of cycles, primarily due to hazards. The software implementation of RTOS-specific mechanisms may lead to significant delays that can affect deadline requirements for some RTSs. The main objective of this paper was the design and deployment of innovative solutions to improve the performance of RTOSs by implementing their functions in hardware. The obtained architectures are intended to provide feasible scheduling, even if the total CPU utilization is close to the maximum limit. The contributions made by the authors will be followed by the validation of a high-performing microarchitecture, which is expected to allow a thread context switching time and event response time of only one clock cycle each. The main purpose of the research presented in this paper is to improve these factors of RTSs, as well as the implementation of the hardware structure used for the static and dynamic scheduling of tasks, for RTOS mechanisms specific to resource sharing and intertask communication.

Low-overhead dynamic sharing of graphics memory space in GPU virtualization environments

The proliferation of GPU intensive workloads has created a new challenge for low-overhead and efficient GPU virtualization solutions over GPU clouds. gVirt is a full GPU virtualization solution for Intel’s integrated GPUs that share system’s on-board memory for graphics memory. In order to solve the inherent scalability limitation on the number of simultaneous virtual machines (VM) in gVirt, gScale proposed a dynamic sharing scheme for global graphics memory among VMs by copying the entries in a private graphics translation table (GTT) to a physical GTT along with a GPU context switch. However, copying entries between private GTT and physical GTT often causes significant overhead, which becomes worse when the global graphics memory space shared by each VM is overlapped. This paper identifies that the copy overhead caused by GPU context switch is one of the major bottlenecks in performance improvement and proposes a low-overhead dynamic memory management scheme called DymGPU. DymGPU provides two memory allocation algorithms such as size-based and utilization-based algorithms. While the size-based algorithm allocates memory space based on the memory size required by each VM, the utilization-based algorithm considers GPU utilization of each VM to allocate memory space. DymGPU is also dynamic in the sense that the global graphics memory space used by each VM is rearranged at runtime by periodically checking idle VMs and GPU utilization of each runnable VM. We have implemented our proposed approach in gVirt and confirmed that the proposed scheme reduces GPU context switch time by up to 53% and improved the overall performance of various GPU applications by up to 39%.

Liquid Silicon-Monona

With the recent trend of promoting Field-Programmable Gate Arrays (FPGAs) to first-class citizens in accelerating compute-intensive applications in networking, cloud services and artificial intelligence, FPGAs face two major challenges in sustaining competitive advantages in performance and energy efficiency for diverse cloud workloads: 1) limited configuration capability for supporting light-weight computations/on-chip data storage to accelerate emerging search-/data-intensive applications. 2) lack of architectural support to hide reconfiguration overhead for assisting virtualization in a cloud computing environment. In this paper, we propose a reconfigurable memory-oriented computing fabric, namely Liquid Silicon-Monona (L-Si), enabled by emerging nonvolatile memory technology i.e. RRAM, to address these two challenges. Specifically, L-Si addresses the first challenge by virtue of a new architecture comprising a 2D array of physically identical but functionally-configurable building blocks. It, for the first time, extends the configuration capabilities of existing FPGAs from computation to the whole spectrum ranging from computation to data storage. It allows users to better customize hardware by flexibly partitioning hardware resources between computation and memory, greatly benefiting emerging search- and data-intensive applications. To address the second challenge, L-Si provides scalable multi-context architectural support to minimize reconfiguration overhead for assisting virtualization. In addition, we provide compiler support to facilitate the programming of applications written in high-level programming languages (e.g. OpenCL) and frameworks (e.g. TensorFlow, MapReduce) while fully exploiting the unique architectural capability of L-Si. Our evaluation results show L-Si achieves 99.6% area reduction, 1.43× throughput improvement and 94.0% power reduction on search-intensive benchmarks, as compared with the FPGA baseline. For neural network benchmarks, on average, L-Si achieves 52.3× speedup, 113.9× energy reduction and 81% area reduction over the FPGA baseline. In addition, the multi-context architecture of L-Si reduces the context switching time to - 10ns, compared with an off-the-shelf FPGA (∼100ms), greatly facilitating virtualization.

ODSA: A Novel Ordering Divisional Scheduling Algorithm for Modern Operating Systems

CPU scheduling is defined as scheduling multiple processes that are required to be executed in a specific time period. A large number of scheduling algorithms have been proposed to achieve maximum CPU utilization/throughput and minimizing turn around, waiting and response time. Existing studies claim that Round Robin (RR) is providing best results in terms of above-mentioned factors. In RR, a process is assigned to CPU for a fixed time quantum then the process starts its execution, in case that assigned time quantum greater than CPU’s capacity then remaining section of that process waits for its next turn. Although RR schedules processes in an efficient manner, however, it has certain limitations such as if time quantum is too small or large, it causes frequent context switching and response time can increase. To address these identified problems, various improved versions of RR also exist. The purpose of this paper is twofold: 1) a comparison between different improved versions of RR; and 2) a new algorithm named Ordering Divisional Scheduling Algorithm (ODSA) is also proposed that combines various features of different algorithms and is actually an improvement to RR. Our results show that ODSA can schedule processes with less turn around and average waiting time as compared to existing solutions.

Efficient Management of PCM-based Swap Systems with a Small Page Size

Due to the recent advances in non-volatile memory technologies such as PCM, a new memory hierarchy of computer systems is expected to appear. In this paper, we explore the performance of PCM- based systems and discuss how this system can be managed efficiently. Specifically, we introduce three management techniques. First, we show that the page fault handling time can be reduced by attaching PCM on DIMM slots, thereby eliminating the software stack overhead of block I/O and the context switch time. Second, we show that it is effective to reduce the page size and turn off the read-ahead option under the PCM system where the page fault handling time is sufficiently small. Third, we show that the performance is not degraded even with a DRAM memory under a PCM device; this leads to the reduction of DRAM's energy consumption significantly compared to HDD-based systems. We expect that the result of this paper will lead to the transition of the legacy system structure of large memory - slow swap to a new paradigm of small memory - fast swap.

Evaluations of Hardware and Software-Based Context Switching Methods in Cortex-M3 for Embedded Applications

In contrast to the previous ARM microprocessor, the ARM Cortex-M3 processor provides a method for accelerating context switching, which is supported by dedicated hardware logic vis a software interrupt (or trap). In general, it is expected that retaining the context of a task using hardware will reduce the context switching time, but it is also known that software interrupts or traps incur their own overheads. In this study, we propose an algorithm for analyzing the performance of context switching methods in uC/OS-II the Cortex-M3. According to our experimental analysis, we obtained the same results using the algorithm in an ideal state and in a real application. We expect that the algorithms and experimental results described in this study may help embedded system designers by providing quantitative measures in the context switching time of Cortex-M3 using a real-world application.

AN IMPROVED APPROACH TO MINIMIZE CONTEXT SWITCHING IN ROUND ROBIN SCHEDULING ALGORITHM USING OPTIMIZATION TECHNIQUES

Scheduling is a fundamental operating system function. Almost all computer resources are scheduled before use. All major CPU scheduling algorithms concentrates more on to maximize CPU utilization, throughput, waiting time and turnaround time. In particularly, the performance of round robin algorithm depends heavily on the size of the time quantum. To improve the performance of CPU and to minimize the overhead on the CPU, time quantum should be large with respect to the context switch time. Otherwise, context switching will be more. In this research paper, we propose a method to minimize the context switching and to break the fixed time quantum size in round robin scheduling algorithm using optimization techniques. Both results and calculations show that, our proposed method is more efficient than the existing round robin scheduling algorithm.

Global EDF-Based On-Line Energy-Aware Real-Time Scheduling Algorithm in Multi-Core Systems

PDF HTML阅读 XML下载 导出引用 引用提醒 多核系统中基于Global EDF 的在线节能实时调度算法 DOI: 10.3724/SP.J.1001.2012.04054 作者: 作者单位: 作者简介: 通讯作者: 中图分类号: 基金项目: 国家教育部博士点基金(20104307110005); 湖南省优秀研究生创新资助(CX2010B026); 国防科学技术大学优秀研究生创新资助(B100601) Global EDF-Based On-Line Energy-Aware Real-Time Scheduling Algorithm in Multi-Core Systems Author: Affiliation: Fund Project: 摘要 | 图/表 | 访问统计 | 参考文献 | 相似文献 | 引证文献 | 资源附件 | 文章评论 摘要:随着多核系统能耗问题日益突出,在满足时间约束条件下降低系统能耗成为多核实时节能调度研究中亟待解决的问题之一.现有研究成果基于事先已知实时任务属性的假设,而实际应用中,只有当任务到达之后才能够获得其属性.为此,针对一般任务模型,不基于任何先验知识,提出一种多核系统中基于Global EDF 在线节能硬实时任务调度算法,通过引入速度调节因子,利用松弛时间,结合动态功耗管理和动态电压/频率调节技术,降低多核系统中任务的执行速度,达到实时约束与能耗节余之间的合理折衷.所提出的算法仅在上下文切换和任务完成时进行动态电压/频率调节,计算复杂度小,易于在实时操作系统中实现.实验结果表明,该算法适用于不同类型的片上动态电压/频率调节技术,节能效果始终优于Global EDF 算法,最多可节能15%~20%,最少可节能5%~10%. Abstract:As the energy consumption of multi-core systems becomes increasingly prominent, meeting the time constraints while reducing as much as possible system energy consumption is still an urgent problem in real-time energy-aware scheduling in multi-core system. Most existing works have assumptions on priori information of real-time tasks, but in real applications the tasks’ property be received only when the tasks arrive. Therefore, based on the general task model with no priori to tasks’ properties, this paper proposes a global EDF-based on-line energy-aware scheduling algorithm for hard real-time tasks in multi-core system. The proposed algorithm can reduce the execution speed of task in multi-core system and reach a reasonable compromise between real-time constraints and energy savings, as it introduces a speed scale factor for utilizing the slack time and combines dynamic power management with dynamic voltage/frequency scaling techniques. The algorithm implements dynamic voltage/frequency scaling only in each context switch time and task completion time, with the smaller computational complexity, and easier to be included in real-time operating system. Experimental results show that the algorithm can be well applied to different kinds of dynamic voltage/frequency scaling on chip, and compared with Global EDF algorithm, it gain more energy savings in all cases, which can improve energy savings about 15% to 20% at most and about 5% to 10% at least. 参考文献 相似文献 引证文献

Improved Round Robin Scheduling using Dynamic Time Quantum

Round Robin scheduling algorithm is the widely used scheduling algorithm in multitasking and real time environment. It is the most popular algorithm due to its fairness and starvation free nature towards the processes, which is achieved by using the time quantum. As the time quantum is static, it causes less context switching incase of high time quantum and high context switching incase of less time quantum. Increasing context switch leads to high avg. waiting time, high avg. turnaround time which is a overhead and degrades the system performance. So, the performance of the system solely depends upon the choice of optimal time quantum which is dynamic in nature. In this paper, we have proposed a new variant of RR scheduling algorithm known as Improved Round Robin (IRR) Scheduling algorithm, by arranging the processes according to their shortest burst time and assigning each of them with an optimal time quantum which is able to reduce all the above said disadvantages. Experimentally we have shown that our proposed algorithm performs better than the RR algorithm, by reducing context switching, average waiting and average turnaround time.

Optimization of Network Packet Scheduling–using Multi Objective Genetic Algorithm with Virtual Deadline as a Schedule Parameter

paper presents a novel approach to improve the performance of multimedia oriented systems by using Multi Objective Genetic Algorithm(MOGA) along with the concept of virtual deadline to efficiently schedule and optimize the real-time network packets thereby reducing the packets loss and delay. MOGA along with virtual deadline is capable of outperforming the Dynamic Window Constraint Scheduling(DWCS) by servicing jobs with different request periods .Additionally, MOGA with virtual deadline yields better results than Virtual Deadline Scheduling(VDS) because the context switching time is less in the former. Eventually, an implementation of MOGA with virtual deadline as a schedule parameter in the Linux Kernel with the help of Wireshark, a network protocol analyzer that captures the real- time network packets, which produces better scheduling results than DWCS and VDS.

Finite state machine-based DRAM power management with early resynchronisation

An efficient operating system-based power management scheme for DRAM in the multiprogramming/time-sharing environment is presented. Formulas for evaluating the condition of positive energy gain are developed and a finite state machine (FSM) for selecting the best power mode for a given idle time is designed. In the proposed scheme, the scheduler selectively assigns the most efficient power mode to each idle memory bank at context switching time based on the FSM. For computing the idle time, two efficient and practical prediction methods are developed and tested for performance. The proposed scheme achieves further energy saving by starting the resynchronisation of idle memory banks as early as possible. In the aspects of the prediction method and the early resynchronisation method, multiple versions of the proposed scheme are developed and tested for performance. The proposed scheme utilises events occurring at context switching time in the multiprogramming/time-sharing environment and the scheduling ensures the maximum energy gain without significantly degrading the performance. The proposed scheme is tested with a simulated system, and the experimental results demonstrate the efficiency of the scheme. In the experiment, the energy gain by using the proposed scheme ranges from 17.84% to 52.21% depending on the time quantum sizes tested.

Handoff Procedure for Seamless Service in IP and OFDM Based 4G Mobile Systems

We propose an efficient and practical seamless handoff scheme for 4G mobile systems based on IP and OFDM. The seamless handoff scheme obtains the physical channel for handoff in a contention-free manner with pre-synchronization and pre-forwarding IP contexts. As a result, it thoroughly decreases the physical channel blocking time as well as IP layer context-switching time to minimize total handoff delay.

Weaves: A Framework for Reconfigurable Programming

This paper presents a language independent runtime framework--called Weaves--for object based composition of unmodified code modules that enables selective sharing of state between multiple control flows through a process. Furthermore, the framework allows dynamic instantiation of code modules and control flows through them. In effect, weaves create intra-process modules (similar to objects in OOP) from code written in any language. Applications can be built by instantiating Weaves to form Tapestries of dynamically interacting code. The framework enables objects to be arbitrarily shared--it is a true superset of both processes as well as threads, with code sharing and fast context switching time similar to threads. Weaves does not require any special support from either the language or application code--practically any code can be weaved. Weaves also include support run-time loading and linking of object modules enabling the next generation of highly dynamic applications. This paper presents the elements of the Weaves framework and its implementation on the Linux platform over source-code independent ELF object files. The current implementation has been validated over Sweep3D, a benchmark for 3D discrete ordinates neutron transport (Koch et al. Trans. Am. Nucl. Soc. 65 (198) [1992]), and a user-level port of the Linux 2.4 family kernel TCP/IP protocol stack.

ECEM: an event correlation based event manager for an I/O-intensive application

In Internet servers that run on general purpose operating systems, network subsystems and disk subsystems cooperate with each other for user requests. Many studies have focused on optimizing the data movement across the subsystems to reduce data copying overhead among kernel buffers, a network send buffer and a disk buffer. When data are moved across the subsystems, events such as read requests and write requests for data movement are also delivered across the subsystems by the servers and the operating system. However, there have been fewer studies on the optimization of event delivery across the subsystems. In conventional operating systems, an event from a disk subsystem is delivered to a network subsystem regardless of the status of the network subsystem. If the network subsystem is not ready for data sending, the execution of the server will be blocked, which causes scheduling and context switching overheads. This non-contiguous execution will incur deficiencies such as avoidable process blocking, context switching, cache pollution and long response time. To alleviate the deficiencies, we have developed inter-subsystem event delivery mechanisms that define event dependencies among the subsystems involved. We define an event correlation based on the happened-before relation. We propose deferred event delivery (DED) and disk-to-network splicing (DNS) to suppress scheduling and context switching during I/O request processing. We performed experiments on Linux 2.4 and the experimental results show that the number of context switching is reduced by up to 20% and server data transmit rate is improved by 4.0–8.1%.

Analytical modeling of multithreaded architectures

Multithreading is used for hiding long memory latency in uniprocessors and multiprocessor computer systems and aims at increasing system efficiency. In such an architecture, a number of threads are allocated to each processing element (PE) and whenever a running thread becomes suspended the PE switches to another ready thread. In this paper, we discuss analytical modeling of coarsely multithreaded architectures and present two analytical models: (i) a deterministic model, where the timing parameters (e.g., context switching time, threads's run length, and memory latency) are assumed to be constant, and (ii) a stochastic model where the timing parameters are random variables. Both models provide a framework to study the dependence of the MTA efficiency on design parameters of the target architecture and its workload. The deterministic model, as well as asymptotic bounding analysis of the stochastic model, allows to determine upper bounds and some break points of the MTA efficiency such as stability (saturation) points, whereas the stochastic model provides more accurate prediction of the efficiency.

UNIDAQ, real-time response of the system

This paper describes a real-time response of UNIDAQ. Interrupt task response time and task switching (context switching) time are measured for real-time UNIX (LynxOS) systems and standard UNIX systems. Here we show the correlation between the context switching time and the values of a benchmark program, SPECint92. We also show distributions of the response time for various operating systems (OS). A performance evaluation tool, DAQBENCH, was used for the measurements.

Hardware support for fast capability-based addressing

Traditional methods of providing protection in memory systems do so at the cost of increased context switch time and/or increased storage to record access permissions for processes. With the advent of computers that supported cycle-by-cycle multithreading, protection schemes that increase the time to perform a context switch are unacceptable, but protecting unrelated processes from each other is still necessary if such machines are to be used in non-trusting environments. This paper examines guarded pointers , a hardware technique which uses tagged 64-bit pointer objects to implement capability-based addressing. Guarded pointers encode a segment descriptor into the upper bits of every pointer, eliminating the indirection and related performance penalties associated with traditional implementations of capabilities. All processes share a single 54-bit virtual address space, and access is limited to the data that can be referenced through the pointers that a process has been issued. Only one level of address translation is required to perform a memory reference. Sharing data between processes is efficient, and protection states are defined to allow fast protected subsystem calls and create unforgeable data keys.

Hardware support for fast capability-based addressing

Traditional methods of providing protection in memory systems do so at the cost of increased context switch time and/or increased storage to record access permissions for processes. With the advent of computers that supported cycle-by-cycle multithreading, protection schemes that increase the time to perform a context switch are unacceptable, but protecting unrelated processes from each other is still necessary if such machines are to be used in non-trusting environments. This paper examines guarded pointers , a hardware technique which uses tagged 64-bit pointer objects to implement capability-based addressing. Guarded pointers encode a segment descriptor into the upper bits of every pointer, eliminating the indirection and related performance penalties associated with traditional implementations of capabilities. All processes share a single 54-bit virtual address space, and access is limited to the data that can be referenced through the pointers that a process has been issued. Only one level of address translation is required to perform a memory reference. Sharing data between processes is efficient, and protection states are defined to allow fast protected subsystem calls and create unforgeable data keys.

Threads and input/output in the synthesis kernal

The Synthesis operating system kernel combines several techniques to provide high performance, including kernel code synthesis, fine-grain scheduling, and optimistic synchronization. Kernel code synthesis reduces the execution path for frequently used kernel calls. Optimistic synchronization increases concurrency within the kernel. Their combination results in significant performance improvement over traditional operating system implementations. Using hardware and software emulating a SUN 3/160 running SUNOS, Synthesis achieves several times to several dozen times speedup for UNIX kernel calls and context switch times of 21 microseconds or faster.