Content Addressable Memory Cell Research Articles

Low Power Design of 0.8V based 8 Bit Content Addressable Memory using MSML implemented in 22nm Technology for Aeronautical Applications

Proposed Paper contains Master slave match line (MSML) architecture which is implemented in traditional Content Addressable Memory (CAM) cell for storing 8 bit of data. Objective of the proposed methodology is to improve searching speed with less power consumption. MSML operation depends on two things one is Master Match Line (MML) and slave match line (SML). Design is performed using SPICE in 22nm technology which is weightless and can be used in Aeronautical Equipment. Various parameters such as temperature, power and delay are calculated for various types of CAM cell. Proposed methodology power consumption is found to be 598mw with delay of 5.98ns for 22nm technology.

Ferroelectric ternary content-addressable memory for one-shot learning

Deep neural networks are efficient at learning from large sets of labelled data, but struggle to adapt to previously unseen data. In pursuit of generalized artificial intelligence, one approach is to augment neural networks with an attentional memory so that they can draw on already learnt knowledge patterns and adapt to new but similar tasks. In current implementations of such memory augmented neural networks (MANNs), the content of a network’s memory is typically transferred from the memory to the compute unit (a central processing unit or graphics processing unit) to calculate similarity or distance norms. The processing unit hardware incurs substantial energy and latency penalties associated with transferring the data from the memory and updating the data at random memory addresses. Here, we show that ternary content-addressable memories (TCAMs) can be used as attentional memories, in which the distance between a query vector and each stored entry is computed within the memory itself, thus avoiding data transfer. Our compact and energy-efficient TCAM cell is based on two ferroelectric field-effect transistors. We evaluate the performance of our ferroelectric TCAM array prototype for one- and few-shot learning applications. When compared with a MANN where cosine distance calculations are performed on a graphics processing unit, the ferroelectric TCAM approach provides a 60-fold reduction in energy and 2,700-fold reduction in latency for a single memory search operation. A compact ternary content-addressable memory cell, which is based on two ferroelectric field-effect transistors, can provide memory augmented neural networks with improved energy and latency performance compared with traditional approaches based on graphics processing units.

Design and Performance Improvement of CNTFET Based Content Addressable Memory (CAM) Cells

The scaling down of transistors is of paramount importance to make ICs and devices more portable and efficient. As it is the most basic component of every electronic device, there is need of finding better and innovative methods of transistor characterization. CNTFET has shown the promise and is best suited for today’s faster digital processing units and Memory devices. Here Carbon Nano Tube (CNT) is characterized for its electrical property and then designed a XOR based CAM cell using CNTFET. Both delay and power analysis for the designed CAM is done.

Optical memory architectures for fast routing address look-up (AL) table operation

Today, the increasing demand for fast routing processes has turned the address look-up (AL) operation into one of the main critical performance operations in modern optical networks, since it conventionally relies on slow-performing AL tables. Specifically, AL memory tables are comprised of content addressable memories (CAMs) for storing a known route of the forwarding information base of the router, and random access memories (RAMs) for storing the respective output port for this route. They thus allow for a one-cycle search operation of a packet’s destination address, yet they typically operate at speeds well below 1 GHz, in contrast with the vastly increasing optical line rates. In this paper, we present our overall vision towards light-based optical AL memory functionalities that may facilitate faster router AL operations, as the means to replace slow-performing electronic counterparts. In order to achieve this, we report on the development of a novel optical RAM cell architecture that performs for the first time with a speed of up to 10 Gb s−1, as well as our latest works on multi-bit 10 Gb s−1 optical CAM cell architectures. Specifically, the proposed optical RAM cell exploits a semiconductor optical amplifier-Mach–Zehnder interferometer in a push-pull configuration and deep saturation regime, doubling the speed of prior optical RAM cell configurations. Error-free write/read operation is demonstrated with a peak power penalty of 6.2 dB and 0.4 dB, respectively. Next, we present the recent progress on optical CAM cell architectures, starting with an experimental demonstration of a 2-bit optical CAM match-line architecture that achieves an exact bitwise search operation of an incoming 2-bit destination address at 10 Gb s−1, while the analysis is also extended to a numerical evaluation of a multi-cell 4-bit CAM-based row architecture with wavelength division multiplexed outputs for fast parallel memory operations at speeds of up to 4 × 20 Gb s−1. Finally, we present a comparative study between electronic and optical RAMs and CAMs in terms of energy and speed and discuss the further challenges towards our vision.

Design of Magnetic Non-Volatile TCAM With Priority-Decision in Memory Technology for High Speed, Low Power, and High Reliability

Recently, various magnetic non-volatile ternary content-addressable memory (MNV-TCAM) cells that use magnetic tunnel junctions (MTJs) as storage units have been proposed to realize zero standby power. However, they still suffer from low reliability and high power consumption for search operation. In addition, the restrictions on the ordering of the TCAM array required by the using of the priority encoder to resolve the multiple match problem due to the `X' results in large delay and high energy consumption for update operation. To address these issues, the novel MNV-TCAM cell is first proposed, aiming to achieve high-speed, low-power, and high-reliable search operation. In addition to the search data operation, it can realize a search length operation. By exploiting this search length operation, we then present circuit-level design of the MNV-TCAM with a priority-decision in memory technology, which can utilize the length information of matched words sorted in an arbitrary order to decide the highest-priority matched word by performing a three-phase search operation. It implies that the restrictions on the ordering can be eliminated, thus, improving the update speed and energy-efficiency. Finally, hybrid CMOS/MTJ simulations are performed to demonstrate its functionality and evaluate its performance in terms of search reliability, search speed, and search energy consumption.

Compact and Low Power 11T-2MTJ Non-Volatile Ternary Content Addressable Memory Cell with High Sense Margin

Compact and Low Power 11T-2MTJ Non-Volatile Ternary Content Addressable Memory Cell with High Sense Margin

True Three-Valued Ternary Content Addressable Memory Cell Based On Ambipolar Carbon Nanotube Transistors

Carbon nanotube-based transistors (CNTFETs) have been shown to exhibit ambipolar field-effect transistor behavior, allowing circuit designers to easily choose between [Formula: see text]- and [Formula: see text]-conduction channels by applying correct voltages at a polarity gate. In this paper, we explore this ambipolar behavior of the CNTFET to design both binary and ternary content addressable memory (AM) cells. Using SPICE simulation, we show the designs of a traditional ternary CAM (TCAM) and a true three-valued TCAM (T3-CAM) functionality of the proposed cells and show that the ambipolar design can lead to a savings of up to 31% in terms of transistor count over a traditional design. We also explore issues related to matchline leakage, cell stability and design in the presence of metallic tubes.

A Novel MTJ-Based Non-Volatile Ternary Content-Addressable Memory for High-Speed, Low-Power, and High-Reliable Search Operation

Recently, several magnetic tunnel junction (MTJ)-based non-volatile ternary content-addressable memory (NV-TCAM) cells have been proposed to realize zero standby power. However, they still suffer from low reliability and high power consumption during search operations. To address these issues, we propose a novel MTJ-based NV-TCAM cell, which is composed of 15 transistors and 4 MTJs (15T-4MTJ). By utilizing the differential MTJs with complementary states and positive feedback of cross-coupled inverters for sensing, the proposed 15T-4MTJ NV-TCAM cell can significantly improve the search reliability. Moreover, owing to that there is no static current during search operations, only dynamic charging and discharging current, it can achieve ultra-low power consumption. In addition, by using only one transistor as the critical path between the match-line and GND, its switch delay can be shortened, thereby realizing high-speed search operations. Hybrid CMOS/MTJ simulation results of the 144-bit word circuit show that the proposed 15T-4MTJ NV-TCAM cell can obtain a smaller search error rate of 2.7%, a higher search speed of 0.17 ns, and a lower search energy of 0.17 fJ/bit/search in comparison with other MTJ-based NV-TCAM cells. On the other hand, its write energy of 1.589 pJ/bit is about 3.64× smaller than that of the previously proposed 10T-4MTJ NV-TCAM cell.

Ternary content-addressable memory with MoS2 transistors for massively parallel data search

Ternary content-addressable memory (TCAM) is specialized hardware that can perform in-memory search and pattern matching for data-intensive applications. However, achieving TCAMs with high search capacity, good area efficiency and good energy efficiency remains a challenge. Here, we show that two-transistor–two-resistor (2T2R) transition metal dichalcogenide TCAM (TMD-TCAM) cells can be created by integrating single-layer MoS2 transistors with metal-oxide resistive random-access memories (RRAMs). The MoS2 transistors have very low leakage currents and can program the RRAMs with exceptionally robust current control, enabling the parallel search of very large numbers of data bits. These TCAM cells also exhibit remarkably large resistance ratios (R-ratios) of up to 8.5 × 105 between match and mismatch states. This R-ratio is comparable to that of commercial TCAMs using static random-access memories (SRAMs), with the key advantage that our 2T2R TCAMs use far fewer transistors and have zero standby power due to the non-volatility of RRAMs. By integrating two-dimensional MoS2 transistors with metal-oxide resistive random-access memories, two-transistor–two-resistor ternary content-addressable memory cells can be created, which could be used to search large amounts of data in parallel.

An innovative radiation hardened CAM architecture

Abstract An innovative Content Addressable Memory (CAM) cell with radiation hardened (RH) architecture is presented. The RH-CAM is designed using a commercial 28 nm CMOS technology. The circuit has been simulated in worst-case conditions, and the effects due to single particles have been analyzed by injecting a current pulse into a circuit node. The proposed architecture is suitable for real-time pattern recognition tasks in harsh environments, such as front-end electronics in the ATLAS experiment at the Large Hadron Collider (LHC) and in space applications.

Compact design of an MTJ-based non-volatile CAM cell with read/write operations

This paper presents a novel design of a magnetic tunnel junction (MTJ) based content addressable memory (CAM) cell with low power dissipation and small-time delay. Magnetic properties of the spintronic device such as non-volatility, write endurance, small read–write delays, low switching current and so on, have been investigated in this paper. The proposed CAM cell design includes a simplified driver circuit to perform read/search and write operations using an optimum number of transistors. Performance parameters such as power dissipation, time-delay, power-delay product (PDP) and energy-delay product (EDP) of the proposed CAM cell are estimated and compared with the previously reported MTJ-based CAM cell already available in the literature. Simulation results obtained in this research work demonstrate that the proposed CAM cell successfully performs write operation at low voltages (up to 0.7 V). Write-time delay and the average power dissipation of the proposed CAM cell is found to be 0.375× and 0.449× less compared to the available MTJ-based CAM cell design. Apart from these, improvements in PDP and EDP of the proposed CAM cell is about 0.17× and 0.063× compared to the previously reported MTJ-based CAM cell, respectively. Performance improvements are also obtained in terms of time delay and power consumption during the read/search operations of the proposed CAM cell. During the read operation with 0.8 V supply, the time-delay, the average power consumption, PDP and EDP of the proposed CAM cell was found to be 0.53×, 0.64×, 0.34× and 0.18× less compared to the MTJ-based CAM cell already reported in the literature, respectively. Simulation results have been exhaustively verified using SPICE.

Optical Content Addressable Memory Matchline for 2-bit Address Look-Up at 10 Gb/s

We demonstrate the first experimental evaluation of a 10Gb/s optical matchline (ML) memory architecture that designates successfully whether an incoming 2-bit optical address is identical to the optical address stored in an optical content addressable memory (CAM) line. The optical CAM line is formed by two optical CAM cells, with every cell comprising a monolithically integrated InP flip-flop and an SOA-MZI-based XOR gate, while the ML is completed by a subsequent wavelength multiplexing element and a semiconductor optical amplifier-cross gain modulation gate. Error-free operation at 10Gb/s has been obtained for 2-bit optical addresses and for both content addressing and write memory functionalities.

A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme

Hardware search using content addressable memory (CAM) produces the fastest upshot but takes larger design area and consumes relatively high power. Dynamic CAM certainly is an alternative to resolve these issues, but the slower search speed and void of ternary approach act as primary design constraints. A fully ternary dynamic storage is presented for high density and low leakage associative memory. A unique self-refresh scheme is introduced with pipelined read-restore mechanism that updates the CAM cells at much lower refresh overhead. The proposed 4-kb dynamic ternary CAM structure has been designed using predictive 45-nm CMOS technology at a 48% reduced cell area than traditional ternary CAM and simulated using SPECTRE at a supply voltage of 1.0 V. The proposed design dissipates 0.583-fJ/bit/search at a search rate of 440 MHz. The refresh module has been integrated at an additional area of 1.92% and updates the TCAM at 0.21% refresh overhead.

A Content-Addressable Memory structure using quantum cells in nanotechnology with energy dissipation analysis

Quantum-dot cellular automata is one of the recent new technologies at the nanoscale that can be a suitable replacement for CMOS technology. The circuits constructed in QCA technology have desirable features such as low power consumption, high speed and small size. These features can be more distinct in memory structures. In this paper, we design a new structure for content addressable memory cell in QCA. For this purpose, first, a unique gate is introduced for mask operation in QCA and then this gate is used to improve the performance of CAM. These structures are evaluated with QCADesigner simulator.

A Non-Volatile Ternary Content-Addressable Memory Cell for Low-Power and Variation-Toleration Operation

A magnetic tunneling junction (MTJ)-based ternary content-addressable memory (TCAM) cell is proposed which consists of 12 transistors and two MTJs. The proposed TCAM cell does not have static power consumption during search operation and therefore ensures highly energy efficient operation. For search operation, the resistance of an MTJ in the anti-parallel state is compared with that of an MTJ in the parallel state and therefore the proposed TCAM cell shows excellent tolerance to the variations of device characteristics. The performance of the proposed TCAM cell is evaluated by simulation and compared with previously reported MTJ-based TCAM cells. The proposed TCAM cells show smaller failure rate of search operation under the same operating condition and device variations.

Low-power content addressable memory (CAM) array for mobile devices

Large-capacity content-addressable memory (CAM) is beneficial in a variety of applications that require high-speed lookup table. It is used extensively in low power CPU design, network routers, and cache controllers. Content addressable memory system includes CAM cells that contains a compare-circuit and a memory bit-cell that stores complementary bits. The compare circuit consists of complementary inputs to receive the complementary stored bits, and an input node to receive a single-ended reference bit. The main CAM design challenge is to reduce the power consumption associated with large amount of parallel switching circuitry, without sacrificing speed or density.This paper presents a novel CAM circuit level implementation aiming at reducing the comparator power and the crowbar current. Consequently, the average current consumption during CAM operation is reduced. In addition, the proposed circuit topology eliminates the need to route the complementary data which saves routing resources. Simulation results using 22nm process technology shows that the elimination of the crowbar current during writing operation saves 40% of power for single bit-cell CAM, while sharing the compare circuitry among 8bit-cells CAM saves 14% of the power without any performance impact regarding chip area.

Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations

Electronic Content Addressable Memories (CAM) implement Address Look-Up (AL) table functionalities of network routers; however, they typically operate in the MHz regime, turning AL into a critical network bottleneck. In this communication, we demonstrate the first steps towards developing optical CAM alternatives to enable a re-engineering of AL memories. Firstly, we report on the photonic integration of Semiconductor Optical Amplifier-Mach Zehnder Interferometer (SOA-MZI)-based optical Flip-Flop and Random Access Memories on a monolithic InP platform, capable of storing the binary prefix-address data-bits and the outgoing port information for next hop routing, respectively. Subsequently the first optical Binary CAM cell (B-CAM) is experimentally demonstrated, comprising an InP Flip-Flop and a SOA-MZI Exclusive OR (XOR) gate for fast search operations through an XOR-based bit comparison, yielding an error-free 10 Gb/s operation. This is later extended via physical layer simulations in an optical Ternary-CAM (T-CAM) cell and a 4-bit Matchline (ML) configuration, supporting a third state of the “logical X” value towards wildcard bits of network subnet masks. The proposed functional CAM and Random Access Memories (RAM) sub-circuits may facilitate light-based Address Look-Up tables supporting search operations at 10 Gb/s and beyond, paving the way towards minimizing the disparity with the frantic optical transmission linerates, and fast re-configurability through multiple simultaneous Wavelength Division Multiplexed (WDM) memory access requests.

Skewed Straintronic Magnetotunneling-Junction-Based Ternary Content-Addressable Memory—Part I

This paper presents a ternary content-addressable memory (TCAM) cell based on a skewed straintronic magnetotunneling junction (MTJ) switch. A straintronic magnetotunneling junction (s-MTJ) is a three-terminal switch, where the resistance between two of the terminals switches when a potential is applied to the third (gate) terminal that induces strain in the magnetostrictive free-layer. An s-MTJ is a highly energy-efficient switch that would dissipate only ~aJ of energy during switching. This paper discusses a novel variant of s-MTJ, namely skewed s-MTJ (ss-MTJ), where the MTJ switching can be controlled by two gate terminals. The current through an ss-MTJ is minimum when the potentials at the first and second gate terminals ( ${V}_{2}$ and ${V}_{3}$ , respectively) obey the relation ${V}_{3} = {V}_{2}+{V}_{F}$ . Here, ${V}_{F}$ is a fixed voltage (“offset voltage”). Current in an ss-MTJ increases steeply when ${V}_{2}$ and ${V}_{3}$ deviate from the above “match” condition. This unconventional ${I}$ – ${V}$ characteristic of an ss-MTJ is exploited to design a non-Boolean TCAM cell based on just one transistor, one trench capacitor, and one ss-MTJ. We also discuss search and write operations in the ss-MTJ-TCAM cell, and show that the cell requires very small voltages to operate because of the unique ${I}$ – ${V}$ characteristics of the ss-MTJ.

Skewed Straintronic Magnetotunneling-Junction-Based Ternary Content-Addressable Memory—Part II

Part I of this paper discussed the design of a four-terminal skewed straintronic magnetotunneling junction (ss-MTJ) switch, and its adaptation to a non-Boolean “one transistor, one trench capacitor, and one ss-MTJ” ternary content-addressable memory (TCAM) cell. This part of the paper discusses a TCAM array based on ss-MTJ-TCAM cells and the associated peripherals for search operation. We show that non-Boolean associative processing of the ss-MTJ-TCAM cells enhances energy-efficiency and performance of an ss-MTJ-based TCAM array. The energy-delay-product (EDP) of ss-MTJ-based TCAM is compared against CMOS-based TCAM for a 144 × 256 array. The minimum EDP in ss-MTJ-based TCAM is ~10.8× lower than the minimum EDP in CMOS-based TCAM. Additionally, the operational frequency at which the ss-MTJ-based design shows the minimum EDP is ~9.4× higher than the respective frequency in the CMOS-based design. We also compare ss-MTJ-based TCAM against other state-of-the-art MTJ-based TCAMs. The comparison shows that the ss-MTJ-based TCAM also outperforms MTJ-based TCAMs in cell density, search delay, and search energy. Finally, we discuss implications of process variability in ss-MTJ to TCAM implementation and identify critical design parameters in ss-MTJ-based TCAM to enhance its robustness and area/ energy-efficiency.

Design and Analysis of STTRAM-Based Ternary Content Addressable Memory Cell

Content Addressable Memory (CAM) is widely used in applications where searching a specific pattern of data is a major operation. Conventional CAMs suffer from area, power, and speed limitations. We propose Spin-Torque Transfer RAM--based Ternary CAM (TCAM) cells. The proposed NOR-type TCAM cell has a 62.5% (33%) reduction in number of transistor compared to conventional CMOS TCAMs (spintronic TCAMs). We analyzed the sense margin of the proposed TCAM with respect to 16-, 32-, 64-, 128-, and 256-bit word sizes in 22nm predictive technology. Simulations indicated a reliable sense margin of 50mV even at 0.7V supply voltage for 256-bits word. We also explored a selective threshold voltage modulation of transistors to improve the sense margin and tolerate process and voltage variations. The worst-case search latency and sense margin of 256-bit TCAM is found to be 263ps and 220mV, respectively, at 1V supply voltage. The average search power consumed is 13mW, and the search energy is 4.7fJ/bit search. The write time is 4ns, and the write energy is 0.69pJ/bit. We leverage the NOR-type TCAM design to realize a 9T-2 Magnetic Tunnel Junctions NAND-type TCAM cell that has 43.75% less number of transistors than the conventional CMOS TCAM cell. A NAND-type cell can support up to 64-bit words with a maximum sense margin of up to 33mV. We compare the performance metrics of NOR- and NAND-type TCAM cells with other TCAMs in the literature.