Content Addressable Memory Cell Research Articles

Energy efficient improved content addressable memory using quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is an emerging technology with high integration density, low power consumption, and high operating speed. This study introduces a QCA-based modified content addressable memory (CAM) cell employing a five-input minority gate. The functionality, temperature sensitivity, and heat distribution of this modified CAM cell are comprehensively analyzed using QCADesigner E and QCA Pro simulation tools. The results reveal significant advancements over existing designs, with a remarkable 8.33% reduction in area and a substantial 63.7% decrease in energy consumption. Additionally, this modified CAM cell exhibits a notable 5% enhancement in temperature tolerance. These findings emphasize the QCA-based modified CAM cell is more efficient and thermally robust.

Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine

Single clock cycle access feature of content-addressable memory (CAM) suits well for high-speed parallel content search operation in data-intensive hardware search engines. The diverse applications span from accelerating databases and routing networks to processing images, implementing machine learning, processing biomedical data, and compressing data. Nevertheless, the CAM macro consumes significant energy due to the high switching of most match-lines (MLs), which comprise CAM words, during parallel access. Segmented ML schemes reduced power yet the cell and ML delay, and the extra sequential cycles affect search-speed. A novel selective-charging and adaptive-discharging (SCAD) scheme in the form of dynamic ML architecture is proposed to reduce CAM power consumption at no extra cycle cost. Additionally, a full-swing CAM cell forms the basis of storage and comparison-evaluation to lessen ML delay. Based on 45-nm technology under 1-V supply, the proposed 64 × 32-bit and 256 × 144-bit SCAD-CAM arrays dissipate only 0.45–0.46 fJ/bit/search energy and achieve high-speed. Compared to CAMs based on low-power ML schemes, viz., low-swing precharge, division and control, and master–slave, and the conventional CAM as baseline design, the SCAD-CAM reduces 13.49%–89.35% energy-delay. The average-power reduction of 1.8×–2.4× establishes the SCAD-CAM as a promising memory architecture for emerging search-intensive applications involving large-scale data workloads.

Content-Addressable Memories and Transformable Logic Circuits Based on Ferroelectric Reconfigurable Transistors for In-Memory Computing.

As a promising alternative to the von Neumann architecture, in-memory computing holds the promise of delivering a high computing capacity while consuming low power. In this paper, we show that the ferroelectric reconfigurable transistor can serve as a versatile logic-in-memory unit that can perform logic operations and data storage concurrently. When functioning as memory, a ferroelectric reconfigurable transistor can implement content-addressable memory (CAM) with a 1-transistor-per-bit density. With the switchable polarity of the ferroelectric reconfigurable transistor, XOR/XNOR-like matching operation in CAM is realized in a single transistor, which can offer a significant improvement in area and energy efficiency compared to conventional CAMs. NAND- and NOR-arrays of CAMs are also demonstrated, which enable multibit matching in a single reading operation. In addition, the NOR array of CAM cells effectively measures the Hamming distance between the input query and the stored entries. When functioning as a logic element, a ferroelectric reconfigurable transistor can be switched between n- and p-type modes. Utilizing the switchable polarity of these ferroelectric Schottky barrier transistors, we demonstrate reconfigurable logic gates with NAND/NOR dual functions, whose input-output mapping can be transformed in real time without changing the layout, and the configuration is nonvolatile.

Ferroelectric Field Effect Transistors–Based Content‐Addressable Storage‐Class Memory: A Study on the Impact of Device Variation and High‐Temperature Compatibility

Hafnium oxide (HfO2)‐based ferroelectric field effect transistors (FeFETs) revolutionize the emerging nonvolatile memory area, especially with the potential to replace flash memories for several applications. In this article, the suitability of FeFET memories is investigated, especially FeFET‐based content addressable memory (CAM) cells, as storage‐class memory under junction temperature variations. FeFETs with silicon oxynitride interfacial layer are fabricated and characterized at various temperatures, varying from room temperature to 120 °C. Although the memory window, numbers of programmable states, and endurance deteriorate at high temperatures, FeFETs show excellent robustness in data retention, write latency, and read stability at all temperatures, especially for binary operation. Finally, system‐level simulations using a Simulation Program with Integrated Circuit Emphasis software using experimental data are conducted to gauge the robustness of the data‐search operation using the CAM array under different temperatures. Despite temperature‐variation‐induced changes in FeFET devices, it is observed that binary CAM cells perform robust and unerring search operations for storing and searching data at temperatures up to 120 °C.

Double-gated ferroelectric-gate field-effect-transistor for multi-bit content-addressable memories

In this study, we proposed a novel multi-bit content addressable memory (MCAM) cell based on one single double-gated ferroelectric-gate FET (DG-FeFET). Baseline DG-FeFET has been modeled, and the parameters are calibrated with experimental results by technology computer aided design (TCAD). Thanks to the pairing opposite ferroelectric states of the top/bottom gate (TG/BG) and pairing opposite searching voltages applied to TG and BG, MCAM functions with one DG-FeFET can be realized. The corresponding writing and searching operations are investigated in detail by the TCAD Sentaurus model. In addition, it is clarified that reducing the coupling effect of top and bottom channel by appropriately increasing the body thickness (Tbody) can boost the mismatch/match ratio. The proposed MCAM cell with one single DG-FeFET is promising for ultra-high-density computing systems.

Flash-based content addressable memory with L2 distance for memory-augmented neural network

Memory-augmented neural network (MANN) has received increasing attention as a promising approach to achieve lifelong on-device learning, of which implementation of the explicit memory is vital. Content addressable memory (CAM) has been designed to accelerate the explicit memory by harnessing the in-memory-computing capability. In this work, a CAM cell with quadratic code is proposed, and a 1Mb Flash-based multi-bit CAM chip capable of computing Euclidean (L2) distance is fabricated. Compared with ternary CAM, the latency and energy are significantly reduced by 5.3- and 46.6-fold, respectively, for the MANN on Omniglot dataset. Besides, the recognition accuracy has slight degradation (<1%) even after baking for 105 s at 200°C, demonstrating the robustness to environmental disturbance. Performance evaluation indicates a reduction of 471-fold in latency and 1267-fold in energy compared with GPU for search operation. The proposed robust and energy-efficient CAM provides a promising solution to implement lifelong on-device machine intelligence.

An Ultracompact Single‐Ferroelectric Field‐Effect Transistor Binary and Multibit Associative Search Engine

Content addressable memory (CAM) is widely used in associative search tasks due to its parallel pattern matching capability. As more complex and data‐intensive tasks emerge, it is becoming increasingly important to enhance CAM density for improved performance and better area efficiency. To reduce the area overheads, various nonvolatile memory (NVM) devices, such as ferroelectric field‐effect transistors (FeFETs), are used in CAM design. Herein, a novel ultracompact 1FeFET CAM design that enables parallel associative search and in‐memory hamming distance calculation is used, as well as a multibit CAM for exact search using the same CAM cell. The proposed CAM design leverages the 1FeFET1R structure, and compact device designs that integrate the series resistor current limiter into the intrinsic FeFET structure are demonstrated to turn the 1FeFET1R structure into an effective 1FeFET cell. A two‐step search operation of the proposed binary and multibit 1FeFET CAM array through both experiments and simulations is proposed, showing a sufficient sensing margin despite unoptimized FeFET device variation. In genome pattern matching applications, using the hyperdimensional computing paradigm, the design results in a 89.9× speedup and 66.5× improvement in energy efficiency over the state‐of‐the‐art alignment tools on GPU.

Ferroelectric Content-Addressable Memory Cells with IGZO Channel: Impact of Retention Degradation on the Multibit Operation.

Indium gallium zinc oxide (IGZO)-based ferroelectric thin-film transistors (FeTFTs) are being vigorously investigated for being deployed in computing-in-memory (CIM) applications. Content-addressable memories (CAMs) are the quintessential example of CIM, which conduct a parallel search over a queue or stack to obtain the matched entries for a given input data. CAM cells offer the ability for massively parallel searches in a single clock cycle throughout an entire CAM array for the input query, thereby enabling pattern matching and searching functionality. Therefore, CAM cells are used extensively for pattern matching or search operations in data-centric computing. This paper investigates the impact of retention degradation on IGZO-based FeTFT on the multibit operation in content CAM cell applications. We propose a scalable multibit 1FeTFT-1T-based CAM cell composed of only one FeTFT and one transistor, thus significantly improving the density and energy efficiency compared with conventional complementary metal-oxide-semiconductor (CMOS)-based CAM. We successfully demonstrate the operations of our proposed CAM with storage and search by exploiting the multilevel states of the experimentally calibrated IGZO-based FeTFT devices. We also investigate the impact of retention degradation on the search operation. Our proposed IGZO-based 3-bit and 2-bit CAM cell shows 104 s and 106 s retention, respectively. The single-bit CAM cell shows lifelong (10 years) retention.

Multi-Layered QCA Content-Addressable Memory Cell Using Low-Power Electronic Interaction for AI-Based Data Learning and Retrieval in Quantum Computing Environment.

In this study, we propose a quantum structure of an associative memory cell for effective data learning based on artificial intelligence. For effective learning of related data, content-based retrieval and storage rather than memory address is essential. A content-addressable memory (CAM), which is an efficient memory cell structure for this purpose, in a quantum computing environment, is designed based on quantum-dot cellular automata (QCA). A CAM cell is composed of a memory unit that stores information, a match unit that performs a search, and a structure, using an XOR gate or an XNOR gate in the match unit, that shows good performance. In this study, we designed an XNOR gate with a multilayer structure based on electron interactions and proposed a QCA-based CAM cell using it. The area and time efficiency are verified through a simulation using QCADesigner, and the quantum cost of the proposed XOR gate and CAM cell were reduced by at least 70% and 15%, respectively, when compared to the latest research. In addition, we physically proved the potential energy owing to the interaction between the electrons inside the QCA cell. We also proposed an additional CAM circuit targeting the reduction in energy dissipation that overcomes the best available designs. The simulation and calculation of power dissipation are performed by QCADesigner-E and it is confirmed that more than 27% is reduced.

An All-Optical Address Look-Up Table Using Optical CAM and Optical RAM Banks

We report for the first time, to the best of our knowledge, the experimental demonstration of a complete all-optical 2-bit Address Look-Up (AL) table that performs address matching and forwarding and operates at 10Gb/s. The circuit incorporates an optical Content Addressable Memory (CAM) and an optical Random Access Memory (RAM) table that are interconnected via an optical Encoding/Decoding circuit. The AL table has been experimentally validated for different sets of CAM and RAM word contents as well as for different CAM and RAM row interconnect settings at 10Gb/s, revealing a power penalty of around 9 dB at a bit-error-rate (BER) of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> . Furthermore, we demonstrate experimental results of a fully integrated InP-based optical CAM cell, which includes an integrated XGM Flip-Flop (FF) memory cell and a Mach-Zehnder Interferometer (MZI) XNOR Access Gate (AG) and supports content addressing operation at 5 Gb/s. This fully-integrated optical CAM cell indicates a possible integration roadmap for the AL constituent building blocks towards the deployment of integrated optical ALs that can be utilized in optical routing or, more general, in optical content matching and forwarding operations.

SMS-CAM: Shared matchline scheme for content addressable memory

Content addressable memory (CAM) is a hardware search engine (HSE) used for accelerating lookup functions in tagged cache, translation lookaside buffers (TLBs) and network routers. Despite its speedy search feature, augmentation of compare-evaluate blocks to storage units costs additional area. Activation of cells and matchlines (MLs) during search operations is responsible for huge dynamic-power dissipation. This paper proposes a shared ML scheme (SMS) based on a two-step evaluation CAM cell, in order to reduce ML transitions per word besides improving density in the comparison units. A 64 × 32-bit proposed SMS-CAM, using 45-nm CMOS technology, dissipates 1.06 fJ/bit/search and achieves 100.77-ps search time. At the cost of 6.55% sacrificial delay over a conventional CAM, the proposed CAM reduces 12.38% – 30.48% energy over a self-power off gating, the conventional and an early terminate ML precharge designs. Low energy-delay results better trade-off budget besides decreasing macro area in the SMS-CAM, which could be useful in search applications of network devices.

A FeFET-Based Hybrid Memory Accessible by Content and by Address

Emerging nonvolatile memory technologies are attracting interest from the system design level to implement alternatives to conventional von-Neumann computing architectures. In particular, the hafnium oxide-based ferroelectric (FE) memory technology is fully CMOS-compatible and has already been used for logic-in-memory architectures or compact ternary content addressable memory (TCAM) cells. These enable the tight combination of different functionalities in the same circuit to reduce implementation area and energy consumption. In this article, we propose a new hybrid memory circuit that combines TCAM and normal memory capability: the Ternary Content addressable and MEMory (TC-MEM). A 1-bit TC-MEM circuit is proposed and discussed in detail, both as a concept and through its implementation in a 28-nm ferroelectric field-effect transistor (FeFET) technology. Measurement results demonstrate the circuit functionality. We also discuss how to scale it to multibit circuits, as well as its use both as a TCAM and as a normal memory allowing the implementation of reversible functions using one memory table instead of two memory tables, and in-memory-computing concepts.

Designing a Content-Addressable Memory Cell Using Multiplexer in Quantum-Dot Cellular Automata

Low power consumption, high density, regularity, and high speed are readily applicable to QCA. Therefore, memory is well suited for implementation using this technology. Because Content Addressable Memory (CAM) is a special type of memory structure used in very fast search applications, QCA can be used to design this memory at the nanoscale. In this paper, we introduce a new structure for the CAM cell. For this purpose, all the components needed to implement this memory cell are designed separately. In order to provide a structure with fewer gates, the operational equations of the components are considered in a way that they can be implemented by a unique multiplexer gate. For this purpose, a new multiplexer is used, which operates based on the Columbic interaction of cells. QCADesigner is used to simulate the proposed structures and verify their operation. The proposed structure has a 28% improvement in the number of cells and a 27% improvement in the occupied area.

A skyrmion content-addressable cell for skyrmion magnetic memories

Content-addressable memories (CAMs) allow searching a pattern, processing in parallel all the data stored. Beyond-CMOS technologies can provide new opportunities to improve CAM memories implementations both at the device and architectural level. In this article, we propose a ternary content-addressable memory cell based on skyrmion technology. The proposed memory cell is based on skyrmion racetrack memory. The cell is able to signal if the bit contained in the cell in form of skyrmion corresponds to an electrical input, the target of the search operation. The proposed design, verified by means of micromagnetic simulations, has an area of 0.054 μm2 and can perform a search operation in 3.3 ns with an energy of 10.5 fJ. The operation performed is non-destructive and does not require conversion between the magnetic and the electronic domains. For this reason, the designed cell has the potential to be used as a basic block for non-volatile CAM memories. Here, we propose also a layout structure to implement a CAM memory employing the proposed cell. This structure allows to achieve memory density comparable to traditional racetrack memories and execute at the same time CAM operations.

Nonvolatile Logic and Ternary Content-Addressable Memory Based on Complementary Black Phosphorus and Rhenium Disulfide Transistors.

Hardware realization of in-memory computing for efficient data-intensive computation is regarded as a promising paradigm beyond the Moore era. However, to realize such functions, the device structure using traditional Si complementary metal-oxide-semiconductor (CMOS) technology is complex with a large footprint. 2D material-based heterostructures have a unique advantage to build versatile logic functions based on novel heterostructures with simplified device footprint and low power. Here, by adopting the charge-trapping mechanism between a black phosphorus (BP) channel and a phosphorus oxide (POx ) layer, a nonvolatile CMOS logic circuit based on 2D BP and rhenium disulfide (ReS2 ) with a high voltage gain of ≈275 is realized with a persistent hysteresis window. A Schmidt-like flip-flop using only two transistors is also demonstrated, with far fewer transistor numbers than the conventional silicon counterpart, which usually requires six transistors. Furthermore, four-transistor (4T) nonvolatile ternary content-addressable memory (nvTCAM) cells are demonstrated with far fewer transistors for parallel data search. The nvTCAM cells exhibit high resistance ratios (Rratio ) up to ≈103 between match and mismatch states with zero standby power thanks to the nonvolatility of the BP transistors. This back-end-of-line compatible nvTCAM shows advantages over other structures with reduced complexity and thermal budget.

A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS

This article presents a communication-aware processing-in-memory deep neural network accelerator, which implements an in-memory entry-counting scheme for low bit-width quantized multiplication-and-accumulations (MACs). To maintain good accuracy on ImageNet, the proposed design adopts a full-stack co-design methodology, from algorithms, circuits to architectures. In the algorithm level, an entry-counting based MAC is proposed to fit the learned step-sized quantization scheme, and exploit the sparsity of both activations and weights intrinsically. In the circuit level, content addressable memory cells and multiplexed arrays are developed in the processing-in-memory macro. In the architecture level, the proposed design is compatible with different stationary dataflow mappings, further reducing the memory access. An in-memory entry-counting silicon prototype and its entire peripheral circuits are fabricated in 65nm LP CMOS technology with an active area of $0.76\times 0.66$ mm2. The 7.36-Kb processing-in-memory macro with 128 search entries can reduce the multiplication number by $12.8\times $ . The peak throughput is 3.58 GOPS, achieved at a clock rate of 143MHz and a power supply of 1.23V. The peak energy efficiency of the processing-in-memory macro is 11.6 TOPS/W, achieved at a clock rate of 40MHz and a power supply of 1.01V. Note that the physical design of the entry-counting memory is completed in a standard digital placement and routing flow by augmenting the library with two dedicated memory cells. A 3-bit quantized ResNet-18 on the ImageNet dataset is performed, where the top-1 accuracy is 64.4%.

FeCAM: A Universal Compact Digital and Analog Content Addressable Memory Using Ferroelectric

Ferroelectric field effect transistors (FeFETs) are being actively investigated with the potential for in-memory computing (IMC) over other nonvolatile memories (NVMs). Content addressable memories (CAMs) are a form of IMC that performs parallel searches for matched entries over a memory array for a given input query. CAMs are widely used for data-centric applications that involve pattern matching and search functionality. To accommodate the ever expanding data, it is attractive to resort to analog CAM for memory density improvement. However, the digital CAM design nowadays based on standard CMOS or emerging NVMs (e.g., resistive storage devices) is already challenging due to area, power, and cost penalties. Thus, it can be extremely expensive to achieve analog CAM with those technologies due to added cell components. As such, we propose, for the first time, a universal compact FeFET-based CAM design, FeCAM, with search and storage functionality enabled in digital and analog domains simultaneously. By exploiting the multilevel-cell (MLC) states of FeFET, FeCAM can store and search inputs in either digital or analog domain. We perform a device-circuit codesign of the proposed FeCAM and validate its functionality and performance using an experimentally calibrated FeFET model. Circuit level simulation results demonstrate that FeCAM can either store continuous matching ranges or encode 3-bit data in a single CAM cell. When compared with the existing digital CMOS-based CAM approaches, FeCAM is found to improve both memory density by 22.4× and energy saving by 8.6×/3.2× for analog/digital modes, respectively.In the CAM-related application, our evaluations show that FeCAM can achieve 60.5×/23.1× saving in area/search energy compared with conventional CMOS-based CAMs.

Experimental Demonstration of a Ferroelectric HfO2-Based Content Addressable Memory Cell

In this work, we present an experimental demonstration of a content addressable memory (CAM) cell based on ferroelectric HfO2 field effect transistors (FeFETs). Our proposed ferroelectric CAM (FeCAM) utilizes a CMOS-compatible ferroelectric material, hafnium zirconium oxide (HZO), as the gate dielectric. We discuss operation of the FeCAM cell and propose a suitable architecture to realize in-memory computation as well as single clock cycle content-driven search. In addition, the HZO FeFET is analyzed for its intrinsic memory characteristic, and design considerations are identified for improving device and therefore projected system-level performance. Our results indicate that FeCAM is well-suited to accommodate demanding modern computational needs by sealing the gaps between conventional memory, logic, and continued device scaling.

A Dual-Port 8-T CAM-Based Network Intrusion Detection Engine for IoT

This letter presents an energy- and memory-efficient pattern-matching engine for a network intrusion detection system (NIDS) in the Internet of Things. Tightly coupled architecture and circuit co-designs are proposed to fully exploit the statistical behaviors of NIDS pattern matching. The proposed engine performs pattern matching in three phases, where the phase-1 prefix matching employs reconfigurable pipelined automata processing to minimize memory footprint without loss of throughput and efficiency. The processing elements utilize 8-T content-addressable memory (CAM) cells for dual-port search by leveraging proposed fixed-1s encoding. A 65-nm prototype demonstrates best-in-class 1.54-fJ energy per search per pattern byte and 0.9-byte memory usage per pattern byte.

Design and Performance Analysis of Low Power High Speed CNTFET Binary Content Addressable Memory Cell for Next Generation Communication Networks

In this paper, Carbon Nanotube Field Effect Transistor (CNTFET) based Binary Content Addressable Memory (BCAM) cells are proposed. The adiabatic logic is integrated with the proposed BCAM cells to improve performance. The performance of proposed BCAM cells is presented for various CNTFET parameters such as number of tubes, chirality vector, pitch value, dielectric constant and dielectric materials. It also explores the optimum set of CNTFET parameters for low power and high speed characteristics of the proposed BCAM cells. Simulation results show an improvement in the average power and delay of proposed BCAM cells. The average power of the proposed BCAM cells is in the order of nano watts while the CMOS based BCAM cells is in the order of micro watts. The delay of the proposed BCAM cells is improved by 56.4 %. All simulations are conducted for both CMOS and CNTFET based BCAM cells in HSPICE at 32 nm technology.