Content Addressable Memory Research Articles

Multifunctional Reconfigurable Operations in an Ultra-Scaled Ferroelectric Negative Transconductance Transistor.

The integration of functional materials into electronic devices has become a key approach to extending Moore's law by increasing the functional density of electronic circuits. Here, we present a device technology based on ultrascaled ferroelectric, antiambipolar transistors (ferro-AAT) with robust negative transconductance, enabling a wide range of reconfigurable functionalities with applications in both the digital and analog domains. The device relies on the integration of a hafnia-based ferroelectric gate stack on a vertical nanowire tunnel field-effect transistor. Through intentional gate/source overlap and tunnel-junction engineering, we demonstrate enhanced antiambipolarity with a high negative transconductance that is reconfigurable using the nonvolatile remanent polarization of the ferroelectric. Experimental validation highlights the versatility of this ferro-AAT in two implementation scenarios: content addressable memory (CAM) for high-density data search and reconfigurable signal processing in analog circuits. As a single-transistor cell for CAMs, the ferro-AAT shows subpicojoule operation for one search with a compact footprint of ∼0.01 μm2. For single-transistor-based signal modulation, multistate reconfigurations and high power conversion (>95%) are achieved in the ferro-AAT, resulting in a significant reduction in the complexity of analog circuit design. Our results reveal that the distinctive device properties allow ferro-AATs to operate beyond conventional transistors with multiple reconfigurable functionalities, ultrascaled footprint, and low power consumption.

In-memory search with learning to hash based on resistive memory for recommendation acceleration

Similarity search is essential in current artificial intelligence applications and widely utilized in various fields, such as recommender systems. However, the exponential growth of data poses significant challenges in search time and energy consumption on traditional digital hardware. Here, we propose a software-hardware co-optimization to address these challenges. On the software side, we employ a learning-to-hash method for vector encoding and achieve an approximate nearest neighbor search by calculating Hamming distance, thereby reducing computational complexity. On the hardware side, we leverage the resistance random-access memory crossbar array to implement the hash encoding process and the content-addressable memory with an in-memory computing paradigm to lower the energy consumption during searches. Simulations on the MovieLens dataset demonstrate that the implementation achieves comparable accuracy to software and reduces energy consumption by 30-fold compared to traditional digital systems. These results provide insight into the development of energy-efficient in-memory search systems for edge computing.

0.765-FJ/Bit/Search Content Addressable Memory Using Search Line Pre-Charge-Free (SLPF) Scheme

Content Addressable Memories (CAMs) are high-speed hardware lookup tables that are crucial in routing, packet classification, search, and other fast look-up applications. Despite having the advantage of high speed, they have limitations due to their power hungriness. This paper addresses the limitations of existing CAMs with two novel modifications in the proposed Search Line Pre-Charge-Free Low-Power-Content Addressable Memory (SLPFCAM) structure. The first novelty is their gated evaluation matching circuit and the second is a match line pre-charge controller. The proposed design reduces the energy consumption and improves the speed of the CAM by eliminating the SLprecharge phase in the CAM operation. The pre-charge controller prevents the attempt of match line pre-charge when it is not required. The design has been implemented using Cadence Virtuoso in a 90-nm CMOS technology with 1-V supply, and the post-layout simulation results show that the SLPFCAM makes significant improvements with a minimum of 83% less power consumption, a 91% less search delay, and the average energy consumption being 0.765 fJ/bit/search.

Semantic memory-based dynamic neural network using memristive ternary CIM and CAM for 2D and 3D vision.

The brain is dynamic, associative, and efficient. It reconfigures by associating the inputs with past experiences, with fused memory and processing. In contrast, AI models are static, unable to associate inputs with past experiences, and run on digital computers with physically separated memory and processing. We propose a hardware-software co-design, a semantic memory-based dynamic neural network using a memristor. The network associates incoming data with the past experience stored as semantic vectors. The network and the semantic memory are physically implemented on noise-robust ternary memristor-based computing-in-memory (CIM) and content-addressable memory (CAM) circuits, respectively. We validate our co-designs, using a 40-nm memristor macro, on ResNet and PointNet++ for classifying images and three-dimensional points from the MNIST and ModelNet datasets, which achieves not only accuracy on par with software but also a 48.1 and 15.9% reduction in computational budget. Moreover, it delivers a 77.6 and 93.3% reduction in energy consumption.

Ternary Content-Addressable Memory Based on a Single Two-Dimensional Transistor for Memory-Augmented Learning.

Ternary content-addressable memory (TCAM) is promising for data-intensive artificial intelligence applications due to its large-scale parallel in-memory computing capabilities. However, it is still challenging to build a reliable TCAM cell from a single circuit component. Here, we demonstrate a single transistor TCAM based on a floating-gate two-dimensional (2D) ambipolar MoTe2 field-effect transistor with graphene contacts. Our bottom graphene contacts scheme enables gate modulation of the contact Schottky barrier heights, facilitating carrier injection for both electrons and holes. The 2D nature of our channel and contact materials provides device scaling potentials beyond silicon. By integration with a floating-gate stack, a highly reliable nonvolatile memory is achieved. Our TCAM cell exhibits a resistance ratio larger than 1000 and symmetrical complementary states, allowing the implementation of large-scale TCAM arrays. Finally, we show through circuit simulations that in-memory Hamming distance computation is readily achievable based on our TCAM with array sizes up to 128 cells.

Do Not Let the Beginning Trap you! On Inhibition, Associative Creative Chains, and Hopfield Neural Networks

ABSTRACTCreative thinking stems from the cognitive process that fosters the creation of new ideas and problem‐solving solutions. Artificial intelligence systems and neural network models can reduce the intricacy of understanding creative cognition. For instance, the generation of ideas could be symbolized as patterns of binary code in which clusters of neurons synchronize their firing and store information inside a neural network, forming connections based on correlation. The Hopfield neural network (HNN) is a simple model known for its biological plausibility in storing and retrieving neuron patterns. We implemented certain modifications to HNN as a step toward the larger framework of creative thinking‐based association. These modifications included introducing pattern weights control, which provides a robust representation for content addressable memory and conceptual links in stored data. We identified two mechanisms controlling the transition from analytical to associative‐based thinking. The first mechanism refers to the activation threshold of neurons, which acts as an on/off switch for the network. The second was the inhibition of stored concepts, similar to an on/off switch that guides the network to search for associative links and when to stop. Our findings suggest that neurons step back from the contextual focus and find alternatives when analytical thinking is insufficient. These alternatives are linked to seemingly unrelated ideas, using inhibition as an analogy to the hyperparameters. Using hyperparameters to inhibit the stored patterns, we could control the creation of associative links.

Energy efficient improved content addressable memory using quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is an emerging technology with high integration density, low power consumption, and high operating speed. This study introduces a QCA-based modified content addressable memory (CAM) cell employing a five-input minority gate. The functionality, temperature sensitivity, and heat distribution of this modified CAM cell are comprehensively analyzed using QCADesigner E and QCA Pro simulation tools. The results reveal significant advancements over existing designs, with a remarkable 8.33% reduction in area and a substantial 63.7% decrease in energy consumption. Additionally, this modified CAM cell exhibits a notable 5% enhancement in temperature tolerance. These findings emphasize the QCA-based modified CAM cell is more efficient and thermally robust.

Enhanced CPU Design for SDN Controller.

Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power-Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs.

A Novel Ferroelectric FET Based Universal Content Addressable Memory With Reconfigurability for Area- and Energy-Efficient In-Memory-Searching System

A Novel Ferroelectric FET Based Universal Content Addressable Memory With Reconfigurability for Area- and Energy-Efficient In-Memory-Searching System

On convergence properties of the brain-state-in-a-convex-domain

Convergence in the presence of multiple equilibrium points is one of the most fundamental dynamical properties of a neural network (NN). Goal of the paper is to investigate convergence for the classic Brain-State-in-a-Box (BSB) NN model and some of its relevant generalizations named Brain-State-in-a-Convex-Body (BSCB). In particular, BSCB is a class of discrete-time NNs obtained by projecting a linear system onto a convex body of Rn. The main result in the paper is that the BSCB is convergent when the matrix of the linear system is symmetric and positive semidefinite or, otherwise, it is symmetric and the step size does not exceed a given bound depending only on the minimum eigenvalue of the matrix. This result generalizes previous results in the literature for BSB and BSCB and it gives a solid foundation for the use of BSCB as a content addressable memory (CAM). The result is proved via Lyapunov method and LaSalle’s Invariance Principle for discrete-time systems and by using some fundamental inequalities enjoyed by the projection operator onto convex sets as Bourbaki–Cheney–Goldstein inequality.

Bio-inspired computational memory model of the Hippocampus: An approach to a neuromorphic spike-based Content-Addressable Memory

The brain has computational capabilities that surpass those of modern systems, being able to solve complex problems efficiently in a simple way. Neuromorphic engineering aims to mimic biology in order to develop new systems capable of incorporating such capabilities. Bio-inspired learning systems continue to be a challenge that must be solved, and much work needs to be done in this regard. Among all brain regions, the hippocampus stands out as an autoassociative short-term memory with the capacity to learn and recall memories from any fragment of them. These characteristics make the hippocampus an ideal candidate for developing bio-inspired learning systems that, in addition, resemble content-addressable memories. Therefore, in this work we propose a bio-inspired spiking content-addressable memory model based on the CA3 region of the hippocampus with the ability to learn, forget and recall memories, both orthogonal and non-orthogonal, from any fragment of them. The model was implemented on the SpiNNaker hardware platform using Spiking Neural Networks. A set of experiments based on functional, stress and applicability tests were performed to demonstrate its correct functioning. This work presents the first hardware implementation of a fully-functional bio-inspired spiking hippocampal content-addressable memory model, paving the way for the development of future more complex neuromorphic systems.

Deep random forest with ferroelectric analog content addressable memory.

Deep random forest (DRF), which combines deep learning and random forest, exhibits comparable accuracy, interpretability, low memory and computational overhead to deep neural networks (DNNs) in edge intelligence tasks. However, efficient DRF accelerator is lagging behind its DNN counterparts. The key to DRF acceleration lies in realizing the branch-split operation at decision nodes. In this work, we propose implementing DRF through associative searches realized with ferroelectric analog content addressable memory (ACAM). Utilizing only two ferroelectric field effect transistors (FeFETs), the ultra-compact ACAM cell performs energy-efficient branch-split operations by storing decision boundaries as analog polarization states in FeFETs. The DRF accelerator architecture and its model mapping to ACAM arrays are presented. The functionality, characteristics, and scalability of the FeFET ACAM DRF and its robustness against FeFET device non-idealities are validated in experiments and simulations. Evaluations show that the FeFET ACAM DRF accelerator achieves ∼106×/10× and ∼106×/2.5× improvements in energy and latency, respectively, compared to other DRF hardware implementations on state-of-the-art CPU/ReRAM.

DSCAM: Latency-Guaranteed and High-Capacity Content-Addressable Memory on FPGAs

DSCAM: Latency-Guaranteed and High-Capacity Content-Addressable Memory on FPGAs

Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine

Single clock cycle access feature of content-addressable memory (CAM) suits well for high-speed parallel content search operation in data-intensive hardware search engines. The diverse applications span from accelerating databases and routing networks to processing images, implementing machine learning, processing biomedical data, and compressing data. Nevertheless, the CAM macro consumes significant energy due to the high switching of most match-lines (MLs), which comprise CAM words, during parallel access. Segmented ML schemes reduced power yet the cell and ML delay, and the extra sequential cycles affect search-speed. A novel selective-charging and adaptive-discharging (SCAD) scheme in the form of dynamic ML architecture is proposed to reduce CAM power consumption at no extra cycle cost. Additionally, a full-swing CAM cell forms the basis of storage and comparison-evaluation to lessen ML delay. Based on 45-nm technology under 1-V supply, the proposed 64 × 32-bit and 256 × 144-bit SCAD-CAM arrays dissipate only 0.45–0.46 fJ/bit/search energy and achieve high-speed. Compared to CAMs based on low-power ML schemes, viz., low-swing precharge, division and control, and master–slave, and the conventional CAM as baseline design, the SCAD-CAM reduces 13.49%–89.35% energy-delay. The average-power reduction of 1.8×–2.4× establishes the SCAD-CAM as a promising memory architecture for emerging search-intensive applications involving large-scale data workloads.

Low power content addressable memory designing and implementation using voltage swing self adjustable match line technique

One of the essential components of computer systems is memory. A primary hindrance in this regard is the memory speed. Content Addressable Memory (CAM) speeds up transformations and table lookups in network routers and data processing systems for hardware search engines. Parallel seeks using the CAM (Content Addressable Memory) model are often used to enhance memory performance. This paper uses the voltage swing self-adjustable match line (VSSA-ML) technique to describe low-power content addressable memory design and implementation. This project decreases Match Line (ML) power loss by reducing load capacitance and ML voltage swing. A simple ML voltage detector is proposed instead of the complex, fully different detector that allows ML voltage swings near zero. This paper presents 6 T 8×8 CAM arrays using VSSA-ML Technique using Tanner tools 45-nm technology. On the other hand, this design enhances robustness in processing variations by self-adjusting voltage swings. Implementation analysis states that the described mode 6 T 8×8 CAM design utilized fewer MOSFETs than the 8 T 8×8 CAM array.

CMOS-Integrated Ternary Content Addressable Memory using Nanocavity CBRAMs for High Sensing Margin.

The development of data-intensive computing methods imposes a significant load on the hardware, requiring progress toward a memory-centric paradigm. Within this context, ternary content-addressable memory (TCAM) can become an essential platform for high-speed in-memory matching applications of large data vectors. Compared to traditional static random-access memory (SRAM) designs, TCAM technology using non-volatile resistive memories (RRAMs) in two-transistor-two-resistor (2T2R) configurations presents a cost-efficient alternative. However, the limited sensing margin between the match and mismatch states in RRAM structures hinders the potential of using memory-based TCAMs for large-scale architectures. Therefore, this study proposes a practical device engineering method to improve the switching response of conductive-bridge memories (CBRAMs) integrated with existing complementary metal-oxide-semiconductor (CMOS) transistor technology. Importantly, this work demonstrates a significant improvement in memory window reaching 1.87 × 107 by incorporating nanocavity arrays and modifying electrode geometry. Consequently, TCAM cells using nanocavity-enhanced CBRAM devices can exhibit a considerable increase in resistance ratio up to 6.17 × 105, thereby closely approximating the sensing metrics observed in SRAM-based TCAMs. The improved sensing capability facilitates the parallel querying of extensive data sets. TCAM array simulations using experimentally verified device models indicate a substantial sensing margin of 65× enabling a parallel search of 2048 bits.

Almost automorphic behaviours of nonlocal stochastic fuzzy Cohen–Grossberg lattice neural networks

Discrete-time Cohen–Grossberg neural networks (CGNNs) play important role in feedback neural networks. The existing literatures of CGNNs only regarded integral order discrete-time models without other variables. This paper builds the lattice model for nonlocal stochastic fuzzy CGNNs with reaction diffusions by employing the finite difference and Mittag–Leffler time Euler difference techniques. Further, the existence of a unique bounded almost automorphic sequence solution in distribution and global exponential convergence in the mean-square sense to the achieved difference model are investigated. At last, by using the tool of Matlab and time Euler difference for the Brownian motions, an illustrative example with simulations is used to show the feasible of the works of the current paper. We think that this work can contribute to achieve some effective real tasks, e.g. content-addressable memory, auto-association, dynamic reconstruction of a chaotic process, etc.

Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices.

Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have the advantage of being much more compatible with existing silicon-based complementary metal oxide semiconductor (CMOS) processes compared to devices using new materials such as ferroelectrics for LiM computing. Utilizing the 32 nm technology node, the leading-edge node where the planar metal oxide semiconductor field effect transistor structure is applied, FGFET devices were analyzed in TCAD, and an environment for analyzing circuits in HSPICE was established. To seamlessly connect FGFET-based devices and circuit analyses, compact models of FGFET-SDB and -CSBs were developed and applied to the design of ternary content-addressable memory (TCAM) and full adder (FA) circuits for LiM. In addition, depression and potential for application of FGFET devices to neural networks were analyzed. The temperature-dependent characteristics of the TCAM and FA circuits with FGFETs were analyzed as an indicator of energy and delay time, and the appropriate number of CSBs should be applied.

Design a self-controlled high-performance evaluation of content addressable memories using 45 nm technology

A special type of random access memory (RAM) array called as content addressable memory (CAM), in which stored data is compared with the search data which can be returning the address. In the applications of highspeed searching, the CAMs are used. NOR type matchline CAMs are helpful for applications requiring faster search speeds. Because the NOR type match line (ML) CAM consumes a lot of power, therefore many published designs have attempted to reduce power consumption. The design self-controlled high-performance content addressable memories (SC-CAM) using 45-nm technology is presented in this paper. The 6T 4×4 CAM arrays in this paper uses SC logic and Tanner tools 45-nm technology. When compared to the conventional CAM, described SC-CAM architecture reduces the number of voltages sources. Described 6T 4×4 SC-CAM design needs less number of MOSFETs than existed 8T 4×4 CAM array and thus reduces the area with high speed.

A 0.75V 10nm FinField-Effect Transistor Based Hybrid Self Controlled PreCharge Free Content Addressable Memory for Low Standby Power Applications

ABSTRACT The switching speed and driving capability have been enhanced by scaling the transistor size to nanoscale. The limitations in using MOSFET are that the short channel effects such as leakage current, subthreshold voltage, etc. thereby the Complementary Metal Oxide Semiconductor (CMOS) scaling is challenging now.This leads to the emergence of multi-gate devices, such as Fin Field Effect Transistor (FinFET) and Double Gate FinFET (DG-FinFET), which reduces the short channel effect. Now, a days memory plays a vital role in Integrated Circuits (IC), so the size of it must be scaled down to reduce the overall leakage andinstead of CMOS an advanced MOSFET such as FinFET can be used to avoid SCE. The area of the memory Static Random Access Memory (SRAM) is reduced by eliminating the two-load transistor. The novel 4T SRAM is designed at 10 nm 0.75 v FinFET Technology and compared with 14 nm Technology that is inbuilt into content addressable memory (CAM) to reduce the power consumption of CAM. The results show that the proposed design improves on a voltage basis and the complexity of the circuit is reduced by about 23% in terms of transistor count compared with the other conventional techniques. The 10 nm FinFET Hybrid Self Controlled - PreCharge Free (HSCPF) CAM design is best-suitable for low-power applications.