Construction Of Binary Decision Diagrams Research Articles

Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams

Multiplier circuit covers a more extensive area of embedded system application in digital signal processing, cryptography, and multimedia. Nonstandard implementations and custom optimization are being done to reduce the size of multipliers. The circuit became prone to a buggy, and hence the demand for verification increased. Formal verification methods, such as satisfiability (SAT), symbolic computer algebra (SCA), and binary decision diagrams (BDDs) have made massive progress over the last few decades. However, these methods are insufficient to verify the optimized multipliers. SAT-based equivalence checking is computationally expensive. SCA-based backward rewriting is limited to algebraic-friendly multipliers. The complexity of BDDs is exponential with the input size. Although, by allowing an additional variable method, the size of the BDD is limited to 4th degree polynomial of the number of the inputs, this method is not explored to verify optimized multipliers. This article focus on verifying integer multipliers with diverse architectures. We propose an algorithm for the direct construction of BDDs without traversing circuits and generate BDDs up to 1024 bits. We utilize the additional variable method and constructing BDDs using high-to-low variable ordering. We reduce the complexity of BDD size to a 3rd degree polynomial. We generate BDDs and verify the multipliers with various architectures up to 64 bits. We propose a method to verify optimized multipliers by checking equivalence and verifying up to 32-bits optimized multipliers. We do the error tolerance analysis of our approach by inserting bugs in a circuit at various locations.

Efficient construction of binary decision diagrams for network reliability with imperfect vertices

This paper discusses evaluation of the network reliability with imperfect vertices, which computes the probability that a subset of nodes is communicable under possible failures of links and nodes. Although the network reliability is efficiently computed utilizing a binary decision diagram (BDD) if assuming link failures only, it can be 10 times slower if considering node failures as well. This is because existing algorithms are designed to repeatedly update a BDD for every node failure in a step-by-step manner. This research proposes an algorithm that creates the final BDD without the redundant repetitions, which greatly improves the computation efficiency. Moreover, this paper presents a better variable order of BDDs among variables corresponding to links and nodes. Under the variable order, the proposed algorithm is compared with existing ones by numerical experiments using various benchmark networks including real communication networks. The results show that the proposed algorithm runs 198.2 times faster than the existing ones for the 10-by-10 grid graph, 1074.6 times faster for the complete graph with 12 vertices, and 65.6 times faster for some well-known benchmark network. For some network instances, the proposed variable order reduces the number of BDD nodes by 15–38% compared with the existing order. This paper reveals that considering imperfect vertices does not impose significant performance overheads.

Dynamic labelling of BDD and ZBDD for efficient non-coherent fault tree analysis

Binary Decision Diagram (BDD) based fault tree analysis algorithms are among the most efficient ones. They allow performing exact probabilistic analyses, as well as to derive a Zero-suppressed BDD (ZBDD) to efficiently encode Significant Prime Implicants (PI) or Minimal Cut Sets (MCS).The present paper describes a dynamic labelling method for BDD/ZBDD to analyse non-coherent fault trees. An L-BDD is a BDD in which the information about the variable type is associated to each node. This information is useful to select, for each node, the corresponding algorithms for performing the probabilistic analysis and for determining PI or MCS.When the computational resources are not sufficient to complete the BDD construction, it is convenient to construct the ZBDD directly from the fault tree. The second part of this paper describes rules for constructing a Truncated Labelled ZBDD (TL-ZBDD) of non-coherent fault trees.Results of the analysis of some non-coherent fault trees by means of L-BDD and TL-ZBDD are provided.

Sequence binary decision diagram: Minimization, relationship to acyclic automata, and complexities of Boolean set operations

The manipulation of large sequence data is one of the most important problems in string processing. In this paper, we discuss a new data structure for storing and manipulating sets of strings, called Sequence Binary Decision Diagrams (sequence BDDs), which has recently been introduced by Loekito et al. (2010) as a descendant of both acyclic DFAs (ADFAs) and binary decision diagrams (BDDs). Sequence BDDs can compactly represent sets of sequences similarly to minimal ADFAs, and allow efficient set operations inherited from BDDs. We study fundamental properties of sequence BDDs, such as the characterization of minimal sequence BDDs by reduced sequence BDDs, non-trivial relationships between sizes of minimal sequence BDDs and minimal ADFAs, the complexities of minimization, Boolean set operations, and sequence BDD construction. We also show experimental results for real and artificial data sets.

Neural Network Selection Mechanism for BDD Construction

AbstractThe binary decision diagram (BDD) methodology is the latest approach used to improve the analysis of the fault ree diagram, which gives a qualitative and quantitative assessment of specified risks. To convert the fault tree into the necessary BDD format requires the basic events of the tree to be placed in an ordering. The ordering of the basic events is critical to the resulting size of the BDD, and ultimately affects the performance and benefits of this technique. A number of heuristic approaches have been developed to produce an optimal ordering permutation for a specific tree, however they do not always yield a minimal BDD structure for all trees. Latest research considers a neural network approach used to select the ‘best’ ordering permutation from a given set of alternatives. To use this approach characteristics are taken from the fault tree as guidelines to selection of the appropriate ordering permutation. This paper looks at a new method of using the Jacobian matrix to choose the most desired characteristics from the fault tree, which will aid the neural network selection procedure. Copyright © 2004 John Wiley & Sons, Ltd.

History-based dynamic BDD minimization

Binary decision diagrams (BDDs) are the state-of-the-art data structure in VLSI CAD. Since their size largely depends on the chosen variable ordering, dynamic variable reordering methods, like sifting, often have to be applied during the construction. Usually sifting is called each time a given node limit is reached and it is therefore called frequently during the creation of large BDDs. Often most of the runtime is spent for sifting while the BDD is built. In this paper we propose an approach to reduce runtime (and space requirement) when constructing BDDs for a given circuit or when computing the set of reachable states in sequential verification. Dependent on the history of the construction process different types of sifting are called. For the BDD construction of combinational circuits we present two methods, one is based on statistics of the unique table, the other one is based on the size reduction of the previous run of sifting. For sequential verification, we propose to select the type of sifting according to the number of iterations processed. Experimental results clearly demonstrate the efficiency of the approach.

Parallel breadth-first BDD construction

With the increasing complexity of protocol and circuit designs, formal verification has become an important research area and binary decision diagrams (BDDs) have been shown to be a powerful tool in formal verification. This paper presents a parallel algorithm for BDD construction targeted at shared memory multiprocessors and distributed shared memory systems. This algorithm focuses on improving memory access locality through specialized memory managers and partial breadth-first expansion, and on improving processor utilization through dynamic load balancing. The results on a shared memory system show speedups of over two on four processors and speedups of up to four on eight processors. The measured results clearly identify the main source of bottlenecks and point out some intereeting directions for further improvements.