Constraint Length Research Articles

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates.

Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

Improvement of noise immunity of satellite DVB channel

This article presents the results of a study on the noise immunity of satellite DVB channels. Dependencies which determine the error probability at the decoder output are presented taking into consideration the parameters of the used RS, convolutional, BCH and LDPC codes and the error probability at the decoder input. Research of the influence of the packet length, constraint length and code rate on the BER characteristics of Reed-Solomon and convolutional decoder is conducted. The values of the parameters under research, at which the highest code effectiveness is achieved, are determined following an analysis of the results. Investigations have been carried out to determine the influence of the BCH packets length, the BCH code rate, the parameters of LDPC parity-check matrix and the number of iteration in the LDPC decoder on the radio channel noise immunity. BER characteristics of satellite DVB channels are presented upon using concatenated RS-convolutional and BCH-LDPC codes with optimised parameters and are compared to the standard ones for such systems.

Performance Analysis of the Multiband Orthogonal Frequency Division Multiplexing Ultra-Wideband Systems for Multipath Fading and Multiuser Interference Channels

This paper presents the performance analysis of the multiband orthogonal frequency division multiplexing (MB-OFDM) ultra-wideband (UWB) systems for multipath fading and multiuser interference channels. A closed form approximation of the BER performance of the MB-OFDM UWB system with multiple interferences is proposed. Based on the derived approximation, the effects on the BER performance for the choice of the codeword constraint lengths of the convolutional encoder, the length of the cyclic prefix, and the multiuser environments of two or more interferers are thoroughly discussed. Four UWB multipath fading channels are also investigated for the BER performance of the MB-OFDM UWB system. The simulated results provide us with useful information to appropriately choose the parameters of the MB-OFDM UWB system for the sake of achieving the BER performance that conforms to requirement of the FCC standards.

Turbo codes for multi-hop wireless sensor networks with decode-and-forward mechanism

Wireless channels are prone to many impairments, such as noise and fading. Weak channels between the nodes in the wireless sensor network (WSN) can cause reception of erroneous packets. Retransmission mechanisms are mainly used to tackle the problem of erroneous reception in WSN communication protocols. Weak channels can cause high number of retransmissions in order to deliver a packet correctly, which will consume high energy of both the transmitting and the receiving nodes. Error correcting codes (ECCs) can be used to reduce number of retransmissions, but most ECCs have complex decoding algorithms, which leads to high processing energy consumption at the receiving nodes in the WSN. In this paper, we present a low power consumption decode-and-forward approach for the multi-hop WSNs; a serial concatenation convolutional codes (SCCC) encoder is implemented at the source node while the complex iterative decoding algorithm is shifted to the sink (base station). The intermediate nodes run a Viterbi decoding algorithm to decode only the inner code of the SCCC encoder. We investigate the effect of changing constraint length of both the inner and the outer codes and the effect of changing encoding block size. We show that most packets can be decoded at the base station at low signal-to-noise ratio (SNR) channels with the penalty of small energy loss in decoding the packet at the nodes in the network.

Blind reconstruction of convolutional code based on segmented Walsh-Hadamard transform

Walsh-Hadamard transform(WHT) can solve linear error equations on Field F2, and the method can be used to recover the parameters of convolutional code. However, solving the equations with many unknowns needs enormous computer memory which limits the application of WHT. In order to solve this problem,a method based on segmented WHT is proposed in this paper. The coefficient vector of high dimension is reshaped and two vectors of lower dimension are obtained. Then the WHT is operated and the requirement for computer memory is much reduced. The code rate and the constraint length of convolutional code are detected from the Walsh spectrum. And the check vector is recovered from the peak position. The validity of the method is verified by the simulation result, and the performance is proved to be optimal.

Space‐time QAM wireless MISO systems employing differentially coded in‐/out‐FECC SCQICs over slow‐fading Jakes scattering mobile radio links

This study presents research that supplements and extends the previous works on design of space-time fully systematic unpunctured (FSU) serial concatenation of quadratic interleaved codes (SCQICs). The requirements for efficient design of the forward error correction (FEC) codecs motivated potential information-theoretic studies for enjoying the development of low-complex system components within the FEC encoder/decoder for securing the transmission reliability. Inspired by this motivation, this study not only provides design guidelines to achieve better bit error rate performance in terms of the major design factors of FSU-SCQICs, that is, component code constraint length and trellis structure, and FEC rate, but also estimates the gain gaps of different quadratic permutation (QP) structures in two crucial untouched aspects: (i) signal-to-noise ratio-region comparison on the optimality and (ii) investigation on the structural parameters of QPs, that is, cyclic shift and primitive factor.

Performance Analysis of Viterbi Decoder for Wireless Applications

Viterbi decoder is employed in wireless communication to decode the convolutional codes; those codes are used in every robust digital communication systems. Convolutional encoding and viterbi decoding is a powerful method for forward error correction. This paper deals with synthesis and implementation of viterbi decoder with a constraint length of three as well as seven and the code rate of ½ in FPGA (Field Programmable Gate Array). The performance of viterbi decoder is analyzed in terms of resource utilization. The design of viterbi decoder is simulated using Verilog HDL. It is synthesized and implemented using Xilinx 9.1ise and Spartan 3E Kit. It is compatible with many common standards such as 3GPP, IEEE 802.16 and LTE.

On the efficient search of punctured convolutional codes with simulated annealing algorithm

Punctured convolution codes (PCCs) have a lot of applications in modern communication system. The efficient way to search for best PCCs with longer constraint lengths is desired since the complexity of exhaustive search becomes unacceptable. An efficient search method to find PCCs is proposed and simulated. At first, PCCs' searching problem is turned into an optimization problem through analysis of PCCs' judging criteria, and the inefficiency to use pattern search (PS) for many local optimums is pointed out. The simulated annealing (SA) is adapted to the non-convex optimization problem to find best PCCs with low complexity. Simulation indicates that SA performs very well both in complexity and success ratio, and PCCs with memories varying from 9 to 12 and rates varying from 2/3 to 4/5 searched by SA are presented.

Performance Analysis of Viterbi Decoder using different Digital Modulation Techniques in AWGN Channel

Error detection and correction has got a great practical importance in maintaining information (data) integrity across noisy channels. Convolutional encoding is considered as one of the forward error correction (FEC) schemes. A Viterbi decoder (VD) uses the Viterbi algorithm for decoding a bit stream that has been encoded using FEC based on a convolutional code. In this proposed work, a simulation of convolutional encoder and Viterbi decoder presented. This paper focuses on the performance study of Viterbi algorithm by varying parameters like constraint length, generating polynomials, traces back lengths and also modulation technique. The code rate considered is ½. In each case the Signal to Noise ratio (SNR) is varied from -2 to 6 and the computation of Bit Error Rate (BER) is performed.

Overhead Transmission Lines Deicing under Different Incentive Displacement

Overhead transmission line icing is one of the main factors affecting safety and reliability of power grid. This paper proposed an excitation deicing method of iced wire and theoretically revealed the ice removal mechanism under displacement excitation conditions, by taking the LGJ-70/10 glaze icing wire as the 3D model and analyzing and studying its dynamic response under the effect of displacement excitation. The simulation results show that the stress of wire icing area is enlarged with the increase of excitation displacement and frequency. Through the comparison of the compression strength experimental results on a series of different iced wires in low temperature environment, the authors found out that the stress generated from the wire icing area is greater than the crushing strength of the ice within the scope of the calculation parameters, which proved the validity and the feasibility of the method, and finally the suitable excitation displacement is determined. Following studies show that, as far as possible, it is necessary to reduce the incentive displacement and also to select the appropriate constraint length in order to avoid the line jumping that may be caused by large span ice shedding.

FPGA Implementation of Viterbi Algorithm for Decoding of Convolution Codes

Abstract: Convolutional code is a coding scheme used in communication systems including deep space communications and wireless communications. It provides an alternative approach to block codes for transmission over a noisy channel. The block codes can be applied only for the block of data. The Convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data. Viterbi decoder employed in digital wireless communication plays a rife role in the overall power consumption of trellis coded modulation decoder. Power reduction in Viterbi decoder could be achieved by reducing the number of states. A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis Viterbi decoder, this approach significantly reduces power consumption without degrading decoding speed. Convolutional encoding with viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN). It operates on data stream and has memory that uses previous bits to encode. The Viterbi Algorithm (VA) is proposed, used for decoding a bit stream that has been encoded using FEC code. The Convolutional encoder adds redundancy to a continuous stream of input data by using a linear shift register. A pre-computation architecture with Viterbi algorithm is implemented for this purpose, Viterbi (Convolutional) encoder and Viterbi decoder are designed and implemented using FPGA technology, which are the essential blocks in digital communication systems. It is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN. The Viterbi decoder of Constraint length 7 and code rate 1⁄2 is considered. The design is implemented using verilog on Xilinx Spartan 3E and advanced Spartan 6 board and the results and Comparisons are presented.

Re-configurable Optimized Area Turbo Decoder for Wireless Applications

Today, the wireless communication is an emanating requirement of day to day process. Due to the noisy environment in wireless communication there is a need of coding system, which can provide high data rate with error free communication. The turbo codes also known as Parallel Convolutional Concatenated Code (PCCC) provides high data rate with bit error rate performance improvement in communication system. With the advent demand of miniaturization, an area efficient turbo decoder of constraint length 3 is proposed in this paper. The turbo decoder used a single SISO (Soft Input Soft Output) decoder architecture in this paper to reduce the area consumption. The SOVA (Soft Output Viterbi Algorithm) is used as a decoding algorithm in SISO decoders. It is based on two step algorithm. The proposed design is simulated using Matlab and synthesized on Xilinx Virtex-2p (xc2vp30-ff896-5) FPGA. The performance of proposed Turbo decoder will be compared for FPGAs in terms of number of slice Flip-flops, LUTs and frequency. The Synthesis results show a 3% improvement in the utilized no. of slice flip-flop and 49% improvement in terms of frequency.

Design and Simulation of a Low Power Viterbi Decoder using Constraint Length Nine

Viterbi Decoder is the dominant module to determining the power consumption of the system. High speed and low power design of Viterbi Decoder with data rate1/2 and convolution encoding with a constraint length K = 9 is presented in this paper. The Proposed Viterbi decoder can be reduce the power consumption without reducing the decoding speed and also increases the length of the bits. The operating frequency of convolution encoder and Viterbi decoded is 306.65MHz and power consumption is 45.01Mw using Xpower tools in Xilinx and Spartan 3E FPGA kit.

Array Convolutional Low-Density Parity-Check Codes

This paper presents a design technique for obtaining regular time-invariant low-density parity-check convolutional (RTI-LDPCC) codes with low complexity and good performance. We start from previous approaches which unwrap a low-density parity-check (LDPC) block code into an RTI-LDPCC code, and we obtain a new method to design RTI-LDPCC codes with better performance and shorter constraint length. Differently from previous techniques, we start the design from an array LDPC block code. We show that, for codes with high rate, a performance gain and a reduction in the constraint length are achieved with respect to previous proposals. Additionally, an increase in the minimum distance is observed.

Performance of Reduced State S–T Trellis Coded MC-CDMA Systems

In this paper, performance of reduced state space-time trellis coded multi carrier code division multiple access (STTC-MC-CDMA) system is evaluated and compared with the performance of original state STTC-MC-CDMA system. The optimum decoding scheme, i.e., maximum likelihood sequence estimation is employed which uses Viterbi algorithm for decoding STTC code. To simplify the implementation of the STTC decoder, the number of states is reduced by reducing the constraint length of the STTC encoder using generating function technique. In this technique, the generator matrix of STTC code is minimized to reduce the number of states of S–T trellis decoder. It is observed that the performance loss in terms of frame error rate of the reduced state STTC-MC-CDMA system is negligible compared to the original state STTC-MC-CDMA system. It is also noted that by using the reduced state technique the STTC decoder can be made faster since it is having lower computational complexity.

Optimized BER Performance of Asymmetric Turbo Codes over AWGN Channel

The performance of the turbo codes can be improved by varying parameters such as block size, code polynomial structure and constraint length. This paper proposes a new asymmetric turbo codes that consists of parallel concatenated component codes with mixed type generator polynomials and also different constraint lengths. This scheme optimizes the BER performance of asymmetric turbo codes of both Waterfall region at lower SNR’s and error-floor region at higher SNR’s. The simulation results shows better BER performance of asymmetric turbo codes for block size of 128, 512 bits, code-rate of 1/2 and Maximum-A-Posteriori (MAP) decoding algorithm over AWGN channel with BPSK modulation by using MATLAB.

Viterbi Decoder Design of Beidou RDSS Receiver

Firstly, the convolutional encoding with constraint length of 7 is used as the channel coding scheme in Beidou RDSS system. In addition, in receiver design Viterbi Decoder serves as the decoder of convolutional encoding. Finally, the optimized design of hardware construction in traditional Viterbi compared with that in decoder is introduced to reduce hardware complexity.

Localized Dimension Growth: A Convolutional Random Network Coding Approach to Managing Memory and Decoding Delay

We consider an Adaptive Random Convolutional Network Coding (ARCNC) algorithm to address the issue of field size in random network coding for multicast, and study its memory and decoding delay performances through both analysis and numerical simulations. ARCNC operates as a convolutional code, with the coefficients of local encoding kernels chosen randomly over a small finite field. The cardinality of local encoding kernels increases with time until the global encoding kernel matrices at the related sink nodes have full rank. ARCNC adapts to unknown network topologies without prior knowledge, by locally incrementing the dimensionality of the convolutional code. Because convolutional codes of different constraint lengths can coexist in different portions of the network, reductions in decoding delay and memory overheads can be achieved. We show that this method performs no worse than block linear network codes in terms of decodability, and can provide significant gains in terms of average decoding delay or memory in combination, shuttle and random geometric networks.

An Efficient Low Power Viterbi Decoder Design using T-algorithm

This paper presents an efficient Low-Power Viterbi Decoder Design using T-algorithm. It implements the viterbi decoder using T-algorithm for decoding a bit-stream encoded by a corresponding forward error correction convolutional encoding system. A lot of digital communication systems incorporated a viterbi decoder for decoding convolutionally encoded data. The viterbi decoder is able to correct errors in received data caused by channel noise. We proposed an architecture implementing a Viterbi Decoder with Talgorithm deployed with threshold generator unit and purge unit to reduce the number of states which reduce power consumption. We propose modified architecture for the survivor Metric Unit to reduce the memory Access power during the trace back operation. The proposed viterbi decoder is carried out for rate-1/2 with a standard constraint length 7. The Synthesis results will be done using cadence RTL Encounter Tool. For ASIC synthesis, we use TSMC 45nm CMOS Process. The architecture which reduces the complexity and power Consumption by as much as 70% without effecting the decoding speed. General Terms

Log-Likelihood Ratio to Improve Hard DecisionViterbi Algorithm

Hard decision of Viterbi decoder suffer from the need of high Signal to Noise Ratio (SNR) to achieve reasonable Bit Error Rate (BER). For the purpose of improving the efficiency of its performance, it must increase the constraint length of the code, in this case highlights the problem of complexity in the structure. Several methods are used to solve this problem. In this paper the Log-Likelihood Ratio (LLR) with 3 bit soft decision and unquantized scheme has been implemented with simple transceiver using Convolutional codes. Results are achieved using the last version of Matlab (R2011b) illustrates that such scheme 2.7 dB over conventional system. In addition it has been examine such system with increasing the speed of data rate to double, the results of simulation confirm that it need 7 dB to achieve 10-6 BER.