Abstract Edge coded signaling (ECS) is a recently introduced communication protocol designed for single-channel signaling among constrained internet of things (IoT) nodes. This study aims to enhance the data rate of ECS, without increasing the clock frequency or power consumption. The goal is to develop an improved protocol that maintains the inherent advantages of ECS while achieving a higher data rate. The proposed solution, double data rate ECS (DDR-ECS), leverages both pulse edges of the ECS pulse stream for information encoding, drawing an analogy to DDR memory systems. The study presents a detailed design of low-power architecture for the DDR-ECS transceiver. This design was synthesized using a 65 nm ASIC process to evaluate its performance in terms of power consumption, gate count, and data rate. The synthesis results demonstrate that the DDR-ECS transceiver preserves the key features of ECS, including tolerance to clock frequency variations and compatibility with lightweight cryptographic algorithms. It effectively doubles the dynamic data rate to the range of 12–73.5 Mb/s while consuming an equivalent power of 13 μW and occupying a compact form factor of only 1,755 gates. The introduction of DDR-ECS represents a significant advancement in the ECS protocol, offering a novel approach to doubling the data rate without increasing the clock frequency or power envelope. This innovation retains the simplicity and efficiency of ECS, providing an enhanced communication solution for constrained IoT nodes.