Consecutive Bits Research Articles

Combined and General Methodologies of Key Space Partition for the Cryptanalysis of Block Ciphers

This paper proposes two new methods of key space partitioning for the cryptanalysis of block ciphers. The first one is called combined methodology of key space partition (CoMeKSPar), which allows us to simultaneously set some of the first and last consecutive bits of the key. In this way, the search is performed using the remaining middle bits. CoMeKSPar is a combination of two methods already proposed in the scientific literature, the Borges, Borges, Monier (BBM) and the Tito, Borges, Borges (TBB). The second method is called the general algorithm of key space reduction (GAKSRed), which makes it possible to perform a genetic algorithm search in the space formed by the unknown bits of the key, regardless of their distribution in the binary block. Furthermore, a method of attacking block ciphers is presented for the case where some key bits are known; the basic idea is to deduce some of the remaining bits of the block. An advantage of these methods is that they allow parallel computing, which allows simultaneous searches in different sub-blocks of key bits, thereby increasing the probability of success. The experiments are performed with the KLEIN (Small) lightweight block cipher using the genetic algorithm.

Optimal synchronization with binary marker for segmented burst deletion errors

In some telecommunication and magnetic/digital recording applications, bits/symbols tend to be lost in the transmission due to the interference. In this paper, we consider a segmented burst deletion channel where in a block of L consecutive bits at most a single burst deletion of length up to D bits exists. Existing synchronization approaches either provide a poor synchronization performance or suffer from a high computational complexity. For example, the reduced state Forward Backward Algorithm (FBA) incurs high time and space complexities, i.e., O(n32) and O(n), respectively, where n denotes the sequence length. In this paper, we discover binary marker patterns which require the minimum D+1 bits redundancy to detect the burst deletion with the length up to D bits for the segmented burst deletion channel, and propose an optimal algorithm to resynchronize the corrupted bit sequence that minimizes the expected bit error rate. As compared to the reduced state FBA, the time and space complexities of our proposed algorithm are reduced to O(n) and O(1), respectively. Theoretical analysis and simulations verify the optimality of our proposed algorithm, and demonstrate that the expected bit error rate introduced in our proposed scheme is lower than that in the existing synchronization error detection schemes and that in the FBA under segmented burst deletion channels.

Lattice attacks on pairing-based signatures

ABSTRACT Practical implementations of cryptosystems often suffer from critical information leakage through side-channels (such as their power consumption or their electromagnetic emanations). For public-key cryptography on embedded systems, the core operation is usually group exponentiation – or scalar multiplication on elliptic curves – which is a sequence of group operations derived from the private-key that may reveal secret bits to an attacker (on an unprotected implementation). We present lattice-based polynomial-time (heuristic) algorithms that recover the signer’s secret in popular pairing-based signatures when used to sign several messages under the assumption that blocks of consecutive bits of the corresponding exponents are known by the attacker. Our techniques rely upon Coppersmith's method and apply to many signatures in the so-called exponent-inversion framework in the standard security model (i.e. Boneh-Boyen, Gentry and Pontcheval-Sanders signatures) as well as in the random oracle model (i.e. Sakai-Kasahara signatures).

A skyrmion helicity-based multistate memory in synthetic antiferromagnets

Skyrmions in synthetic antiferromagnets (SAFs) are famous for being immune to the skyrmion Hall effect and hold the advantages of significantly higher speed for motion and smaller size than ferromagnetic systems. Therefore, skyrmions in SAFs are promising in spintronic devices. Here, we investigated the formation and in-plane-current-driven motion of bilayer skyrmions in the absence of Dzyaloshinskii–Moriya interaction by using micromagnetic simulations. Then, we studied the spacing variation between consecutive skyrmionic bits on the antiferromagnetic coupled nanotrack; it is found that there is an equilibrium distance between two Bloch skyrmions with opposite helicities. We also propose a reasonable method to distinguish skyrmions with opposite helicities. Finally, we displayed that the SAF skyrmion could pass through impurities due to topological protection. Based on these results, we designed the skyrmion helicity-based multistate memory devices in the SAF system, which have the advantages of high density and energy efficiency.

Reversible data hiding in encrypted image with local-correlation-based classification and adaptive encoding strategy

In recent years, reversible data hiding in encrypted images has attracted more and more attention due to its wide application in secret information transmission and image content protection. In this paper, we propose a reversible data hiding scheme for encrypted image based on classification and multi-layer processing. The image owner utilizes a block-level encryption method, including block-level bitwise exclusive-or operation and block permutation, to obtain encrypted image such that the correlation of pixels in most blocks is preserved. Therefore, there provably exist identical consecutive high-order bit planes (ICHOBPs) from the most significant bit (MSB) where the number of ICHOBPs is defined as local correlation. Further, a local-correlation-based classification mechanism is proposed such that these blocks can be classified into different types. The data hider adopts multi-layer processing to fully exploit the local correlation in each block. First, ICHOBPs of each block are utilized as redundant space for data embedding. For those blocks with a small number of ICHOBPs, an adaptive coding strategy is proposed to improve embedding capacity. Especially for those blocks whose correlation is not well preserved, we propose a special processing method to exploit redundant space. Experimental results show that our method can effectively improve the embedding capacity than other similar ones with keeping high quality in security analysis.

Efficient Compression Methods for Wire-Spread-Based Stochastic Computing Deep Neural Networks

To accelerate the computation of deep neural networks (DNNs), their hardware implementations have been extensively explored. Stochastic computing (SC) is recognized as an efficient computing paradigm that can be adopted to design low-complexity architectures for DNNs. However, most of the reported SC-DNNs suffer from long latency. Recently, a novel SC scheme called wire spreading has been proposed to address the issue of latency, delivering fully parallel SC-DNN architectures. This brief aims to further reduce the hardware complexity of the wire-spread-based SC-DNNs (WSSC-DNNs). By investigating the bit distribution, we first propose a consecutive bit compression (CBC) method without introducing any accuracy loss. Moreover, another method called approximate compression (AC) is presented to reduce the number of wires at the expense of acceptable accuracy loss. These two compression methods are compatible and therefore can be utilized simultaneously. In the experiment for SqueezeNet on CIFAR10, it shows that the proposed methods can save up to 70.6% area cost and 67.0% power consumption.

FPGA implementation of high performance digital FIR filter design using a hybrid adder and multiplier

ABSTRACT The energetic growth in portable multimedia and mobile communication system has increased the requirement of high-speed signal processing system with compact area and power consumption. Finite impulse response(FIR) filters are broadly used in image, signal, speech and video signal processing, medical electronics, noise filtering, mobile communication and many other fields. The performance of the whole signal processing system with FIR filter depends on the basic building block of multiplier and adders. Hence, the hybrid FIR filter is proposed to improve the speed of the signal processing system using hybrid adder and hybrid multiplier. In this technique, the basic hybrid adder is designed with the help of 2-bit adders, BEC and 4:1 Multiplexer. Also, the hybrid multiplier is designed based on partial products of two consecutive multiplicand bits which are added at same time using Han-Carlson, Weinberger and Ling adder. The proposed FIR filter is functionally verified and synthesised using Xilinx ISE simulator and is implemented in Spartan 6 FPGA boards. The result shows that the delay of FIR filter using the proposed multiplier is improved by 26.51%, 15.59%, 15.83% and 2.79% as compared with CLA, conventional CSA, CSA-BK-BEC and the proposed adder with array multiplier, respectively.

High-Speed Hybrid Multiplier Design Using a Hybrid Adder with FPGA Implementation

The major role of electronic devices is providing low power dissipation and high speed with compact area. The speed of electronic devices depends on arithmetic operations. Multiplication is the important arithmetic operation in many VLSI signal processing applications. Hence, a high-speed multiplier is needed to design any signal processing module. Many multipliers are surveyed in the literature. They are Array, Wallace tree, booth, Vedic and Compressor-based multiplier. The speed of these multipliers depends on partial product accumulation. The hybrid parallel adder-based multiplier is proposed to improve the speed of multiplication compared to the existing technique. In this technique the partial products of, two consecutive bits (multiplicands), are added simultaneously with the help of a hybrid adder (Hancarlson, Weinberger and Ling adder). The proposed architecture is synthesized and simulated using Xilinx ISE 12.1 with various FPGA boards. Synthesized report shows that the speed of proposed multiplier (Spartan 6 FPGA implementation) is improved when compared to an Array multiplier (22.14%), Wallace tree multiplier (20.41%), Multiplier using compressor (13.89%), Vedic Multiplier using CLA (13.03%), Vedic Multiplier using RCA (3.54%), Modified Booth multiplier (4.42%) and Vedic Multiplier using HCA with BEC (3.28%).

A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers

This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (Nm). To overcome this limitation, the proposed system includes a frequency calibration circuit, which reduces the frequency mismatch to ±0.5%, thus enabling the WuRx to be used with different encoding techniques up to Nm = 100. A full WuRx prototype, including an always-on clockless AFE operating in subthreshold, was fabricated with STMicroelectronics 90 nm BCD technology. The WuRx is supplied with 0.6 V, and the power consumption, excluding the calibration circuit, is 12.8 nW during the rest state and 17 nW at a 1 kbps data rate. With a 1 kbps On-Off Keying (OOK) modulated input and −35 dBm of input RF power after the input matching network (IMN), a 10−3 missed detection rate with a 0 bit error tolerance is measured, transmitting 63 bit packets with the Nm ranging from 1 to 63. The total sensitivity, including the estimated IMN gain at 100 MHz and 433 MHz, is −59.8 dBm and −52.3 dBm, respectively. In comparison with an ideal CDR, the degradation of the sensitivity due to the GO-CDR is 1.25 dBm. False alarm rate measurements lasting 24 h revealed zero overall false wake-ups.

Simulating self-learning in photorefractive optical reservoir computers

Photorefractive materials exhibit an interesting plasticity under the influence of an optical field. By extending the finite-difference time-domain method to include the photorefractive effect, we explore how this property can be exploited in the context of neuromorphic computing for telecom applications. By first priming the photorefractive material with a random bit stream, the material reorganizes itself to better recognize simple patterns in the stream. We demonstrate this by simulating a typical reservoir computing setup, which gets a significant performance boost on performing the XOR on two consecutive bits in the stream after this initial priming step.

Rebuttal: On the Security of Reversible Data Hiding in Encrypted Images by MSB Prediction

Prior to the publication of our article in 2018, to our knowledge, there were no methods of achieving a favourable trade-off between the payload in bits-per-pixel (bpp) and the quality of the reconstructed image in terms of PSNR or SSIM. Indeed, a high payload value would lead to a degradation of the reconstructed image’s quality. Moreover, it should also be noted that almost all of the other state-of-the-art methods at the time, were based on Least Significant Bit (LSB) substitution and made little use of the redundancy between pixels in the clear domain to realize the data embedding of a secret message. In our proposed work <xref ref-type="bibr" rid="ref2" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[2]</xref> , we have taken the opposing view by developing a Most Significant Bits (MSB) prediction-based reversible data hiding in encrypted images (RDHEI) method. In the EPE-HCRDH approach, the original image is encrypted without modification and information about the location of all pixels which cannot be correctly predicted is embedded by MSB substitution. In order to localize the prediction errors, flags of consecutive bits equal to 1 are used. With this information, the data hider can detect all the bits which can be marked and substitute them with bits of a secret message. In this case, the payload is slightly lower than 1 bpp, but perfect reversibility is achieved. So, the proposed EPE-HCRDH approach provides a high payload with a little complexity. But as highlighted by Dragoi and Coltuc <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> , the fact of using flags, so that the data hider can embed a secret message introduces security flaws in the method. Despite this, the method has attracted the attention of many researchers, with 100 citations (according to Google Scholar on November 9, 2020) in several peer-reviewed journals of excellent reputation (IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY <xref ref-type="bibr" rid="ref3" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[3]</xref> , IEEE TRANSACTIONS ON MULTIMEDIA <xref ref-type="bibr" rid="ref4" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[4]</xref> – <xref ref-type="bibr" rid="ref5" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"/> <xref ref-type="bibr" rid="ref6" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"/> <xref ref-type="bibr" rid="ref7" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[7]</xref> , IEEE ACCESS <xref ref-type="bibr" rid="ref8" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[8]</xref> , IEEE TRANSACTIONS ON SIGNAL PROCESSING, and IEEE TRANSACTION ON DEPENDABLE AND SECURE COMPUTING <xref ref-type="bibr" rid="ref9" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[9]</xref> . Today, we can say that high capacity RDHEI has become a hot topic.

Properties and Constructions of Energy-Harvesting Sliding-Window Constrained Codes

We study properties and constructions of constrained binary codes that enable simultaneous energy and information transfer. We specifically study sliding-window constrained codes that guarantee that within any prescribed window of ℓ consecutive bits the constrained sequence has at least t, t > 1, 1's. We present a K-state source, K = ℓ choose t, that models the (ℓ, t) sliding-window constraint. We compute the information capacity of sliding-window (ℓ, t)-constrained sequences. We design efficient coding techniques for translating source data into sliding-window (ℓ, t)-constrained sequences.

DMole: A Novel Transreceiver for Mobile Molecular Communication Using Robust Differential Detection Techniques.

This paper proposes two differential detection techniques for signal detection in mobile molecular communication (MMC) for targeted drug delivery (TDD) application. In MMC, a nano-transmitter and a nano-receiver are considered to be in Brownian motion in an extracellular fluid medium. Transmitter uses calcium molecules to communicate with the receiver. Detection is performed using concentration difference based detector (CDD) at the receiver which calculates the maximum absolute concentration difference of the received signal within the same bit interval to detect the bit. This improves the bit error rate (BER) performance in MMC. The performance is further enhanced using manchester coded transmission with differential detection (MCD). In MCD, Bit-1 is coded by the symbol [1 0] and Bit-0 is coded by the symbol [0 1] and the difference between peaks of signals received in consecutive bit duration is taken to detect the bit. Simulation results prove that the MCD technique is 3 dB less sensitive to inter symbol interference (ISI) than the CDD technique. The detection threshold is selected using maximum a posteriori probability (MAP) rule. The performance of these detectors is compared with other existing detection techniques. Results reveal that BER performance of the CDD and MCD better by at least 3 dB and 6 dB, respectively. The proposed CDD and MCD techniques perform better in different bit-sequence length, various initial distance and different bit duration than other existing techniques.

Block Codes for Energy-Harvesting Sliding-Window Constrained Channels

Energy-harvesting sliding-window constrained block codes guarantee that within any prescribed window of ℓ consecutive bits the constrained sequence has at least t, t ≥ 1, 1's. Prior art code design methods build upon the finite-state machine description of the (ℓ, t) constraint, but as the number of states equals I choose t, a code design becomes prohibitively complex for mounting I and t. We present a new block code construction that circumvents the enumeration of codewords using a finite-state description of the (ℓ, t)-constraint. The codewords of the block code are encoded and decoded using a single look-up table. For (ℓ = 4, t = 2), the new block codes are maximal, that is, they have the largest possible number of codewords for its parameters.

Future 5G mmWave TV Service With Fast List Decoding of Polar Codes

The commercial deployment of 5G technology has brought new opportunities and challenges to digital broadcasting service. Digital broadcasting, together with other applications, will have to rely on 5G mmWave channel to transmit high quality signals. In mmWave band, channel coding is a key technology to ensure reliable information transmission and quality of service. This paper correspondingly proposes a fast simplified multi-bit successive cancellation list (Fast-SMSCL) decoding method for polar codes, with FPGA implementation details. Simulation study shows that our proposed method makes fully use of consecutive information bits and achieves prominent latency reduction compared to the conventional simplified multi-bit successive cancellation list decoding.

Amplified spontaneous emission based quantum random number generator

There is an increasing need for true random bits, for which true random number generators (TRNG) are absolutely necessary, because the output of pseudo random number generators is deterministically calculated from the previous states. We introduce our quantum number generator (QRNG) based on amplified spontaneous emission (ASE), a truly random quantum physical process. The experimental setup utilizes the randomness of the process. In this system, optical amplifiers (based on ASE) play the major role. The suitable sampling rate is selected in order to build the fastest generator, while avoiding the correlation between consecutive bits. Furthermore, the applied post-processing increases the quality of the random bits. As a results of this, our system generated random bits which successfully passed the NIST tests. Our real-time generation system – which is currently a trial version implemented with cheap equipment – will be available for public use, generating real time random bits using a web page.

Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation

In this paper, an adaptive approximation approach is proposed for the design of a divider and a square root (SQR) circuit. In this design, the division/SQR is computed by using a reduced-width divider/SQR circuit and a shifter by adaptively pruning some insignificant input bits. Specifically, for a $2n/n$2n/n division, $2k$2k and $k$k ($k<n$k<n) consecutive bits are selected starting from the most significant ‘1’ in the dividend and divisor, respectively. At the same time, redundant least significant bits (LSBs) are truncated or if the number of remaining bits after pruning is smaller than the number of bits to be kept, ‘0's are appended to the LSBs of the inputs. To avoid overflow, a $2(k+1)/(k+1)$2(k+1)/(k+1) divider is used to compute the $2k/k$2k/k division. Finally, an error correction circuit is proposed to recover the error caused by the shifter using OR gates. For a $2n$2n-bit approximate SQR circuit, similar pruning schemes are used to obtain a $2k$2k-bit radicand. A $2k$2k-bit SQR circuit and a shifter are then utilized to compute the SQR. This adaptive operation leads to very small maximum error distances of the approximate divider and SQR circuits, as shown by a theoretical error analysis. The proposed 16/8 approximate divider using an 8/4 exact array divider is $2.5\times$2.5× as fast but only consumes 34.42 percent of the power of the accurate design. Compared to the accurate 16-bit array SQR circuit, the approximate design with a 6-bit radicand is $3.9\times$3.9× as fast and consumes 20.66 percent of the power. The approximate SQR circuit using a 6-bit lookup table-based SQR circuit consumes 7.15 percent of the power of its corresponding accurate design. The proposed designs outperform other approximate designs in image processing applications including change detection (for the divider), envelope detection (for the SQR circuit) and image reconstruction (for both designs).

High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

This paper presents a novel baseband architecture that supports high-speed wireless VR solutions using 60 GHz RF circuits. Based on the experimental observations by our previous 60 GHz transceiver circuits, the efficient baseband architecture is proposed to enhance the quality of transmission. To achieve a zero-latency transmission, we define an (106,920, 95,040) interleaved-BCH error-correction code (ECC), which removes iterative processing steps in the previous LDPC ECC standardized for the near-field wireless communication. Introducing the block-level interleaving, the proposed baseband processing successfully scatters the existing burst errors to the small-sized component codes, and recovers up to 1080 consecutive bit errors in a data frame of 106,920 bits. To support the high-speed wireless VR system, we also design the massive-parallel BCH encoder and decoder, which is tightly connected to the block-level interleaver and de-interleaver. Including the high-speed analog interfaces for the external devices, the proposed baseband architecture is designed in 65 nm CMOS, supporting a data rate of up to 12.8 Gbps. Experimental results show that the proposed wireless VR solution can transfer up to 4 K high-resolution video streams without using time-consuming compression and decompression, successfully achieving a transfer latency of 1 ms.

Practical quantum private query of blocks based on the two-dimensional QKD system

Quantum private query of blocks (QPQB) allow user to obtain meaningful multiple consecutive bits in one query, which has certain advantages in improving communication efficiency and protecting user privacy. However, previous QPQB protocols generally show poor practicability for the use of high-dimensional quantum system (which is difficult to implement) or the ignorance of error correction (as a result, user may pay for a false database item). To solve this problem, we proposed a new fault-tolerant quantum protocol for private query of blocks based on the two-dimensional quantum system, by using a special reorder-shift-addition technique. This technology can not only compress user’s additional information obtained in error correction, but also can reduce the user’s advantage obtained from the alignment of the key bits in bitwise adding, solving an inherent security problem in postprocessing. Moreover, our protocol is loss tolerant and can resist the quantum memory attack.

Interference Mitigation in Large-Scale Multiuser Molecular Communication

In recent years, communicating information using molecules via diffusion has attracted significant interest in bio-medical applications. To date, most of the studies have concentrated on point-to-point molecular communication (MC), whereas in a realistic environment, multiple MC transmitters are likely to transmit molecular messages simultaneously sharing the same propagation medium, resulting in significant performance variation of the MC system. In this type of large-scale MC system, the collective signal strength at the desired receiver can be impaired by the interference caused by other MC transmitters, which may degrade the system reliability and efficiency. This paper presents the first tractable analytical framework for the collective signal strength at a partially absorbing receiver due to the desired transmitter under the impact of a swarm of interfering transmitters in a 3D large-scale MC system using stochastic geometry. To combat the multi-user interference and the intersymbol interference (ISI) in the multi-user environment, we propose Reed–Solomon (RS) error correction coding, due to its high effectiveness in combating burst and random errors, as well as the two types of information molecule modulating scheme, where the transmitted bits are encoded using two types of information molecules at consecutive bit intervals. We derive analytical expressions for the bit error probability (BEP) of the large-scale MC system with the proposed two schemes to show their effectiveness. The results obtained using Monte Carlo simulations, match exactly with the analytical results, justifying the accuracy of the derivations. Results reveal that both schemes improve the BEP by a factor of 3–4 compared with that of a conventional MC system without using any ISI mitigation techniques. Due to the implementation simplicity, the two-type molecule encoding scheme is better than the RS error correction coding scheme, as the RS error correction coding scheme involves additional encoding and decoding process at both the transmitter and receiver nodes. Furthermore, the proposed analytical framework can be generalized to the analysis of other types of receiver designs and performance characterization in multi-user large-scale MC systems. Also, the two types of information molecule modulating scheme can be extended to M-type of information molecule modulating scheme without loss of generality.